On 6/11/2024 3:58 PM, Tvrtko Ursulin wrote:
On 10/06/2024 10:24, Nirmoy Das wrote:
Hi Andi,
On 6/7/2024 4:51 PM, Andi Shyti wrote:
The forcewake count and domains listing is multi process critical
and the uncore provides a spinlock for such cases.
Lock the forcewake evaluation section
, below seems to be correct one.
Fixes: 9dd4b065446a ("drm/i915/gt: Move pm debug files into a gt aware
debugfs")
Cc: # v5.6+
Reviewed-by: Nirmoy Das
Regards,
Nirmoy
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4
1 file changed, 4 insertions(+)
diff --git a/d
On 5/24/2024 1:58 AM, Andi Shyti wrote:
Following the guidelines it takes 3 seconds to perform an FLR
reset. Let's give it a bit more slack because this time can
change depending on the platform and on the firmware
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
Hi,
In this second
Hi Andi,
On 5/21/2024 12:56 PM, Andi Shyti wrote:
Hi Nirmoy,
On Fri, May 17, 2024 at 10:13:37PM +0200, Nirmoy Das wrote:
Hi Andi,
On 5/17/2024 9:34 PM, Andi Shyti wrote:
Hi Nirmoy,
On Fri, May 17, 2024 at 04:00:02PM +0200, Nirmoy Das wrote:
On 5/17/2024 1:25 PM, Andi
Hi Andi,
On 5/17/2024 9:34 PM, Andi Shyti wrote:
Hi Nirmoy,
On Fri, May 17, 2024 at 04:00:02PM +0200, Nirmoy Das wrote:
On 5/17/2024 1:25 PM, Andi Shyti wrote:
If we timeout while waiting for an FLR reset, there is nothing we
can do and i915 doesn't have any control on it. In any case
Hi Andi,
On 5/17/2024 1:25 PM, Andi Shyti wrote:
If we timeout while waiting for an FLR reset, there is nothing we
can do and i915 doesn't have any control on it. In any case the
system is still perfectly usable
If a FLR reset fails then we will have a dead GPU, I don't think the GPU
is
On 5/17/2024 1:53 PM, Jani Nikula wrote:
On Fri, 17 May 2024, Nirmoy Das wrote:
Hi Jani,
On 5/17/2024 9:39 AM, Jani Nikula wrote:
On Thu, 16 May 2024, Nirmoy Das wrote:
The previous commit 'commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick
"previous commit" is a fairly vague
Hi Jani,
On 5/17/2024 9:39 AM, Jani Nikula wrote:
On Thu, 16 May 2024, Nirmoy Das wrote:
The previous commit 'commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick
"previous commit" is a fairly vague reference once this gets
committed. It's not going to be "previous"
han Cavitt
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
index 65a931ea80e9..3527b8f44
Simplify child iteration using for_each_child macro
instead of using manual for loop. There is no functional
change.
Cc: John Harrison
Cc: Tvrtko Ursulin
Signed-off-by: Nirmoy Das
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 64 ++-
1 file changed, 33 insertions(+), 31
: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
Also need Cc: # v5.2+
With those:
Reviewed-by: Nirmoy Das
Nirmoy
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
On 5/7/2024 7:10 PM, Rodrigo Vivi wrote:
On Tue, May 07, 2024 at 10:54:11AM +0200, Janusz Krzysztofik wrote:
On Tuesday, 7 May 2024 09:30:15 GMT+2 Nirmoy Das wrote:
Hi Janusz,
Just realized we need Fixes tag for this.
Fixes: 1f33dc0c1189 ("drm/i915: Remove extra multi-gt pm-refer
figurations, where a VMA we reopen may be handled by a
GT different from the one that we already keep active via its engine while
we set up an execbuf request.
Restoring the extra GT0 PM wakeref removed from i915_gem_do_execbuffer()
processing path seems to fix this issue.
Clo
est.
Restoring the extra GT0 PM wakeref removed from i915_gem_do_execbuffer()
processing path seems to fix this issue.
Closes:https://gitlab.freedesktop.org/drm/intel/-/issues/10608
Signed-off-by: Janusz Krzysztofik
Cc: Rodrigo Vivi
Cc: Nirmoy Das
Reviewed-by: Nirmoy Das
---
drivers/gpu/d
Hi Janusz,
On 4/16/2024 6:40 PM, Rodrigo Vivi wrote:
On Tue, Apr 16, 2024 at 10:09:46AM +0200, Janusz Krzysztofik wrote:
Hi Rodrigo,
On Tuesday, 16 April 2024 03:16:31 CEST Rodrigo Vivi wrote:
On Mon, Apr 15, 2024 at 09:53:09PM +0200, Janusz Krzysztofik wrote:
We defer actually closing,
are no more engines awake,
disarm the breadcrumb and go to sleep.
Fixes: 9d5612ca165a ("drm/i915/gt: Defer enabling the breadcrumb interrupt to after
submission")
Closes: https://gitlab.freedesktop.org/drm/intel/issues/10026
Signed-off-by: Chris Wilson
Cc: Andrzej Hajda
Cc: # v
Hi Andi,
On 4/23/2024 11:32 AM, Andi Shyti wrote:
Hi Nirmoy,
On Mon, Apr 22, 2024 at 10:19:51PM +0200, Nirmoy Das wrote:
Currently intel_gt_reset() kills the GuC and then resets requested
engines. This is problematic because there is a dedicated CSB FIFO
which only GuC can access
i
Do we have a IGT for partial FB mmap test ? Would be nice to have one
but this patch looks good to me.
Reviewed-by: Nirmoy Das
Regards,
Nirmoy
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
Hi Andi,
On 4/17/2024 12:49 AM, Andi Shyti wrote:
For the upcoming changes we need a cleaner way to build the list
of uabi engines.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
---
Hi,
just sending this patch to unburden the coming series from this
single patch inherited from a
should be killed only after resetting
the requested engines and before calling intel_gt_init_hw().
v2: Improve commit message(John)
Cc: John Harrison
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_reset.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff
-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 35
Hi John,
On 4/19/2024 1:38 AM, John Harrison wrote:
On 4/18/2024 10:10, Nirmoy Das wrote:
Currently intel_gt_reset() happens as follows:
reset_prepare() ---> Sends GDRST to GuC, GuC is in GS_MIA_IN_RESET
do_reset()
intel_gt_reset_all_engines()
*_engine_reset_prepare() -->RES
Hi John,
On 4/19/2024 1:27 AM, John Harrison wrote:
On 4/18/2024 10:10, Nirmoy Das wrote:
intel_engine_reset() not only reset a engine but also
tries to recover it so give it a proper name without
any functional changes.
Not seeing what the difference is. If this was a super low level
Hi John.
On 4/19/2024 1:27 AM, John Harrison wrote:
On 4/18/2024 10:10, Nirmoy Das wrote:
__intel_gt_reset() is really for resetting engines though
the name might suggest something else. So add two helper functions
to remove confusions with no functional changes.
Technically you only added one
_IN_RESET with FW loaded.
Fix the issue by sanitizing the GuC only after resetting requested
engines and before intel_gt_init_hw().
Note intel_uc_reset_finish() and intel_uc_reset() are nop when
guc submission is disabled.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_res
intel_engine_reset() not only reset a engine but also
tries to recover it so give it a proper name without
any functional changes.
Signed-off-by: Nirmoy Das
---
.../drm/i915/gem/selftests/i915_gem_context.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt
__intel_gt_reset() is really for resetting engines though
the name might suggest something else. So add two helper functions
to remove confusions with no functional changes.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
.../drm/i915/gt
Hi John,
On 4/17/2024 2:37 AM, John Harrison wrote:
On 4/15/2024 09:44, Nirmoy Das wrote:
Currently intel_gt_reset() happens as follows:
reset_prepare() ---> Sends GDRST to GuC, GuC is in GS_MIA_IN_RESET
do_reset()
__intel_gt_reset()
*_engine_reset_prepare() -->RESET_CTL e
, 0, SZ_2M);
Do we need this extra memset() ? Otherwise
Reviewed-by: Nirmoy Das
+ munmap(ptr_b, SZ_2M);
+ }
+
+ gem_close(i915, handle);
+}
+
static int mmap_gtt_version(int i915)
{
int gtt_version = -1;
@@ -931,6 +1010,11 @@ igt_main
-by: Balasubramani Vivekanandan
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
.../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++
drivers/gpu/drm/i915/display/intel_tdf.h | 25 +++
drivers/gpu/drm/xe/Makefile | 3 ++-
drivers/gpu
nit_hw() --> GuC FW loading happens, GuC comes out of
GS_MIA_IN_RESET.
Fix the above flow so that GuC reset happens after all the
engines reset is done.
Cc: John Harrison
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_reset.c | 9 --
drivers/gpu/drm/i915/gt/uc/intel_
Hi Andi,
On 3/29/2024 5:39 PM, Andi Shyti wrote:
To enable partial memory mapping of GPU virtual memory, it's
necessary to introduce an offset to the object's memory
(obj->mm.pages) scatterlist. This adjustment compensates for
instances when userspace mappings do not start from the beginning
of
Hi Bala,
On 4/3/2024 1:22 PM, Balasubramani Vivekanandan wrote:
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index modes on Xe2. The expectation is that KMD
needs to request transient data flush at the start of flip sequence
-wb-transient
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
.../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++
drivers/gpu/drm/i915/display/intel_tdf.h | 25
On 4/3/2024 1:22 PM, Balasubramani Vivekanandan wrote:
From: Matthew Auld
Needed in an upcoming patch, where we want GT level print, but only
which to trigger once to avoid flooding dmesg.
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Nirmoy Das
There is new fixup patch(PR#630) which modifies this patch. Could you
please bring that in as well.
Regards,
Nirmoy
On 4/3/2024 12:51 PM, Balasubramani Vivekanandan wrote:
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index
cular locking issue on busyness
flush")
Signed-off-by: John Harrison
Cc: Zhanjun Dong
Cc: John Harrison
Cc: Andi Shyti
Cc: Daniel Vetter
Cc: Daniel Vetter
Cc: Rodrigo Vivi
Cc: Nirmoy Das
Cc: Tvrtko Ursulin
Cc: Umesh Nerlige Ramappa
Cc: Andrzej Hajda
Cc: Matt Roper
Cc: Jonathan
ded. Limit it to DG2 onwards.
I would use "Limit it to platforms that need WAs" as those WA are only
needed till 12.71, otherwise
Reviewed-by: Nirmoy Das
Fixes: 9bb66c179f50 ("drm/i915: Reserve some kernel space per vm")
Signed-off-by: Andi Shyti
Cc: Andrzej Hajda
Hi Andi,
On 3/26/2024 12:12 PM, Andi Shyti wrote:
Hi Nirmoy,
...
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index a2195e28b625..57a2dda2c3cc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++
Hi Andi,
I have too many questions :) I think the patch makes sense but need more
context, see below:
On 3/25/2024 2:40 PM, Andi Shyti wrote:
To enable partial memory mapping of GPU virtual memory, it's
necessary to introduce an offset to the object's memory
(obj->mm.pages) scatterlist. This
the
total amount of the VM space. Add it back when the user requests
the GTT size through ioctl (I915_CONTEXT_PARAM_GTT_SIZE).
Fixes: 9bb66c179f50 ("drm/i915: Reserve some kernel space per vm")
Signed-off-by: Andi Shyti
Cc: Andrzej Hajda
Cc: Chris Wilson
Cc: Lionel Landwerlin
Cc: Micha
On 3/12/2024 3:55 PM, Jonathan Cavitt wrote:
We cannot write requests to objects without struct pages, so escape
early if the requests are bound to objects that lack them.
Signed-off-by: Jonathan Cavitt
---
v2: s/vma-obj/vma->obj
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 7 +++
i915: Reserve some kernel space per vm")
Signed-off-by: Andi Shyti
Cc: Andrzej Hajda
Cc: Chris Wilson
Cc: Lionel Landwerlin
Cc: Michal Mrozek
Cc: Nirmoy Das
Cc: # v6.2+
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/
On 3/12/2024 3:28 PM, Andi Shyti wrote:
Hi Nirmoy,
On Tue, Mar 12, 2024 at 12:18:15PM +0100, Nirmoy Das wrote:
Caching mode is HW dependent so pick a correct one using
intel_gt_coherent_map_type().
Cc: Andi Shyti
Cc: Janusz Krzysztofik
Cc: Jonathan Cavitt
Closes: https
Caching mode is HW dependent so pick a correct one using
intel_gt_coherent_map_type().
Cc: Andi Shyti
Cc: Janusz Krzysztofik
Cc: Jonathan Cavitt
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10249
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
per fix (Rodrigo).
Signed-off-by: Janusz Krzysztofik
Cc: Nirmoy Das
Cc: Rodrigo Vivi
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/
drm/intel/issues/8875
Signed-off-by: Janusz Krzysztofik
Cc: Thomas Hellström
Cc: Nirmoy Das
Cc: Andi Shyti
Cc: Rodrigo Vivi
Cc:sta...@vger.kernel.org # v5.19+
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_vma.c | 50 -
1 file changed, 43 insertions(
On 3/5/2024 3:35 PM, Janusz Krzysztofik wrote:
This reverts commit 7a2280e8dcd2f1f436db9631287c0b21cf6a92b0, obsoleted
by "drm/i915/vma: Fix UAF on destroy against retire race".
Signed-off-by: Janusz Krzysztofik
Cc: Nirmoy Das
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/
https://gitlab.freedesktop.org/drm/intel/issues/8875
Signed-off-by: Janusz Krzysztofik
Cc: Thomas Hellström
Cc: Nirmoy Das
Cc: Andi Shyti
Cc: Rodrigo Vivi
Cc: sta...@vger.kernel.org # v5.19+
---
drivers/gpu/drm/i915/i915_vma.c | 26 +++---
1 file changed, 19 insertions(+),
Hi Andi,
On 2/29/2024 4:28 PM, Andi Shyti wrote:
Hi Nirmoy,
On Thu, Feb 29, 2024 at 02:29:18PM +0100, Nirmoy Das wrote:
Add missing doc for struct drm_i915_reset_stats.
Cc: Andi Shyti
Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Thanks, merged to din.
Nirmoy
Thanks,
Andi
Add missing doc for struct drm_i915_reset_stats.
Cc: Andi Shyti
Signed-off-by: Nirmoy Das
---
include/uapi/drm/i915_drm.h | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2ee338860b7e
On 2/28/2024 2:24 PM, Tvrtko Ursulin wrote:
On 27/02/2024 09:26, Nirmoy Das wrote:
Hi Tvrtko,
On 2/27/2024 10:04 AM, Tvrtko Ursulin wrote:
On 21/02/2024 11:52, Nirmoy Das wrote:
Merged it to drm-intel-gt-next with s/check/Check
Shouldn't this have had:
Fixes: ed29c2691188 ("drm
Hi Tvrtko,
On 2/27/2024 10:04 AM, Tvrtko Ursulin wrote:
On 21/02/2024 11:52, Nirmoy Das wrote:
Merged it to drm-intel-gt-next with s/check/Check
Shouldn't this have had:
Fixes: ed29c2691188 ("drm/i915: Fix userptr so we do not have to worry
about obj->mm.lock, v7.")
Merged it to drm-intel-gt-next with s/check/Check
On 2/19/2024 1:50 PM, Nirmoy Das wrote:
Error in mmu_interval_notifier_insert() can leave a NULL
notifier.mm pointer. Catch that and return early.
Cc: Andi Shyti
Cc: Shawn Lee
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem
Hi Rodrigo,
On 2/19/2024 9:12 PM, Rodrigo Vivi wrote:
On Mon, Feb 19, 2024 at 01:50:47PM +0100, Nirmoy Das wrote:
Error in mmu_interval_notifier_insert() can leave a NULL
notifier.mm pointer. Catch that and return early.
Cc: Andi Shyti
Cc: Shawn Lee
Signed-off-by: Nirmoy Das
---
drivers/gpu
Error in mmu_interval_notifier_insert() can leave a NULL
notifier.mm pointer. Catch that and return early.
Cc: Andi Shyti
Cc: Shawn Lee
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem
Hi Janusz,
There seems to be a regression in CI related to this:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v2/bat-dg1-7/igt@gem_lmem_swapping@random-engi...@lmem0.html#dmesg-warnings1053
Please have a look.
Regards,
Nirmoy
On 1/24/2024 6:13 PM, Janusz Krzysztofik wrote:
On 1/19/2024 11:47 AM, Nirmoy Das wrote:
On 1/19/2024 12:12 AM, Ville Syrjälä wrote:
On Wed, Jan 17, 2024 at 06:46:24PM +0100, Nirmoy Das wrote:
On 1/17/2024 3:13 PM, Michał Winiarski wrote:
On Tue, Jan 16, 2024 at 09:56:25AM +0200, Ville Syrjala wrote:
From: Ville Syrjälä
Now
On 1/19/2024 12:12 AM, Ville Syrjälä wrote:
On Wed, Jan 17, 2024 at 06:46:24PM +0100, Nirmoy Das wrote:
On 1/17/2024 3:13 PM, Michał Winiarski wrote:
On Tue, Jan 16, 2024 at 09:56:25AM +0200, Ville Syrjala wrote:
From: Ville Syrjälä
Now that the GGTT PTE updates go straight to GSMBASE
v2: Keep using MI_UPDATE_GTT on VM guests
Cc: Paz Zcharya
Cc: Nirmoy Das
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_g
Zcharya
Reviewed-by: Andrzej Hajda
Signed-off-by: Ville Syrjälä
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
b/drivers/gpu/drm/i915/display
On 1/16/2024 8:56 AM, Ville Syrjala wrote:
From: Ville Syrjälä
0x108100 and 0x1080c0 have been around since snb. Rename the
defines appropriately.
Cc: Paz Zcharya
Reviewed-by: Andrzej Hajda
Signed-off-by: Ville Syrjälä
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem
a working
display now depends on a lot more extra components working correctly
TODO: MI_UPDATE_GTT might be interesting as an optimization
though, so perhaps someone should look into always using it
(assuming the GPU is alive and well)?
v2: Keep using MI_UPDATE_GTT on VM guests
Cc: Paz Zcharya
Cc:
setup. Once
command submission is up we should switch to MI_UPDATE_GTT
which at least shouldn't hang the whole machine.
v2: Don't use direct GSM/DSM access on guests
Add w/a number
Cc: Paz Zcharya
Cc: Nirmoy Das
Cc: Joonas Lahtinen
Reviewed-by: Andrzej Hajda
Reviewed-by: Radhakrishna Sripada
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 3 ---
2 files changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index d2440c793f84
ej Hajda
Signed-off-by: Ville Syrjälä
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_fbdev_fb.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 17 +
drivers/gpu/drm/i915/gem/i915_gem_ttm.c
-by: Nirmoy Das
---
drivers/gpu/drm/i915/intel_memory_region.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index b2708f8cac2a..52d998e5c21a 100644
--- a/drivers/gpu/drm/i915
On 1/12/2024 4:12 PM, Ville Syrjälä wrote:
On Wed, Jan 10, 2024 at 11:49:47AM +0100, Nirmoy Das wrote:
Hi Ville,
Apologies, but I lost track of this series after I returned from sick leave.
On 12/15/2023 11:59 AM, Ville Syrjala wrote:
From: Ville Syrjälä
On MTL accessing stolen memory via
On 1/10/2024 11:49 AM, Nirmoy Das wrote:
Hi Ville,
Apologies, but I lost track of this series after I returned from sick
leave.
Please ignore the uncontextual "but" in the previous response. I need to
disable auto correct options.
Regards,
Nirmoy
On 12/15/2023 11:59
/a numbers and whatnot
Cc: Paz Zcharya
Cc: Nirmoy Das
Cc: Radhakrishna Sripada
Cc: Joonas Lahtinen
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 11 ++-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 13 -
2 files changed, 22 insertions(+), 2
On 12/6/2023 9:46 PM, Andi Shyti wrote:
Get the guc reference from the ce using the ce_to_guc() helper.
Just a leftover from previous cleanups.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion
On 12/6/2023 9:46 PM, Andi Shyti wrote:
Get the guc reference from the gt using the gt_to_guc() helper.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_debugfs_params.c | 2 +-
drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.c | 4
On 12/6/2023 9:46 PM, Andi Shyti wrote:
Get the guc reference from the gt using the gt_to_guc() helper.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 4 +--
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 3 +-
drivers/gpu/drm
/ directory.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 9 +++--
drivers/gpu/drm/i915/gt/intel_gt.h| 5 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 6
Hi John,
On 12/5/2023 8:50 PM, John Harrison wrote:
On 12/5/2023 02:39, Nirmoy Das wrote:
Hi John,
On 12/5/2023 10:10 AM, John Harrison wrote:
On 12/5/2023 00:52, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases
Hi Tvrtko,
On 12/5/2023 11:05 AM, Tvrtko Ursulin wrote:
On 05/12/2023 08:50, Nirmoy Das wrote:
Hi Tvrtko,
On 12/5/2023 9:34 AM, Tvrtko Ursulin wrote:
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some
Hi John,
On 12/5/2023 10:10 AM, John Harrison wrote:
On 12/5/2023 00:52, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Convert the log to a trace log for debugging without
commit message(Tvrtko)
Cc: Tvrtko Ursulin
Cc: John Harrison
Cc: Andi Shyti
Cc: Andrzej Hajda
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5591
Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_reset.c | 8
1
Hi Tvrtko,
On 12/5/2023 9:34 AM, Tvrtko Ursulin wrote:
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Let the caller of gen8_engine_reset_prepare
Harrison
Cc: Andi Shyti
Cc: Andrzej Hajda
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5591
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_reset.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers
On 11/15/2023 1:10 PM, Andrzej Hajda wrote:
Trace requires new-line at the end of message (in opposition to printk),
otherwise trace dump becomes messy.
Signed-off-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +-
1 file changed, 1 insertion
://gitlab.freedesktop.org/drm/intel/-/issues/8489
Fixes: bec68cc9ea42d8 ("drm/i915: Prepare for multiple GTs")
Signed-off-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
- Link to v1:
https://lore.kernel.org/r/20231114-dont_clean_gt_on_error_path-v1-1-37f2fa827...@intel.com
---
drive
On 11/6/2023 1:45 PM, Jani Nikula wrote:
On Wed, 25 Oct 2023, Nirmoy Das wrote:
Handle platforms with multiple GTs by iterate over all GTs.
Add a Fixes commit so this gets propagated for MTL support.
Fixes: 213c43676beb ("drm/i915/mtl: Remove the 'force_probe' requirement for Meteor
On 10/31/2023 3:18 PM, Jani Nikula wrote:
On Tue, 31 Oct 2023, Nirmoy Das wrote:
On 10/31/2023 1:45 PM, Jani Nikula wrote:
+void i915_gpu_error_debugfs_register(struct drm_i915_private *i915)
+{
+ struct drm_minor *minor = i915->drm.primary;
+
+ debugfs_create_f
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_gpu_error.c | 75 -
drivers/gpu/drm/i915/i915_gpu_error.h | 17 +++---
drivers/gpu/drm/i915/i915_sysfs.c | 79 +--
3 files changed, 86 insertions(+), 85 deletions(-)
diff --git
te_read,
+ .write = i915_error_state_write,
+ .llseek = default_llseek,
+ .release = gpu_state_release,
+};
+
+void i915_gpu_error_debugfs_register(struct drm_i915_private *i915)
+{
+ struct drm_minor *minor = i915->drm.primary;
+
+ debugfs_create_file(&qu
On 10/31/2023 1:45 PM, Jani Nikula wrote:
Not needed outside of i915_gpu_error.c.
Signed-off-by: Jani Nikula
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_gpu_error.c | 8
drivers/gpu/drm/i915/i915_gpu_error.h | 5 -
2 files changed, 4 insertions(+), 9 deletions
On 10/31/2023 11:57 AM, Nirmoy Das wrote:
merged to drm-next
Sorry, drm-intel-next not drm-next.
Regards,
Nirmoy
Thanks,
Nirmoy
On 10/25/2023 3:12 PM, Andrzej Hajda wrote:
On 25.10.2023 12:28, Nirmoy Das wrote:
Handle platforms with multiple GTs by iterate over all GTs.
Add
merged to drm-next
Thanks,
Nirmoy
On 10/25/2023 3:12 PM, Andrzej Hajda wrote:
On 25.10.2023 12:28, Nirmoy Das wrote:
Handle platforms with multiple GTs by iterate over all GTs.
Add a Fixes commit so this gets propagated for MTL support.
Fixes: 213c43676beb ("drm/i915/mtl: R
This is now merged to gt-next
Thanks,
Nirmoy
On 10/18/2023 4:04 PM, Nirmoy Das wrote:
On 10/18/2023 3:00 PM, Andi Shyti wrote:
Hi Nirmoy,
gen8_ggtt_invalidate() is only needed for limited set of platforms
where GGTT is mapped as WC. This was added as way to fix WC based
GGTT in
commit
_name, and fix tc mem leak(Imre)
Fixes: 3eafcddf766b ("drm/i915/tc: Move TC port fields to a new intel_tc_port
struct")
Cc: Mika Kahola
Cc: Imre Deak
Cc: Jani Nikula
Signed-off-by: Nirmoy Das
Reviewed-by: Andrzej Hajda
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_t
On 10/26/2023 12:11 PM, Imre Deak wrote:
On Thu, Oct 26, 2023 at 12:05:13PM +0300, Imre Deak wrote:
On Wed, Oct 25, 2023 at 07:08:34PM +0200, Nirmoy Das wrote:
Fix below compiler warning:
intel_tc.c:1879:11: error: ‘%d’ directive output may be truncated
writing between 1 and 11 bytes
"drm/i915/tc: Move TC port fields to a new intel_tc_port
struct")
Cc: Mika Kahola
Cc: Imre Deak
Cc: Jani Nikula
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_tc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/displa
On 10/25/2023 5:45 PM, Imre Deak wrote:
On Wed, Oct 25, 2023 at 03:57:26PM +0200, Nirmoy Das wrote:
Fix below compiler warning:
intel_tc.c:1879:11: error: ‘%d’ directive output may be truncated
writing between 1 and 11 bytes into a region of size 3
[-Werror=format-truncation=]
"%c/
xxx(), but it didn't develop further.
Reviewed-by: Nirmoy Das
Thanks,
Andi
guc_to_gt(guc)->i915;
+}
+
We don't want inline functions in headers files[1]. Otherwise the series
looks fine to me:
Reviewed-by: Nirmoy Das
[1] https://patchwork.freedesktop.org/series/124069/
Regards,
Nirmoy
void intel_gt_common_init_early(struct intel_gt *gt);
int intel_ro
915/tc: Fix -Wformat-truncation in
intel_tc_port_init")
intel_tc_port struct")
Cc: Mika Kahola
Cc: Imre Deak
Cc: Jani Nikula
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/i
ko Ursulin
Cc: Andi Shyti
Cc: Andrzej Hajda
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_debugfs_params.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs_params.c
b/drivers/gpu/drm/i915/i915_debugfs_params.c
index 61
) += \
+ display/intel_display_debugfs.o \
+ display/intel_pipe_crc.o
From a quick look, I am not sure how this file is related to debugfs. I
will try to find out but that is
unrelated to this patch so
Reviewed-by: Nirmoy Das
# modesetting output/encoder code
i915-y += \
On 10/24/2023 3:04 PM, Jani Nikula wrote:
Unify the line continuations and indents, and sort the build lists.
Signed-off-by: Jani Nikula
---
Note: This is easiest to review by applying and looking at 'git show -w'
Thanks for the hint :)
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm
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