Em seg, 2020-07-20 às 17:01 +0530, Karthik B S escreveu:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
>
> Enable the flip done interrupt in IER.
>
> Enable flip done function is called before writing the
> surface address
Em seg, 2020-07-20 às 17:01 +0530, Karthik B S escreveu:
> Set the Async Address Update Enable bit in plane ctl
> when async flip is requested.
>
> v2: -Move the Async flip enablement to individual patch (Paulo)
>
> v3: -Rebased.
>
> v4: -Add separate plane hook for async flip case (Ville)
>
>
Em seg, 2020-07-20 às 17:01 +0530, Karthik B S escreveu:
> Without async flip support in the kernel, fullscreen apps where game
> resolution is equal to the screen resolution, must perform an extra blit
> per frame prior to flipping.
>
> Asynchronous page flips will also boost the FPS of Mesa
Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
>
> Enable the flip done interrupt in IER.
>
> Enable flip done function is called before writing the
> surface address
Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
> Without async flip support in the kernel, fullscreen apps where game
> resolution is equal to the screen resolution, must perform an extra blit
> per frame prior to flipping.
>
> Asynchronous page flips will also boost the FPS of Mesa
Em seg, 2020-04-20 às 15:17 +0530, Karthik B S escreveu:
> Make the commit call blocking in case of async flips
> so that there is no delay in completing the flip.
>
I'm trying to understand the code. Can you please elaborate more here
in this commit message? Why exactly does the call need to
Em seg, 2020-04-20 às 15:17 +0530, Karthik B S escreveu:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
>
> Enable the flip done interrupt in IER.
>
> Enable flip done function is called before writing the
> surface address
Em seg, 2020-04-20 às 15:17 +0530, Karthik B S escreveu:
> Enable asynchronous flips in i915 for gen9+ platforms.
>
> v2: -Async flip enablement should be a stand alone patch (Paulo)
... and at the very end of the series.
If someone is bisecting the Kernel for some problem unrelated to async
Em seg, 2020-04-20 às 15:17 +0530, Karthik B S escreveu:
> Support added only for async flips on primary plane.
> If flip is requested on any other plane, reject it.
>
> Make sure there is no change in fbc, offset and framebuffer modifiers
> when async flip is requested.
>
> If any of these are
Em sex, 2020-03-06 às 17:09 +0530, Karthik B S escreveu:
> Without async flip support in the kernel, fullscreen apps where game
> resolution is equal to the screen resolution, must perform an extra blit
> per frame prior to flipping.
>
> Asynchronous page flips will also boost the FPS of Mesa
Em sex, 2020-03-06 às 17:09 +0530, Karthik B S escreveu:
> Send the flip done event in the handler and disable the interrupt.
>
> Signed-off-by: Karthik B S
> ---
> drivers/gpu/drm/i915/i915_irq.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git
Em sex, 2020-03-06 às 17:09 +0530, Karthik B S escreveu:
> Support added only for async flips on primary plane.
> If flip is requested on any other plane, reject it.
>
> Signed-off-by: Karthik B S
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 29
> 1 file changed,
Em sex, 2020-03-06 às 17:09 +0530, Karthik B S escreveu:
> Enable support for async flips in I915.
> Set the Async Address Update Enable bit in plane ctl
> when async flip is requested.
>
> Signed-off-by: Karthik B S
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4
>
Em sex, 2020-03-06 às 17:09 +0530, Karthik B S escreveu:
> Add enable/disable flip done functions and enable
> the flip done interrupt in IER.
>
> Flip done interrupt is used to send the page flip event as soon as the
> surface address is written as per the requirement of async flips.
>
>
Em qui, 2019-05-02 às 11:29 +0300, Jani Nikula escreveu:
> Using arithmetic operators with booleans is confusing. Switch to logical
> operators.
>
> Cc: Paulo Zanoni
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1
niLake until a solution is found.
> >
> > Buglink: https://bugs.freedesktop.org/show_bug.cgi?id=108085
> > Signed-off-by: Daniel Drake
> > Signed-off-by: Jian-Hong Pan
>
> Fixes: fd7d6c5c8f3e ("drm/i915: enable FBC on gen9+ too") ?
> Cc: Paulo Zanoni
> Cc: Danie
Em seg, 2019-04-15 às 09:42 +0300, Tomi Sarvela escreveu:
> On 4/12/19 11:57 PM, Paulo Zanoni wrote:
> > Em qui, 2019-04-11 às 01:08 +, Patchwork escreveu:
> > > == Series Details ==
> > >
> > > Series: IRQ initialization debloat and conversion
Em qui, 2019-04-11 às 01:08 +, Patchwork escreveu:
> == Series Details ==
>
> Series: IRQ initialization debloat and conversion to uncore (rev2)
> URL : https://patchwork.freedesktop.org/series/59202/
> State : success
So, this is the BAT email I got yesterday. I don't see the FI.CI.IGT
)
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 136
1 file changed, 86 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8d8935d71180..60a3f4203ac3 100644
--- a/drivers/gpu/drm/i915
atches.
Reviewed-by: Ville Syrjälä (v1)
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 144 +++-
1 file changed, 88 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 22b89da25289..f6ab4c
have so many instances of IIR/IMR in comments that
adding a prefix would make the users of these register more easily
findable, in addition to make our token pasting macros actually
readable. So IMHO opening an exception here is worth it.
Cc: Ville Syrjälä
Signed-off-by: Paulo Zanoni
in the macro callers. Doing that
should be very simple now.
v2: Rebase on top of the new patches.
Reviewed-by: Ville Syrjälä (v1)
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 97 -
1 file changed, 48 insertions(+), 49 deletions(-)
diff --git
:
- Two additional patches based on the discussion with Ville and Checkpatch.
- No more checkpatch complaints.
Cc: Ville Syrjälä
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Paulo Zanoni (5):
drm/i915: refactor the IRQ init/reset macros
drm/i915: don't specify the IRQ register in the gen2
them through variables.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 57 +++--
1 file changed, 25 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 60a3f4203ac3..b1f1db2bd879 100644
Em ter, 2019-04-09 às 21:20 +0300, Ville Syrjälä escreveu:
> On Tue, Apr 09, 2019 at 10:34:22AM -0700, Paulo Zanoni wrote:
> > Em ter, 2019-04-09 às 00:44 +, Patchwork escreveu:
> > > == Series Details ==
> > >
> > > Series: IRQ initialization debloa
Em ter, 2019-04-09 às 21:10 +0300, Ville Syrjälä escreveu:
> On Mon, Apr 08, 2019 at 05:37:27PM -0700, Paulo Zanoni wrote:
> > The whole point of having macros here is for the token pasting
> > necessary to automatically have IMR, IIR and IER selected. We don't
> > re
Em ter, 2019-04-09 às 00:44 +, Patchwork escreveu:
> == Series Details ==
>
> Series: IRQ initialization debloat and conversion to uncore
> URL : https://patchwork.freedesktop.org/series/59202/
> State : warning
>
> == Summary ==
>
> $ dim checkpatch origin/drm-tip
> 7f73d1fe31bb
1100 333-767
gen11_irq_reset 1959 686 -1273
Total: Before=2262051, After=2256428, chg -0.25%
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 123 +++-
1 file changed, 73 insertions(+), 50
Make them take the uncore argument from the caller instead of passing
the implicit _priv->uncore directly. This will allow us to finally
pass something that's not dev_priv->uncore in the future, and gets rid
of the implicit variables in register macros.
Signed-off-by: Paulo Zanoni
---
d
Ceraolo Spurio
Paulo Zanoni (3):
drm/i915: refactor the IRQ init/reset macros
drm/i915: convert the IRQ initialization functions to intel_uncore
drm/i915: fully convert the IRQ initialization macros to intel_uncore
drivers/gpu/drm/i915/i915_irq.c | 275 +++-
1 file
in the macro callers. Doing that
should be very simple now.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 100
1 file changed, 50 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index
> Total: Before=1544400, After=1544366, chg -0.00%
>
> Win some, lose some, gcc is gcc.
>
> Signed-off-by: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> Reviewed-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_reset.c | 122
gned-off-by: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_reset.c | 125 +-
> 1 file changed, 73 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reset.c
> b/dri
e?
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_reset.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reset.c
Em seg, 2019-03-25 às 14:49 -0700, Daniele Ceraolo Spurio escreveu:
> Save the HW capabilities to avoid having to jump back to dev_priv
> every time.
>
Reviewed-by: Paulo Zanoni
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> Cc: Chris Wilson
> ---
&g
>
> Note that this patch also change the behavior for gen5 with vpgu
> enabled, but this is not an issue since we don't support vgpu on gen5.
>
> v2: split out from previous path, fix check for missing case (Paulo)
Much better as a separate patch. Thanks.
Reviewed-by: Paulo Zanoni
>
Em seg, 2019-03-25 às 14:49 -0700, Daniele Ceraolo Spurio escreveu:
> They now work on uncore, so use raw_uncore_ prefix. Also move them to
> uncore.h
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/
Em ter, 2019-03-19 às 11:35 -0700, Daniele Ceraolo Spurio escreveu:
> Save some uncore properties to avoid having to jump back to
> dev_priv every time
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4
Em ter, 2019-03-19 às 11:35 -0700, Daniele Ceraolo Spurio escreveu:
> This will allow futher simplifications in the uncore handling.
>
> v2: move register access setup under uncore (Chris)
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Paulo Z
r:
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/gvt/mmio_context.c | 8 +--
> drivers/gpu/drm/i915/gvt/scheduler.c | 4 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 12 ++---
&
reserved
bits in gen6 is not an issue, then everything else looks correct:
Reviewed-by: Paulo Zanoni
I also couldn't find information about WaRsClearFWBitsAtReset. Don't we
need to update its tags to include the most recent platforms and
ivb/hsw/vlv?
>
> Signed-off-by: Daniele Cerao
To give a parallel with other parts of the driver, in display code we
tend to pass struct intel_crtc as much as possible and only pass enum
pipe when it doesn't make sense anymore to pass a CRTC. So uncore makes
sense here.
More below:
>
> Cc: Paulo Zanoni
> Signed-off-by: Dani
Em qua, 2019-03-13 às 16:13 -0700, Daniele Ceraolo Spurio escreveu:
> Use a local variable where it makes sense.
Also worth it on its own IMHO.
Reviewed-by: Paulo Zanoni
>
> Cc: Paulo Zanoni
> Signed-off-by: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/i
Em qua, 2019-03-13 às 16:13 -0700, Daniele Ceraolo Spurio escreveu:
> Remove unneeded usage of dev_priv from 1 extra function.
>
Reviewed-by: Paulo Zanoni
> Cc: Paulo Zanoni
> Signed-off-by: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 20 +++
ase fix all of them :).
I think the s/dev_priv/i915/ here is a little unnecessary since it
inflates the diff even more (when will we settle with a single name?),
but okay let's go with it.
Patch still worth on its own IMHO due to all the dev_priv->uncore to
just uncore reduction.
Reviewed-b
d much value on its own IMHO
(i.e., without the rest of the series), but it still helps intel_uncore
move away from the God Object pattern of dev_priv. I'll add my r-b to
the version with the gvt fix when it's sent.
>
> Cc: Paulo Zanoni
> Signed-off-by: Daniele Ceraolo Spurio
> ---
Em qua, 2019-03-13 às 16:13 -0700, Daniele Ceraolo Spurio escreveu:
> Get/put functions used outside of uncore.c are updated in the next
> patch for a nicer split
>
> Cc: Paulo Zanoni
> Signed-off-by: Daniele Ceraolo Spurio
I really like this one, replacing a gazillion i915->
Em qua, 2019-03-13 às 16:13 -0700, Daniele Ceraolo Spurio escreveu:
> The only usage we have for it is for the regs pointer. Save a pointer to
> the set and ack registers instead of the register offsets to remove this
> requirement
Reviewed-by: Paulo Zanoni
>
> Cc: Paulo Zanon
Em sex, 2019-03-15 às 06:56 +, Tvrtko Ursulin escreveu:
> On 15/03/2019 00:52, Chris Wilson wrote:
> > Quoting José Roberto de Souza (2019-03-15 00:42:35)
> > > We don't have any platform that is composed by 2 or more platforms so
> > > we don't need a mask, lets drop it and remove the actual
L0
> when the latter was most definitely available).
Reviewed-by: Paulo Zanoni
>
> Cc: Lucas De Marchi
> Cc: Paulo Zanoni
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff -
Em qui, 2019-01-24 às 10:52 -0800, Lucas De Marchi escreveu:
> On Wed, Jan 23, 2019 at 05:15:26PM -0800, Paulo Zanoni wrote:
> > Em qui, 2019-01-17 às 12:21 -0800, Lucas De Marchi escreveu:
> > > Fix the TODO leftover in the code by changing the argument in MG_PLL
> > >
Em qui, 2019-01-17 às 12:21 -0800, Lucas De Marchi escreveu:
> Instead of looping again on the range of plls, just keep track of one
> unused one and use it later.
>
Reviewed-by: Paulo Zanoni
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/int
state->shared_dpll;
> @@ -1004,10 +1004,11 @@ static uint32_t icl_pll_to_ddi_pll_sel(struct
> intel_encoder *encoder,
>
> switch (id) {
> default:
> + /*
> + * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be use
dpll_id id)
> +static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
> {
> - return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
> + return id - DPLL_ID_ICL_MGPLL1;
> }
>
> -enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
> +enum intel_dpll_id icl_tc_
Reviewed-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 43 ++---
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27498ded4949..18914c4ca070
() and keep the
icp_rawclk() style, but Ville gave some good arguments that what's in
this patch may be the better choice.
v2: Switch numerator to 1 from 1000 and adjust calculations
accordingly (Ville).
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu
;, which makes a lot more sense. Use the more complete ICL
naming because we will merge the CNP and ICP functions into a single
one, which will introduce the concept of the numerator. That will make
a lot more sense when you read the "num/frac = den" calculation.
Reviewed-by: Ville Syrjäl
lä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_cdclk.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 8d74276029e6..810670976e86 100644
--- a/drivers/gpu/drm/i915/intel_cdc
() and keep the
icp_rawclk() style, but Ville gave some good arguments that what's in
this patch may be the better choice.
v2: Switch numerator to 1 from 1000 and adjust calculations
accordingly (Ville).
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu
Em Seg, 2018-11-12 às 16:54 +0200, Ville Syrjälä escreveu:
> On Fri, Nov 09, 2018 at 04:23:50PM -0800, Paulo Zanoni wrote:
> > I think I'm probably the one who argued in favor of having separate
> > implementations for both PCHs, but the calculations are actually
> > the
() and keep the
icp_rawclk() style, but Ville gave some good arguments that what's in
this patch may be the better choice.
Cc: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_cdclk.c | 37 -
1 file changed, 8 insertions(+), 29 deletions
;, which makes a lot more sense. Use the more complete ICL
naming because we will merge the CNP and ICP functions into a single
one, which will introduce the concept of the numerator. That will make
a lot more sense when you read the "num/frac = den" calculation.
Signed-off-by: Paulo Zan
BSpec was updated and now there's no more "subtract 1" to the
Microsecond Counter Divider field.
It seems this should help fixing some GMBUS issues. I'm not aware of
any specific open bug that could be solved by this patch.
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Pa
Reviewed-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 43 ++---
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9da8ff263d36
Em Seg, 2018-10-22 às 17:06 -0700, Rodrigo Vivi escreveu:
> On Mon, Oct 22, 2018 at 04:48:50PM -0700, Paulo Zanoni wrote:
> > Em Seg, 2018-10-22 às 09:57 -0700, Rodrigo Vivi escreveu:
> > > Let's add a platform has_sagv instead of having a full
> > > function that
Em Seg, 2018-10-22 às 16:55 -0700, Rodrigo Vivi escreveu:
> On Mon, Oct 22, 2018 at 04:32:00PM -0700, Paulo Zanoni wrote:
> > Em Qui, 2018-10-18 às 16:14 +0300, Ville Syrjälä escreveu:
> > > On Tue, Oct 16, 2018 at 03:01:23PM -0700, Paulo Zanoni wrote:
> >
Em Seg, 2018-10-22 às 09:57 -0700, Rodrigo Vivi escreveu:
> Let's add a platform has_sagv instead of having a full
> function that handle platform by platform.
>
> The specially case for SKL for not controlled sagv
> is already taken care inside intel_enable_sagv, so there's
> no need to
Em Qui, 2018-10-18 às 16:14 +0300, Ville Syrjälä escreveu:
> On Tue, Oct 16, 2018 at 03:01:23PM -0700, Paulo Zanoni wrote:
> > BSpec does not show these WAs as applicable to GLK, and for CNL it
> > only shows them applicable for a super early pre-production
> > stepping
>
Em Qui, 2018-10-18 às 16:41 +0300, Ville Syrjälä escreveu:
> On Tue, Oct 16, 2018 at 03:01:29PM -0700, Paulo Zanoni wrote:
> > The goal of struct skl_wm_params is to cache every watermark
> > parameter so the other functions can just use them without worrying
> > about
Em Qui, 2018-10-18 às 16:55 +0300, Ville Syrjälä escreveu:
> On Tue, Oct 16, 2018 at 03:01:30PM -0700, Paulo Zanoni wrote:
> > Print a more generic "failed to compute watermark levels" whenever
> > any
> > of skl_compute_wm_levels() fail, and print only
Em Sex, 2018-10-12 às 15:42 +0300, Ville Syrjälä escreveu:
> On Thu, Oct 11, 2018 at 05:40:45PM -0700, Paulo Zanoni wrote:
> > These are the new recommended values provided by our spec (18 -> 19
> > and 23 -> 24). It seems this should help fixing GMBUS issues. Since
> &
Em Ter, 2018-10-16 às 22:39 +, Patchwork escreveu:
> == Series Details ==
>
> Series: More watermarks improvements
> URL : https://patchwork.freedesktop.org/series/51086/
> State : failure
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_4990 -> Patchwork_10481 =
>
> == Summary -
Em Ter, 2018-10-16 às 22:21 +, Patchwork escreveu:
> == Series Details ==
>
> Series: More watermarks improvements
> URL : https://patchwork.freedesktop.org/series/51086/
> State : warning
>
> == Summary ==
>
> $ dim checkpatch origin/drm-tip
> 6a8c3f3d3663 drm/i915: don't apply Display
/kms_cursor_legacy/nonblocking-modeset-vs-cursor-atomic
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 15 ++-
2 files changed, 7 insertions(+), 9 deletions(-)
The error message mentioned above isd the one added by patch 06
chosen names for its parameters.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 20
2 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index
functions.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1290efc64869..d101c542f10d 100644
--- a/drivers/gpu/drm/i915
ndom intel state structs.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4053f4a68657..1290efc64869 100644
---
;just to be safe", then we should also
zero initialize it when we use it for plane 0.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9043ffe40ce8..d1
Except for maybe patch 1, I don't believe this series will allow us to
close any real bugs, but at least it should make the code more
readable. Please notice that we removed more lines than we added :).
Thanks,
Paulo
Paulo Zanoni (11):
drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL
on a void function really doesn't help readability IMHO.
Refactor the function so that the first level of checks is per
platform and the second level is for planar planes. IMHO that makes
the code much more readable.
Requested-by: Matt Roper
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel
.
The ddb_blocks parameter is one that is used by both the the plane
watermarks and the transition watermarks. Move ddb_blocks to the
parameter struct so we can simplify the code.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 44
Stop passing modeset state structures to functions that should work
only with the skl_wm_params. The only use for cstate there was to
reach dev_priv, so pass it directly.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions
to assign it.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1dd3ae408f9..7fd344b81d66 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b
.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3017ef037fed..3616b718b5d2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915
BSpec does not show these WAs as applicable to GLK, and for CNL it
only shows them applicable for a super early pre-production stepping
we shouldn't be caring about anymore. Remove these so we can avoid
them on ICL too.
Cc: Matt Roper
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915
tching the values listed in BSpec instead of recalculating
them.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h| 1 -
drivers/gpu/drm/i915/intel_cdclk.c | 37 ++---
2 files changed, 6 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/dr
From: Mahesh Kumar
Enable SAGV for ICL platform.
Cc: Gwan-gyeong Mun
Reviewed-by: James Ausmus
Reviewed-by: Paulo Zanoni
Signed-off-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
I had previously
Em Qua, 2018-09-05 às 16:41 -0700, Rodrigo Vivi escreveu:
> On Wed, Sep 05, 2018 at 02:32:38PM +0530, Karthik B S wrote:
> > Display Workarounds #1125 and #1126 are intended for Gen10 and
> > below platforms. These workarounds can be avoided in Gen11.
> >
> > The result blocks for WM1-WM7 should
Em Ter, 2018-10-09 às 16:55 -0700, Matt Roper escreveu:
> On Thu, Oct 04, 2018 at 04:15:55PM -0700, Paulo Zanoni wrote:
> > BSpec does not show these WAs as applicable to GLK, and for CNL it
> > only shows them applicable for a super early pre-production
> > stepping
>
e definition macros")
> v4: Rodrigo fixing his own mess on commit mentioning on v3
> comment above.
>
> Fixes: 4445930f1c4a ("firmware/dmc/icl: load v1.07 on icelake.")
Yes, please. I wasted time because I lacked this commit.
Tested-by: Paulo Zanoni
> Cc: Rodrigo V
the double write.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 14f13a371989..53b4a9a2de69 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu
Blocks minus 1 without any rounding errors.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 40ce99c455f3..14f13a371989 100644
I'm investigating ICL watermarks failures and these are some of the immediate
problems I was able to find in the watermarks code. I don't think they're enough
to fix the problems our CI is able to reproduce, but I do think these changes
are worth having.
Paulo Zanoni (6):
drm/i915: don't apply
On these platforms we're supposed to unconditonally pick the method 2
result instead of the minimum.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b
The transition minimum is 14 blocks for gens 9 and 10, and 4 blocks
for gen 11. This minimum value is supposed to be added to the
configurable trans_amount. This matches both BSpec and additional
information provided by our HW engineers.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915
BSpec does not show these WAs as applicable to GLK, and for CNL it
only shows them applicable for a super early pre-production stepping
we shouldn't be caring about anymore. Remove these so we can avoid
them on ICL too.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 43
This message is currently marked as DRM_DEBUG_ATOMIC. I would like it
to be DRM_DEBUG_KMS since it is more KMS than atomic, and this will
also make the message appear in the CI logs, which may or may not help
us with some FIFO underrun bugs.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915
Em Qui, 2018-09-27 às 17:16 +0300, Ville Syrjälä escreveu:
> On Tue, Sep 25, 2018 at 03:02:21PM -0700, Paulo Zanoni wrote:
> > Em Ter, 2018-09-25 às 15:02 +0300, Ville Syrjälä escreveu:
> > > On Mon, Sep 24, 2018 at 05:19:11PM -0700, Paulo Zanoni wrote:
> > > > F
Em Ter, 2018-09-25 às 15:05 +0300, Ville Syrjälä escreveu:
> On Mon, Sep 24, 2018 at 05:19:12PM -0700, Paulo Zanoni wrote:
> > Because we can, the places where we use them already expect const
> > structs.
>
> https://patchwork.freedesktop.org/series/44104/ already has the r
Em Ter, 2018-09-25 às 15:02 +0300, Ville Syrjälä escreveu:
> On Mon, Sep 24, 2018 at 05:19:11PM -0700, Paulo Zanoni wrote:
> > Function intel_framebuffer_init() checks for the possibilities
> > during
> > framebuffer creation (addfb ioctl time). It is missing the fact
>
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