From: Ville Syrjälä
I don't think the display hardware really has such chroma
plane tile row alignment requirements as outlined in
commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar
UV plane is tile row size aligned")
Bspec had the same exact thing to say about earlier hardware
as well,
From: Ville Syrjälä
Currently we still use the SKL+ PLANE_SURF alignment even
for TGL+ even though the hardware no longer needs it.
Introduce a separate tgl_plane_min_alignment() and update
it to more accurately reflect the hardware requirements.
v2: Don't screw up DPT+semiplanar 2MiB alignment
From: Ville Syrjälä
Now that all pre-skl platforms have their own .min_alignment()
functions the remainder of intel_surf_alignment() can be hoisted
into skl_univerals_plane.c (and renamed appropriately).
Reviewed-by: Imre Deak
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Extract the necessary chunks from intel_surf_alignment()
into per-platform variants for all pre-skl primary/sprite
planes.
Reviewed-by: Imre Deak
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 69 -
From: Ville Syrjälä
Split intel_cursor_alignment() into per-platform variants.
Reviewed-by: Imre Deak
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 40 +++--
drivers/gpu/drm/i915/display/intel_fb.c | 16 -
From: Ville Syrjälä
Different planes could have different alignment requirements
even for the same format/modifier. Collect the alignment
requirements across all planes capable of scanning out the
fb such that the alignment is satisfactory to all those
planes.
So far this was sort of handle by
From: Ville Syrjälä
Different hardware generations have different scanout alignment
requirements. Introduce a new vfunc that will allow us to
make that distinction without horrible if-ladders.
For now we directly plug in the existing intel_surf_alignment()
and intel_cursor_alignment()
From: Ville Syrjälä
Rename drm_plane_check_pixel_format() to drm_plane_has_format()
and change the return type accordingly. Allows one to write
more natural code.
Also matches drm_any_plane_has_format() better.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Export drm_plane_has_format() so that drivers can use it.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_crtc_internal.h | 2 --
drivers/gpu/drm/drm_plane.c | 1 +
include/drm/drm_plane.h | 2 ++
3 files changed, 3
From: Ville Syrjälä
intel_surf_alignment() in particular has devolved into
a complete mess. Redesign the code so that we can handle
alignment restrictions in a nicer. Also adjust alignment
for TGL+ to actually match the hardware requirements.
v2: Drop the per-plane vma stuff as it was borked
From: Ville Syrjälä
At leat on Intel GPUs it is best to allocate CRTCs bottom up
as it will generally lead to lower power consumption. Recommend
userspace does so.
Not sure if this is strictly the best order for other hardware,
but drivers could always rearrange the CRTC list into some kind
of
From: Ville Syrjälä
Document all the fields of the drm_get_encoder ioctl.
Cc: Simon Ser
Cc: Daniel Stone
Signed-off-by: Ville Syrjälä
---
Documentation/gpu/drm-uapi.rst | 13 +
include/uapi/drm/drm_mode.h| 22 +-
2 files changed, 34 insertions(+), 1
From: Ville Syrjälä
The ATS faults have something to do with some new iommu stuff
on mtl+. Document that the relevant DSB interrupt bits aren't
valid for earlier platforms.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb_regs.h | 4 ++--
1 file changed, 2
From: Ville Syrjälä
DSB_STATUS bit 16 is supposed to be a sticky bit informing us whether
the DSB was idle or not when the pipe's delayed vblank (when double
buffered registers latch) occurred. Unfortunately it turns out this
is a level triggred signal, ie. the bit will be set whenever the
DSB
From: Ville Syrjälä
intel_crtc.c doens't need intel_dsb.h so don't include it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
From: Ville Syrjälä
The future direction will be to mainly use intel_display
rather than i915 in the display code. Start on that path
for the DSB code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c | 52
1 file changed, 26 insertions(+), 26
From: Ville Syrjälä
As we extend the use of DSB for critical pipe/plane register
programming, it'll be nice to have an escape valve at hand,
in case things go very poorly. To that end, add a i915.enable_dsb
modparam by which we can force the driver to take the pure mmio
path instead.
From: Ville Syrjälä
The DSB code will need to examine both the old and new crtc
states. Pass in the whole atomic state so we can dig up
what we need.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 2 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 11
From: Ville Syrjälä
We'll have need to examine both the old and new crtc states in
intel_color_prepare_commit(), so let's just pass in the whole
atomic state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 11 ---
From: Ville Syrjälä
The DSB code will need to know the hardware's idea of vertical
active, as that is also what defines the start of undelayed
vblank. Introduce a helper that gives us that information,
in line with the other intel_mode_v*() functions.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Add a tracepoint to see exactly when async flips complete.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_display_irq.c | 1 +
.../drm/i915/display/intel_display_trace.h| 23 +++
2 files changed, 24 insertions(+)
diff --git
From: Ville Syrjälä
Add a separate tracepoint for async flips vs. sync plane updates
to make it a bit easier to figure out what is happening.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 22 +++
.../gpu/drm/i915/display/intel_atomic_plane.h | 4
From: Ville Syrjälä
We'll need to arm the vblank event also from the future
DSB based codepath. Extract the function that does the
whold dance for us.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.c | 29 +++
From: Ville Syrjälä
More prep work extracted from my upcoming DSB based plane
programming series.
Ville Syrjälä (11):
drm/i915: Extract intel_crtc_arm_vblank_event()
drm/i915: Add async flip tracepoint
drm/i915: Add flip done tracepoint
drm/i915: Introduce intel_mode_vdisplay()
From: Ville Syrjälä
Since BDB version 211 block 46 has included more luminance and
gamma related information. Define it fully. The data is semi-based
on DisplayID v2.0 apparently.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12
1 file changed,
From: Ville Syrjälä
The VBT spec does a very poor job of defining how the chromaticity
coordinates in block 46 are laid out. After double checking the
Windows implementation it turns out these more or less match the
EDID definition, where the 10bit values are split into 2bit + 8bit
chunks.
From: Ville Syrjälä
No idea why the DDI clock gating print is done with drm_notice().
Just use drm_dbg_kms() since no one is going to be interested in
this under normal circumstances.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
1 file changed, 3
From: Ville Syrjälä
MTL has some new IOMMU thing that has a few new fault interrupts.
Enable those so we can know if things are going poorly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++
drivers/gpu/drm/i915/i915_reg.h |
From: Ville Syrjälä
PipeDMC has its own fault interrupt. Enable that so that
we can know if things are failing.
While at it, define the other pipeDMC interrupt as well, even
though we're not currently using it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_irq.c
From: Ville Syrjälä
GEN8_DE_PIPE_IRQ_FAULT_ERRORS & co. don't really achieve anything.
Get rid of them and just declare all the bits directly in
gen8_de_pipe_fault_mask().
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_display_irq.c | 26 ---
From: Ville Syrjälä
GEN9_PIPE_PLANE_FLIP_DONE() only works for planes 1-4. Extend
it handle planes 5-7 as well. Somewhat annoyingly the bits are
spread around into two distinct clumps.
Currently this doesn't achieve anything, but if we ever extend
async flip support to more than just the first
From: Ville Syrjälä
It's really hard to figure out which bdw+ pipe interrupt bits
we've defined and which we have not. Sort the defines to make
that a bit easier (still not super easy since the bits have
been shuffled a bit over the years).
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Sprinkle some notes indicating which platforms have which
pipe interrupt bits.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 42 -
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git
From: Ville Syrjälä
Replace the hand rolled (1<
---
drivers/gpu/drm/i915/i915_reg.h | 54 -
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0569a23b83b2..6b77de060e33 100644
From: Ville Syrjälä
Clean up the bdw+ pipe interrupt bits, and enable some new fault
interrupts on tgl+ and mtl+.
Ville Syrjälä (7):
drm/i915: Use REG_BIT() for bdw+ pipe interrupts
drm/i915: Document bdw+ pipe interrupt bits
drm/i915: Sort bdw+ pipe interrupt bits
drm/i915: Extend
From: Ville Syrjälä
Sprinkle some comments around to indicate which CRC registers
are valid for which platforms.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
It's probably a good idea to start protecting all macro arguments
to avoid any cargo-cult mistakes when people go looking for examples
of how to define these things.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_pipe_crc_regs.h| 26 +--
1
From: Ville Syrjälä
On hsw+ we only have one CRC result registers, instead of the
five we have on ivb, and some of the others have been repurposed
to serve other CRC related purposed.
Since the hsw+ vs. pre-hsw register operate quite diffently
let's add a separate definition for the hsw+
From: Ville Syrjälä
I need a scratch register which fill the following requirements:
- can be accessed via DSB
- all the bits can be read/written
- no serious side effects
So far the only thing I could think of is the "expected CRC"
register. Add the definition so I can use it.
While I only
From: Ville Syrjälä
The CRC registers are a pretty self contained bunch.
Extract them to a separate header to declutter i915_reg.h.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_display_irq.c | 1 +
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 1 +
From: Ville Syrjälä
PIPE_CRC_RES_*_IVB are proper pipe registers, and only valid
for IVB+ where pipe register blocks are equally spaced, so we
can switch from _MMIO_TRANS2() to the simpler _MMIO_PIPE() for
these.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Put all the definitions related to a single pipe CRC register
in one place, instead of the current approach where things are
spread all over the place.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_pipe_crc_regs.h| 43 ++-
1 file changed,
From: Ville Syrjälä
Polish the CRC register defintions. I really meant to
just add one new register definition, but the whole thing
ballooned a bit...
Ville Syrjälä (7):
drm/i915: Extract intel_pipe_crc_regs.h
drm/i915: Switch PIPE_CRC_RES_*_IVB to _MMIO_PIPE()
drm/i915: Regroup pipe CRC
From: Ville Syrjälä
Use intel_color_uses_dsb() instead of open coding it in
intel_vblank_evade_init(). Make the logic around DSB a bit
more isolated from the rest of the code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 4 +++-
1 file changed, 3
From: Ville Syrjälä
Allow the caller of intel_dsb_prepare() to determine which DSB
engine (out of the three possible per pipe) to use. This will
let us utilize multiple DSB engines during the same commit.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 2 +-
From: Ville Syrjälä
We're going to need to make the DSB ID visible outside the DSB
code, so that we eg. can use multiple DSB engines in parallel.
to that end move the definition to intel_dsb.h.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c | 8
From: Ville Syrjälä
Namespace the DSB ID enum properly, and make the naming match
other such enums in general. Also make the names 0 based as
that's what Bspec uses for DSB (unlike eg. planes where it
uses 1 based indexing).
We'll throw out INVALID_DSB while at it since we have no use for
it at
From: Ville Syrjälä
Apply a bit of polish to the DSB interface.
Ville Syrjälä (4):
drm/i915/dsb: Polish the DSB ID enum
drm/i915/dsb: Move DSB ID definition to the header
drm/i915/dsb: Pass DSB engine ID to intel_dsb_prepare()
drm/i915/dsb: Use intel_color_uses_dsb()
From: Ville Syrjälä
Dotclocks can reach ~1GHz these days, so intel_usecs_to_scanlines(),
with its 32bit maths, is currently limited to a few milliseconds.
I want bigger numbers in DSB selftests, so switch over to 64bit
maths.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Currently we switch from out software idea of a scanline
to the hw's idea of a scanline during the commit phase in
_intel_dsb_commit(). While that is slightly easier due to
fastsets fiddling with the timings, we'll also need to
generate proper hw scanline numbers already when
From: Ville Syrjälä
Extract intel_mode_vblank_end() in the same vein as
intel_mode_vblank_start(). While we have only one use
of this it seems nicer to unify the approach.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 16
From: Ville Syrjälä
I want to use intel_crtc_scanline_offset() in
intel_crtc_scanline_to_hw(). Relocate intel_crtc_scanline_offset()
a bit to avoid a forward declaration.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 76 ++---
1 file changed,
From: Ville Syrjälä
Currently intel_crtc_scanline_offset() is careful to always
return a positive offset. That is not actually necessary
as long as we take care of negative values when applying the
offset in __intel_get_crtc_scanline().
This simplifies intel_crtc_scanline_offset(), and makes
From: Ville Syrjälä
We have several copies of code calculating the hardware's
idea of vtotal. Pull that to a helper, similar to
intel_mode_vblank_{start,end}().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 40 +
From: Ville Syrjälä
Replace a few hand rolled copies of intel_mode_vblank_start() with
the real thing.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c| 10 +++---
drivers/gpu/drm/i915/display/intel_vblank.c | 9 +++--
From: Ville Syrjälä
A few cleanups around parts what deal with scanline numbers.
Ville Syrjälä (7):
drm/i915: Reuse intel_mode_vblank_start()
drm/i915: Extract intel_mode_vblank_end()
drm/i915: Extract intel_mode_vtotal()
drm/i915: Simplify scanline_offset handling for gen2
drm/i915:
From: Ville Syrjälä
skl_ddb_add_affected_planes() needs the full atomic state. Instead
of digging that out from dubious sources plumb it in explicitly.
The wm counterpart (skl_wm_add_affected_planes()) already does
things in the proper way.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
icl_check_nv12_planes() needs the full atomic state. Instead of
digging that out from dubious sources plumb it in explicitly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
From: Ville Syrjälä
Various parts of the cdclk code need access the full atomic
state. Currently it's being dug out via the cdclk_state->base.state
pointer, which is not great as that pointer isn't always valid.
Instead plumb the full atomic state from the top so that it's
clear that it is in
From: Ville Syrjälä
Fix up the SEL_FETCH_{SIZE,OFFSET} registers. A classic
copy-paste fail on my part.
I even had a small test to confirm that the old and new register
offsets match, but somehow I must have screwed things up when
running it, and likely just ended up comparing the old defines
From: Ville Syrjälä
The c8_planes_changed() check in the high level atomic code is
a bit of an eyesore. Push it inside intel_color_check() so the
high level code doesn't have to care about this stuff.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 11
From: Ville Syrjälä
Move the intel_crtc_needs_color_update() into intel_color_check()
so that the caller doesn't have to care about this. This will
also enable us to hide the c8_planes_changed() thing better.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 5
From: Ville Syrjälä
Bunch of stuff in intel_color_check() needs to look at both the
old and new crtc states. Currently we do that by digging the
full atomic state via the crtc_state->state pointer. That thing
is a total footgun if I ever saw one, as it's only valid during
specific parts of the
From: Ville Syrjälä
Eliminate the crtc_state->state footgun from intel_color_check(),
and hide some mundane C8 plane details inside it.
Ville Syrjälä (3):
drm/i915: Plumb the entire atomic state into intel_color_check()
drm/i915: Hide the intel_crtc_needs_color_update() inside
From: Ville Syrjälä
Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.
v2: Pass the correct register offset fpr pipe B (Jani)
From: Ville Syrjälä
Bspec lists the mas TMDS bitrate as 6 Gbps on ADL-S/ADL-P/DG2.
Bump our limit to match.
v2: Bump for ADL-S as well (Jani)
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
From: Ville Syrjälä
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
of unnecessary head scratching. Add aliases using the skl+ plane
names.
And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
as we only ever have 0-2 sprites per pipe on those platforms.
v2: Don't break
From: Ville Syrjälä
Disable eDP DSC usage when instructed to do so by the VBT.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 4
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c| 4
3
From: Ville Syrjälä
No idea what this MST checks is doing in intel_dp_has_audio().
Looks completely pointless, so get rid of it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
From: Ville Syrjälä
intel_dp_supports_dsc() now works for MST as well, reuse it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 20
From: Ville Syrjälä
Reuse intel_dp_has_dsc() during .compute_config() instead of
repeating some of the checks again by hand. We'll be adding
more checks to intel_dp_has_dsc() and this will make sure
we cover both .mode_valid() and .compute_config() with them.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Extract a helper to check whether the source+sink combo
supports DSC. That basic check is needed both during mode
validation and compute config. We'll also need to add extra
checks to both places, so having a single place for it is nicer.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Utilize intel_dp_has_dsc() for MST as well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 -
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +--
3 files changed, 6 insertions(+), 3
From: Ville Syrjälä
If we have no dsc_decompression_aux (only possible on MST)
then we won't have the dsc_dpcd caps either. So checking
both is not needed.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 1 -
1 file changed, 1 deletion(-)
diff --git
From: Ville Syrjälä
Respect the VBT's edp_disable_dsc bit, and do a bunch
of refactoring around checking for DSC support.
Also threw in a bonus cleanup to intel_dp_has_audio()
that caught my eye.
Ville Syrjälä (7):
drm/i915: Drop redundant dsc_decompression_aux check
drm/i915: Extract
From: Ville Syrjälä
Bspec lists the mas TMDS bitrate as 6 Gbps on ADL/DG2.
Bump our limit to match.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
From: Ville Syrjälä
Make life easier for drivers by filtering out unwanted YCbCr 4:2:0
only modes prior to calling the connector->mode_valid() hook.
Currently drivers will still see YCbCr 4:2:0 only modes in said
hook, which will likely come as a suprise when the driver has
declared no support
From: Ville Syrjälä
Group the sprite plane register definitions such that everything
to do wiht the same register is in one place.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_sprite_regs.h | 231 ++
1 file changed, 134 insertions(+), 97 deletions(-)
diff
From: Ville Syrjälä
Note which sprite registers are valid for which platforms.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_sprite_regs.h | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
From: Ville Syrjälä
Relocate all pre-skl primary plane register definitions
into their own declutter i915_reg.h.
Cc: Zhenyu Wang
Cc: Zhi Wang
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 1 +
.../gpu/drm/i915/display/i9xx_plane_regs.h| 98
From: Ville Syrjälä
Add some notes indicatign which plane registers/bits are
valid for which platforms.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/i9xx_plane_regs.h| 22 +--
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git
From: Ville Syrjälä
Group the pre-skl primary plane register definitions
sensible, and toss in a few comments to indicate which
platforms have what.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/i9xx_plane_regs.h| 46 ---
1 file changed, 29 insertions(+), 17
From: Ville Syrjälä
PIPEGCMAX was left behind when all other gamma registers moved
into intel_color_regs.h.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color_regs.h | 5 +
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 5 insertions(+), 4
From: Ville Syrjälä
Make a more thorough split between universal planes vs. cursors
by defining the contents of the cursor WM/DDB registers separately.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 34 +++
From: Ville Syrjälä
Instead of that huge _PICK() let's use PICK_EVEN_2RANGES()
for the SEL_FETCH_PLANE registers. A bit more tedious to have
to define 8 raw register offsets for everything, but perhaps
a bit easier to understand since we use a standard mechanism
now instead of hand rolling the
From: Ville Syrjälä
Rename the selective fetch plane registers to match the spec.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 +-
drivers/gpu/drm/i915/display/skl_universal_plane.c | 12 ++--
2 files changed, 11 insertions(+), 11
From: Ville Syrjälä
PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x7 range.
so using _MMIO_TRANS2() for it is not really correct. Also since this
is a pipe register, and not present on CHV, the registers will be
equally spaced out, so we can use the simpler _MMIO_PIPE() instead
From: Ville Syrjälä
Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Group the cursor register defines such that everything to
do with one register is in one place.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_cursor_regs.h | 52 +--
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git
From: Ville Syrjälä
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
of unnecessary head scratching. Add aliases using the skl+ plane
names.
And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
as we only ever have 0-2 sprites per pipe on those platforms.
Signed-off-by:
From: Ville Syrjälä
Bunch of cleanup mostly around plane registers.
Ville Syrjälä (13):
drm/i915: Add skl+ plane name aliases to enum plane_id
drm/i915: Clean up the cursor register defines
drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
drm/i915: Simplify PIPESRC_ERLY_TPT
From: Ville Syrjälä
I don't think the display hardware really has such chroma
plane tile row alignment requirements as outlined in
commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar
UV plane is tile row size aligned")
Bspec had the same exact thing to say about earlier hardware
as well,
From: Ville Syrjälä
Currently we still use the SKL+ PLANE_SURF alignment even
for TGL+ even though the hardware no longer needs it.
Introduce a separate tgl_plane_min_alignment() and update
it to more accurately reflect the hardware requirements.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Now that all pre-skl platforms have their own .min_alignment()
functions the remainder of intel_surf_alignment() can be hoisted
into skl_univerals_plane.c (and renamed appropriately).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fb.c | 77
From: Ville Syrjälä
Extract the necessary chunks from intel_surf_alignment()
into per-platform variants for all pre-skl primary/sprite
planes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 69 -
drivers/gpu/drm/i915/display/intel_fb.c |
From: Ville Syrjälä
Split intel_cursor_alignment() into per-platform variants.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 40 +++--
drivers/gpu/drm/i915/display/intel_fb.c | 16 -
drivers/gpu/drm/i915/display/intel_fb.h | 3
From: Ville Syrjälä
Different planes could have different alignment requirements
even for the same format/modifier. Collect the alignment
requirements across all planes capable of scanning out the
fb such that the alignment used when pinning the normal ggtt
view is satisfactory to all those
From: Ville Syrjälä
Different hardware generations have different scanout alignment
requirements. Introduce a new vfunc that will allow us to
make that distinction without horrible if-ladders.
For now we directly plug in the existing intel_surf_alignment()
and intel_cursor_alignment()
From: Ville Syrjälä
Rename drm_plane_check_pixel_format() to drm_plane_has_format()
and change the return type accordingly. Allows one to write
more natural code.
Also matches drm_any_plane_has_format() better.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c| 7 ++-
From: Ville Syrjälä
Export drm_plane_has_format() so that drivers can use it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_crtc_internal.h | 2 --
drivers/gpu/drm/drm_plane.c | 1 +
include/drm/drm_plane.h | 2 ++
3 files changed, 3 insertions(+), 2 deletions(-)
1 - 100 of 8965 matches
Mail list logo
