subject:"\[Intel\-gfx\] \[GLK MIPI DSI V5 2\/8\] drm\/i915\/glk\: Program new MIPI DSI PHY registers for GLK"

Re: [Intel-gfx] [GLK MIPI DSI V5 2/8] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

2017-02-16 Thread Jani Nikula

On Tue, 14 Feb 2017, Madhav Chauhan wrote: > From: Deepak M > > Program the clk lane and tlpx time count registers > to configure DSI PHY. > > v2: Addressed Jani's Review comments(renamed bit field macros) > v3: Program clk lane timing reg same as

[Intel-gfx] [GLK MIPI DSI V5 2/8] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

2017-02-14 Thread Madhav Chauhan

From: Deepak M Program the clk lane and tlpx time count registers to configure DSI PHY. v2: Addressed Jani's Review comments(renamed bit field macros) v3: Program clk lane timing reg same as dphy param reg. v4: Removed "line over 80 character" warning Signed-off-by: Deepak