On Thu, 14 Apr 2011 10:03:46 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Older chipsets do not support snooping (i.e. cache sharing between the
CPU and GPU) on tiled surfaces. So prevent userspace from being silly
should we one day expose the ability to change cache levels from
Older chipsets do not support snooping (i.e. cache sharing between the
CPU and GPU) on tiled surfaces. So prevent userspace from being silly
should we one day expose the ability to change cache levels from
userspace.
It does enforce a strict ordering for mode changing though. So in order
to
On Thu, Apr 14, 2011 at 10:03:46AM +0100, Chris Wilson wrote:
Older chipsets do not support snooping (i.e. cache sharing between the
CPU and GPU) on tiled surfaces. So prevent userspace from being silly
should we one day expose the ability to change cache levels from
userspace.
It does
On Thu, 14 Apr 2011 19:43:35 +0200, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Apr 14, 2011 at 10:03:46AM +0100, Chris Wilson wrote:
+ if (INTEL_INFO(dev)-gen 6
+ args-tiling_mode != I915_TILING_NONE
+ obj-cache_level != I915_CACHE_NONE) {
+ DRM_DEBUG(can't
