At Wed, 16 Oct 2013 18:27:33 +0100,
Chris Wilson wrote:
On Wed, Oct 16, 2013 at 10:06:27AM -0700, Ben Widawsky wrote:
On Wed, Oct 16, 2013 at 05:58:31PM +0100, Chris Wilson wrote:
So clearing the valid bit should result in the GPU reporting errors for
delayed accesses, but none were
On Thu, Oct 17, 2013 at 09:41:09AM +0200, Takashi Iwai wrote:
At Wed, 16 Oct 2013 18:27:33 +0100,
Chris Wilson wrote:
On Wed, Oct 16, 2013 at 10:06:27AM -0700, Ben Widawsky wrote:
On Wed, Oct 16, 2013 at 05:58:31PM +0100, Chris Wilson wrote:
So clearing the valid bit should result in
At Thu, 17 Oct 2013 10:24:07 +0100,
Chris Wilson wrote:
On Thu, Oct 17, 2013 at 09:41:09AM +0200, Takashi Iwai wrote:
At Wed, 16 Oct 2013 18:27:33 +0100,
Chris Wilson wrote:
On Wed, Oct 16, 2013 at 10:06:27AM -0700, Ben Widawsky wrote:
On Wed, Oct 16, 2013 at 05:58:31PM +0100,
On 10/16/13 9:21 AM, Ben Widawsky wrote:
Once the machine gets to a certain point in the suspend process, we
expect the GPU to be idle. If it is not, we might corrupt memory.
Empirically (with an early version of this patch) we have seen this is
not the case. We cannot currently explain why the
On Wed, Oct 16, 2013 at 09:21:30AM -0700, Ben Widawsky wrote:
Once the machine gets to a certain point in the suspend process, we
expect the GPU to be idle. If it is not, we might corrupt memory.
Empirically (with an early version of this patch) we have seen this is
not the case. We cannot
On Wed, Oct 16, 2013 at 05:58:31PM +0100, Chris Wilson wrote:
On Wed, Oct 16, 2013 at 09:21:30AM -0700, Ben Widawsky wrote:
Once the machine gets to a certain point in the suspend process, we
expect the GPU to be idle. If it is not, we might corrupt memory.
Empirically (with an early
On Wed, Oct 16, 2013 at 10:06:27AM -0700, Ben Widawsky wrote:
On Wed, Oct 16, 2013 at 05:58:31PM +0100, Chris Wilson wrote:
So clearing the valid bit should result in the GPU reporting errors for
delayed accesses, but none were reported?
So I can't actually reproduce the problem for some
