Hi Daniel,
Is there any other change required in this patch to consider before merge?
Please let me know.
- Vandana
On 7/3/2015 10:23 AM, Kannan, Vandana wrote:
Hi,
Any other review comments on this patch? Do let me know.
Siva and Sonika have given their R-b.
Thanks,
Vandana
On 7/1/2015
On Thu, Jul 02, 2015 at 10:39:05AM -0300, Paulo Zanoni wrote:
2015-07-01 17:44 GMT-03:00 Chris Wilson ch...@chris-wilson.co.uk:
On Wed, Jul 01, 2015 at 05:15:21PM -0300, Paulo Zanoni wrote:
Looks much cleaner with the split.
+void intel_fbc_cleanup_cfb(struct drm_device *dev)
+{
+
On 7/6/2015 2:06 PM, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 11:23:53AM +0530, Sonika Jindal wrote:
Writing to PCH_PORT_HOTPLUG for each interrupt is not required.
Handle it only if hpd has actually occurred like we handle other
interrupts.
Signed-off-by: Sonika Jindal
On Wed, Jul 01, 2015 at 07:26:01PM -0700, Matt Roper wrote:
From: Matt Roper m...@mattrope.com
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks
On Fri, Jul 03, 2015 at 12:17:33PM +0100, Tvrtko Ursulin wrote:
On 07/02/2015 04:55 PM, Chris Wilson wrote:
It would be nice if we could reuse one seqno both for internal/external
fences. If you need to expose a fence ordering within a timeline that is
based on the creation stamp rather
On Mon, Jul 06, 2015 at 11:09:25AM +0300, Mika Kuoppala wrote:
Now when we have requests this deep on call chain, we can mark
the elsp being submitted when it actually is. Remove temp variable
and readjust commenting to more closely fit to the code.
v2: Avoid tmp variable and reduce number
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6723
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
Writing to PCH_PORT_HOTPLUG for each interrupt is not required.
Handle it only if hpd has actually occurred like we handle other
interrupts.
v2: Make few variables local to if block (Ville)
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 14
On Fri, Jul 03, 2015 at 03:36:09AM +0300, Dmitry V. Levin wrote:
On Wed, Jul 01, 2015 at 02:52:47PM +0200, Patrik Jakobsson wrote:
[...]
--- a/drm.c
+++ b/drm.c
@@ -35,6 +35,9 @@
#define DRM_MAX_NAME_LEN 128
+extern int drm_i915_decode_number(struct tcb *tcp, unsigned int
On Fri, Jul 03, 2015 at 12:31:30PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
drivers/gpu/drm/i915/intel_ddi.c: In function ‘intel_prepare_ddi’:
drivers/gpu/drm/i915/intel_ddi.c:517:6: warning:
‘ddi_translations_fdi’ may be used uninitialized in this function
From: Deepak M m.dee...@intel.com
LFP brighness control from the VBT block 43 indicates which
controller is used for brightness.
LFP1 brightness control method:
Bit 7-4 = This field controller number of the brightnes controller.
0 = Controller 0
1 = Controller 1
2 = Controller 2
3 = Controller 3
On Mon, Jul 06, 2015 at 02:31:56PM +0530, Jindal, Sonika wrote:
On 7/6/2015 2:19 PM, Ville Syrjälä wrote:
On Mon, Jul 06, 2015 at 11:23:53AM +0530, Sonika Jindal wrote:
Writing to PCH_PORT_HOTPLUG for each interrupt is not required.
Handle it only if hpd has actually occurred like we
On Thu, Jul 02, 2015 at 08:24:12AM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 7/1/2015 6:26 PM, Daniel Vetter wrote:
On Tue, Jun 30, 2015 at 09:49:57PM +0530, Shashank Sharma wrote:
Userspace always sets force. Are you sure this actually improves anything?
Yes we do. We have had
On Fri, Jul 03, 2015 at 01:52:04PM -0300, Paulo Zanoni wrote:
2015-07-03 6:23 GMT-03:00 Dave Gordon david.s.gor...@intel.com:
On 01/07/15 14:02, Daniel Vetter wrote:
On Tue, Jun 30, 2015 at 11:14:54AM -0300, Paulo Zanoni wrote:
2015-06-30 10:54 GMT-03:00 Chris Wilson
On Thu, Jul 02, 2015 at 11:15:40AM +0100, Chris Wilson wrote:
On Wed, Jul 01, 2015 at 10:12:23AM +0300, Abdiel Janulgue wrote:
Ensures that the batch buffer is executed by the resource streamer
v2: Don't skip 115 for the exec flags (Jani Nikula)
v3: Use HAS_RESOURCE_STREAMER macro for
On Mon, Jul 06, 2015 at 11:23:53AM +0530, Sonika Jindal wrote:
Writing to PCH_PORT_HOTPLUG for each interrupt is not required.
Handle it only if hpd has actually occurred like we handle other
interrupts.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
Hi,
I see we don't check
On Mon, Jul 06, 2015 at 11:23:53AM +0530, Sonika Jindal wrote:
Writing to PCH_PORT_HOTPLUG for each interrupt is not required.
Handle it only if hpd has actually occurred like we handle other
interrupts.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
Hi,
I see we don't check
On 7/6/2015 2:19 PM, Ville Syrjälä wrote:
On Mon, Jul 06, 2015 at 11:23:53AM +0530, Sonika Jindal wrote:
Writing to PCH_PORT_HOTPLUG for each interrupt is not required.
Handle it only if hpd has actually occurred like we handle other
interrupts.
Signed-off-by: Sonika Jindal
On Wed, Jul 01, 2015 at 07:25:59PM -0700, Matt Roper wrote:
Calculate pipe watermarks during atomic calculation phase, based on the
contents of the atomic transaction's state structure. We still program
the watermarks at the same time we did before, but the computation now
happens much
On Mon, Jul 06, 2015 at 12:15:25PM +0530, Sivakumar Thulasimani wrote:
On 7/3/2015 6:27 PM, Ville Syrjälä wrote:
On Fri, Jul 03, 2015 at 02:35:49PM +0300, Mika Kahola wrote:
It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
On Fri, Jul 03, 2015 at 12:31:30PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
drivers/gpu/drm/i915/intel_ddi.c: In function ‘intel_prepare_ddi’:
drivers/gpu/drm/i915/intel_ddi.c:517:6: warning:
‘ddi_translations_fdi’ may be used uninitialized in this function
On Mon, Jul 06, 2015 at 12:26:15PM +0530, Sivakumar Thulasimani wrote:
On 7/2/2015 6:35 PM, Jani Nikula wrote:
Add an overview of the drm/i915 hotplug handling.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
Documentation/DocBook/drm.tmpl | 5 +
On Thu, Jul 02, 2015 at 03:48:50PM +0100, Chris Wilson wrote:
On Thu, Jul 02, 2015 at 05:43:21PM +0300, Jani Nikula wrote:
Signed-off-by: Jani Nikula jani.nik...@intel.com
25 code looks correct, but haven't crosschecked with the new OpRegion
spec, so Acked-by: Chris Wilson
On Sat, Jul 04, 2015 at 11:50:58AM +0200, Lukas Wunner wrote:
Currently when allocating a framebuffer fails, the gem object gets
unrefed at the bottom of the call chain in __intel_framebuffer_create,
not where it gets refed, which is in intel_framebuffer_create_for_mode
(via
On 7/6/2015 1:08 PM, Daniel Vetter wrote:
On Thu, Jul 02, 2015 at 08:24:12AM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 7/1/2015 6:26 PM, Daniel Vetter wrote:
On Tue, Jun 30, 2015 at 09:49:57PM +0530, Shashank Sharma wrote:
Userspace always sets force. Are you sure this actually
On Fri, Jul 03, 2015 at 03:33:31AM +0300, Dmitry V. Levin wrote:
On Wed, Jul 01, 2015 at 02:52:45PM +0200, Patrik Jakobsson wrote:
[...]
--- a/defs.h
+++ b/defs.h
@@ -266,6 +266,13 @@ struct tcb {
int u_error;/* Error code */
long scno; /* System call
In preparation to make intel_lr_context_pin|unpin to accept
requests, assign ringbuf into request before we call the pinning.
v2: No need to unset ringbuf on error path (Chris)
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
Now when we have requests this deep on call chain, we can mark
the elsp being submitted when it actually is. Remove temp variable
and readjust commenting to more closely fit to the code.
v2: Avoid tmp variable and reduce number of writes (Chris)
Cc: Chris Wilson ch...@chris-wilson.co.uk
On Mon, Jul 06, 2015 at 01:38:44PM +0530, Kannan, Vandana wrote:
Hi Daniel,
Is there any other change required in this patch to consider before merge?
Please let me know.
Oh I was kinda waiting for an ack from Imre. Merged now anyway.
Btw for next time around please spell out BUN - not
On Wed, Jul 01, 2015 at 09:08:15PM +0300, Imre Deak wrote:
On Tue, 2015-06-30 at 15:33 +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Here's my second attempt at flipping HDMI 12bpc back on. In my last attempt
[1]
Imre found that lots of
On Wed, Jul 01, 2015 at 05:15:20PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We want to move the FBC code out of i915_gem_stolen.c, but that code
directly adds/removes stolen memory nodes. Let's create this
abstraction, so i915_gme_stolen.c is still in control of
On Wed, Jul 01, 2015 at 07:26:00PM -0700, Matt Roper wrote:
Add a simple mechanism to trigger final watermark updates in an
asynchronous manner once the next vblank occurs. No platform types
actually support atomic watermark programming until a future patch, so
there should be no functional
On 6 July 2015 at 09:46, Abdiel Janulgue
abdiel.janul...@linux.intel.com wrote:
On 07/06/2015 11:28 AM, Daniel Vetter wrote:
On Thu, Jul 02, 2015 at 11:15:40AM +0100, Chris Wilson wrote:
On Wed, Jul 01, 2015 at 10:12:23AM +0300, Abdiel Janulgue wrote:
Ensures that the batch buffer is
On Thu, Jul 02, 2015 at 04:33:42PM +0300, Ville Syrjälä wrote:
On Thu, Jul 02, 2015 at 02:29:58PM +0300, Imre Deak wrote:
Ville noticed that the PLL HW readout code parsed the fractional
divider value as if the fractional divider was always enabled. This may
result in a port clock state
On 07/06/2015 11:28 AM, Daniel Vetter wrote:
On Thu, Jul 02, 2015 at 11:15:40AM +0100, Chris Wilson wrote:
On Wed, Jul 01, 2015 at 10:12:23AM +0300, Abdiel Janulgue wrote:
Ensures that the batch buffer is executed by the resource streamer
v2: Don't skip 115 for the exec flags (Jani Nikula)
On Mon, Jul 06, 2015 at 10:25:17AM +0100, Chris Wilson wrote:
On Mon, Jul 06, 2015 at 11:09:25AM +0300, Mika Kuoppala wrote:
Now when we have requests this deep on call chain, we can mark
the elsp being submitted when it actually is. Remove temp variable
and readjust commenting to more
On Mon, Jul 06, 2015 at 11:32:47AM +0200, Daniel Vetter wrote:
On Thu, Jul 02, 2015 at 04:33:42PM +0300, Ville Syrjälä wrote:
On Thu, Jul 02, 2015 at 02:29:58PM +0300, Imre Deak wrote:
Ville noticed that the PLL HW readout code parsed the fractional
divider value as if the fractional
From: Ville Syrjälä ville.syrj...@linux.intel.com
All the *_ddi_pll_select() functions get passed the port_clock and pipe
config as parameters. We only need to pass the pipe config, and the
functions can dig up the port_clock themselves.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
From: Ville Syrjälä ville.syrj...@linux.intel.com
We only need the link_bw/rate_select parameters when starting link
training, and they should be computed based on the currently active
config, so throw them out from intel_dp and just compute on demand.
Toss in an extra debug print to see
From: Ville Syrjälä ville.syrj...@linux.intel.com
While working on CHV DPIO powergating I relized DP .compute_config() was
clobbering lane_count etc. stored in intel_dp. This could cause problems
if we do the .compute_config() but later fail the modeset for some reason.
Any subsequent link
From: Ville Syrjälä ville.syrj...@linux.intel.com
Use port_clock instead of link_bw when picking the PLL parameters for
DP. link_bw may be zero with an eDP 1.4 sink that supports
DP_LINK_RATE_SET so we shouln't use it for anything other than feed it
to the sink appropriately.
Signed-off-by:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Use a separate variable for the TRANS_DP_CTL value instead of reusing
'tmp' that otherwise contains the DP port register value.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 7 ---
1 file
I few days ago I built a kernel from git (commit 6aaf0da872), and
noticed a couple of NULL pointer deferences. These seem to be
regressions as they aren't present in v4.1.
I did a bisect between v4.1 and 6aaf0da872, and came up with the
following commit as the first bad one:
d5432a9d
It can look pretty and allows to differenciate between several plots
drawn on the same canvas.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_plot.c | 24
lib/igt_plot.h | 3 +++
lib/tests/igt_plot.c | 1 +
3 files changed, 28
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_plot.c | 16 +++-
lib/igt_plot.h | 1 +
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/lib/igt_plot.c b/lib/igt_plot.c
index 2ca005e..763c000 100644
--- a/lib/igt_plot.c
+++ b/lib/igt_plot.c
@@ -443,7
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/tests/igt_plot.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/lib/tests/igt_plot.c b/lib/tests/igt_plot.c
index 7091cef..1706912 100644
--- a/lib/tests/igt_plot.c
+++ b/lib/tests/igt_plot.c
@@
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_plot.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/lib/igt_plot.c b/lib/igt_plot.c
index 126f160..c8d6dcb 100644
--- a/lib/igt_plot.c
+++ b/lib/igt_plot.c
@@ -452,6 +452,37 @@
Not only useful for inspection but also to check we can re-start a
drawing just fine.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/tests/igt_plot.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/tests/igt_plot.c b/lib/tests/igt_plot.c
index a178fbf..7091cef 100644
On Mon, Jul 06, 2015 at 01:47:44PM +0300, David Weinehall wrote:
On Fri, Jul 03, 2015 at 12:31:30PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
drivers/gpu/drm/i915/intel_ddi.c: In function ‘intel_prepare_ddi’:
drivers/gpu/drm/i915/intel_ddi.c:517:6: warning:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Since
commit e62925567c7926e78bc8ca976cde5c28ea265a49
Author: Vandana Kannan vandana.kan...@intel.com
Date: Wed Jul 1 17:02:57 2015 +0530
drm/i915/bxt: BUNs related to port PLL
BXT DPLL can now generate frequencies in the 216-223 MHz
From: Ville Syrjälä ville.syrj...@linux.intel.com
DP dongles may signal downstream HPD via short HPD pulses. If we know
the device has a HPD capable downstream port, make sure we kick off the
full hotplug processing even for short HPDs.
Additonally setting the sink to DPMS off kills the
On Mon, Jul 06, 2015 at 02:11:12PM +0530, Jindal, Sonika wrote:
On 7/6/2015 2:06 PM, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 11:23:53AM +0530, Sonika Jindal wrote:
Writing to PCH_PORT_HOTPLUG for each interrupt is not required.
Handle it only if hpd has actually occurred like we
Especially for workarounds which is stuff that's almost impossible to
verify: The initial state from the firmware on boot-up and after
resume could be different, which will hide bugs when we do an RMW
cycle.
Hence never do them, and if it's required we need a special mask.
Cc: Damien Lespiau
On 24/06/15 11:29, Daniel Vetter wrote:
On Fri, Jun 19, 2015 at 09:43:11AM +0100, Dave Gordon wrote:
On 18/06/15 15:49, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 01:11:34PM +0100, Dave Gordon wrote:
On 17/06/15 13:05, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 07:36:20PM +0100, Dave
On Mon, Jul 06, 2015 at 11:07:52AM +0200, Daniel Vetter wrote:
On Wed, Jul 01, 2015 at 07:26:00PM -0700, Matt Roper wrote:
Add a simple mechanism to trigger final watermark updates in an
asynchronous manner once the next vblank occurs. No platform types
actually support atomic watermark
On 03/07/15 16:42, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluvery wrote:
In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after PIPE_CONTROL
instruction but there is a slight complication as this is applied in WA batch
where the values are only
From: Ville Syrjälä ville.syrj...@linux.intel.com
intel_dp-link_bw is going away, so consul the port_clock instead when
choosing between TP1 and TP3.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 4 ++--
1 file changed, 2 insertions(+), 2
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently we clobber intel_dp-lane_count in compute config, which means
after a rejected modeset we may no longer be able to retrain the current
link. Move lane_count into pipe_config to avoid that.
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently we treat intel_{dp,hdmi}-color_range as partly user
controller value (via the property) but we also change it during
.compute_config() when using the Automatic mode. That is a bit
confusing, so let's just change things so that we store
Op 02-07-15 om 04:26 schreef Matt Roper:
From: Matt Roper m...@mattrope.com
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state
On 06/07/2015 12:52, Dave Gordon wrote:
On 03/07/15 16:42, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluvery wrote:
In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after PIPE_CONTROL
instruction but there is a slight complication as this is applied in WA
On Mon, Jul 06, 2015 at 02:20:00PM +0200, Maarten Lankhorst wrote:
Op 02-07-15 om 04:26 schreef Matt Roper:
From: Matt Roper m...@mattrope.com
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
On Fri, Jul 03, 2015 at 07:50:31PM +0100, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 03:40:54PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Now all the functions called by other files check whether FBC has been
initialized. This allows us to drop the checks on
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_stats.c | 22 ++
lib/igt_stats.h | 2 ++
2 files changed, 24 insertions(+)
diff --git a/lib/igt_stats.c b/lib/igt_stats.c
index 37fcc23..1103a7b 100644
--- a/lib/igt_stats.c
+++ b/lib/igt_stats.c
@@ -133,6
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
.../intel-gpu-tools/intel-gpu-tools-docs.xml | 1 +
lib/Makefile.sources | 2 +
lib/igt_plot.c | 607 +
lib/igt_plot.h
On Mon, Jul 06, 2015 at 12:52:51PM +0100, Dave Gordon wrote:
On 03/07/15 16:42, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluvery wrote:
In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
PIPE_CONTROL
instruction but there is a slight complication as
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_stats.c | 68 +
lib/igt_stats.h | 3 +++
2 files changed, 71 insertions(+)
diff --git a/lib/igt_stats.c b/lib/igt_stats.c
index 70650ec..37fcc23 100644
---
Can use to reduce typing a bit, at the expense of a function call.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_plot.c | 21 -
lib/igt_plot.h | 9 +
lib/tests/igt_plot.c | 11 ++-
3 files changed, 35 insertions(+), 6
Histograms are a great way to have a look at a dataset to understand how
the values are distributed.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_stats.c | 105 ++
lib/igt_stats.h | 23 +++
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_plot.c | 59
lib/igt_plot.h | 2 ++
lib/tests/igt_plot.c | 1 +
3 files changed, 62 insertions(+)
diff --git a/lib/igt_plot.c b/lib/igt_plot.c
index
This frames a bit more the plot will look nice with a background grid.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_plot.c | 46 +-
lib/igt_plot.h | 2 ++
lib/igt_types.h | 14 ++
3 files changed, 53 insertions(+),
Might as well start to define some igt wide types. I'll need them for
igt_plot, but other things belong here, like a color type.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
.../intel-gpu-tools/intel-gpu-tools-docs.xml | 1 +
lib/Makefile.sources
Until now we had transparent black.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_plot.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/lib/igt_plot.c b/lib/igt_plot.c
index c8d6dcb..afe4a1c 100644
--- a/lib/igt_plot.c
+++
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_plot.c | 100 +--
lib/igt_plot.h | 9 -
lib/tests/igt_plot.c | 2 ++
3 files changed, 100 insertions(+), 11 deletions(-)
diff --git a/lib/igt_plot.c
Unfortunately, I didn't manage to make the image inclusion work...
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_plot.c | 29 -
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/lib/igt_plot.c b/lib/igt_plot.c
index b3d4bc7..bc7bce1
On Mon, Jul 06, 2015 at 02:42:02PM +0200, Daniel Vetter wrote:
Especially for workarounds which is stuff that's almost impossible to
verify: The initial state from the firmware on boot-up and after
resume could be different, which will hide bugs when we do an RMW
cycle.
Hence never do them,
On Mon, Jul 06, 2015 at 09:46:07AM +0530, Deepak M wrote:
In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.
The CABC is not standardized and panel vendors
On Mon, Jul 06, 2015 at 02:42:02PM +0200, Daniel Vetter wrote:
Especially for workarounds which is stuff that's almost impossible to
verify: The initial state from the firmware on boot-up and after
resume could be different, which will hide bugs when we do an RMW
cycle.
If you're really
Hi Daniel,
On Mon, Jul 06, 2015 at 09:41:51AM +0200, Daniel Vetter wrote:
Please keep a record of the changes you do to the patch so I know what to
look out for. Just reving the patch revision alone doesn't add much
information for reviewers/maintainers.
There's a changelog in the first patch
On 06/07/2015 10:29, Daniel Vetter wrote:
On Fri, Jul 03, 2015 at 12:17:33PM +0100, Tvrtko Ursulin wrote:
On 07/02/2015 04:55 PM, Chris Wilson wrote:
It would be nice if we could reuse one seqno both for internal/external
fences. If you need to expose a fence ordering within a timeline that is
On 06/07/15 13:38, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 12:52:51PM +0100, Dave Gordon wrote:
On 03/07/15 16:42, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluvery wrote:
In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after PIPE_CONTROL
On Mon, Jul 06, 2015 at 01:44:10PM +0100, Dave Gordon wrote:
On 24/06/15 11:29, Daniel Vetter wrote:
On Fri, Jun 19, 2015 at 09:43:11AM +0100, Dave Gordon wrote:
On 18/06/15 15:49, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 01:11:34PM +0100, Dave Gordon wrote:
On 17/06/15 13:05, Daniel
On Fri, Jul 03, 2015 at 06:35:55PM +0300, Ville Syrjälä wrote:
On Fri, Jul 03, 2015 at 04:25:15PM +0100, Damien Lespiau wrote:
On Fri, Jul 03, 2015 at 06:21:58PM +0300, Ville Syrjälä wrote:
In the old VBT spec I have, each child_dev_config is supposed to have
only 33 bytes. But in this
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently we clobber intel_dp-lane_count in compute config, which means
after a rejected modeset we may no longer be able to retrain the current
link. Move lane_count into pipe_config to avoid that.
v2: Add missing ':' to the pipe config debug
On Mon, Jul 06, 2015 at 02:59:02PM +0200, Lukas Wunner wrote:
Hi Daniel,
On Mon, Jul 06, 2015 at 09:41:51AM +0200, Daniel Vetter wrote:
Please keep a record of the changes you do to the patch so I know what to
look out for. Just reving the patch revision alone doesn't add much
On Mon, Jul 06, 2015 at 01:58:25PM +0100, John Harrison wrote:
On 06/07/2015 10:29, Daniel Vetter wrote:
On Fri, Jul 03, 2015 at 12:17:33PM +0100, Tvrtko Ursulin wrote:
On 07/02/2015 04:55 PM, Chris Wilson wrote:
It would be nice if we could reuse one seqno both for internal/external
fences.
On Fri, Jul 03, 2015 at 01:30:25PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
Two new module parameters: enable_guc_submission which will turn
on submission of batchbuffers via the GuC (when implemented), and
guc_log_level which controls the level of debugging logged by the
On Fri, Jul 03, 2015 at 01:30:32PM +0100, Dave Gordon wrote:
A GuC client has its own doorbell and workqueue. It maintains the
doorbell cache line, process description object and work queue item.
A default guc_client is created for the i915 driver to use for
normal-priority in-order
On 06/07/15 13:50, Ville Syrjälä wrote:
On Mon, Jul 06, 2015 at 02:42:02PM +0200, Daniel Vetter wrote:
Especially for workarounds which is stuff that's almost impossible to
verify: The initial state from the firmware on boot-up and after
resume could be different, which will hide bugs when we
On Fri, Jul 03, 2015 at 01:30:24PM +0100, Dave Gordon wrote:
Current devices may contain one or more programmable microcontrollers
that need to have a firmware image (aka binary blob) loaded from an
external medium and transferred to the device's memory.
This file provides common support
On Fri, Jul 03, 2015 at 01:30:33PM +0100, Dave Gordon wrote:
Turn on interrupt steering to route necessary interrupts to GuC.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 11
On Mon, Jul 06, 2015 at 08:58:31PM +0100, Damien Lespiau wrote:
On Mon, Jul 06, 2015 at 08:25:56PM +0200, Daniel Vetter wrote:
atm QA rolls their own thing, developers on mesa side have ministat, and
it looks like you want to create something in igt. I know it's easier, but
I'd like to
On Mon, Jul 06, 2015 at 01:46:19PM +0100, Damien Lespiau wrote:
On Mon, Jul 06, 2015 at 02:42:02PM +0200, Daniel Vetter wrote:
Especially for workarounds which is stuff that's almost impossible to
verify: The initial state from the firmware on boot-up and after
resume could be different,
On 07/06/2015 04:12 PM, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 03:46:49PM +0100, Tvrtko Ursulin wrote:
On 07/06/2015 03:26 PM, John Harrison wrote:
On 06/07/2015 14:59, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 01:58:25PM +0100, John Harrison wrote:
On 06/07/2015 10:29, Daniel
On Mon, Jul 06, 2015 at 03:57:44PM +0100, Chris Wilson wrote:
On Mon, Jul 06, 2015 at 05:50:37PM +0300, Imre Deak wrote:
We have 3 types of DMA mappings for GEM objects:
1. physically contiguous for stolen and for objects needing contiguous
memory
2. DMA-buf mappings imported via a
On 06/07/15 15:14, Daniel Vetter wrote:
On Fri, Jul 03, 2015 at 01:30:33PM +0100, Dave Gordon wrote:
Turn on interrupt steering to route necessary interrupts to GuC.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
On ma, 2015-07-06 at 17:04 +0100, Chris Wilson wrote:
On Mon, Jul 06, 2015 at 06:56:00PM +0300, Imre Deak wrote:
On ma, 2015-07-06 at 16:33 +0100, Chris Wilson wrote:
On Mon, Jul 06, 2015 at 05:29:39PM +0200, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 03:57:44PM +0100, Chris Wilson
On 06/07/15 15:28, Daniel Vetter wrote:
On Fri, Jul 03, 2015 at 01:30:27PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
This uses the common firmware loader to fetch the firmware image,
then loads it into the GuC's memory via a dedicated DMA engine.
This patch is derived from GuC
On Mon, Jul 06, 2015 at 02:11:55PM -0300, Paulo Zanoni wrote:
2015-07-06 13:43 GMT-03:00 Vivi, Rodrigo rodrigo.v...@intel.com:
On Fri, 2015-07-03 at 09:10 +0200, Daniel Vetter wrote:
On Thu, Jul 02, 2015 at 04:41:32PM +, Vivi, Rodrigo wrote:
On Thu, 2015-07-02 at 13:03 -0300, Paulo
On Mon, Jul 06, 2015 at 08:25:56PM +0200, Daniel Vetter wrote:
atm QA rolls their own thing, developers on mesa side have ministat, and
it looks like you want to create something in igt. I know it's easier, but
I'd like to share as much tooling between QA and devs as possible. And
that kinda
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