Prior to display version 12, platforms had DDI ports A,B,C,D,E,F
represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of
the ports were in the same order as the ports. So the port enums
were directly used as index to calculate the
On Tue, 04 Oct 2022, Jani Nikula wrote:
> On Fri, 30 Sep 2022, Matt Roper wrote:
>> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
>> b/drivers/gpu/drm/i915/i915_reg_defs.h
>> index 8f486f77609f..e823869b9afd 100644
>> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
>> +++
On 04/10/2022 14:00, Tvrtko Ursulin wrote:
On 04/10/2022 10:29, Tvrtko Ursulin wrote:
On 03/10/2022 20:24, Ashutosh Dixit wrote:
PMU and sysfs use different wakeref's to "interpret" zero freq. Sysfs
uses
runtime PM wakeref (see intel_rps_read_punit_req and
From: Ville Syrjälä
I had to stare at the pps stuff again while dealing with the -stable
pps regression. While doing that I figured I'd try to make it so we
don't accidentally use the wrong pps during the panle probe when we
don't yet have the VBT parsed. So here's an attempt at deducing the
On Tue, 04 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename a few functions from intel_crtc_foo_init() to
> intel_foo_crtc_init() so that the namespaec clearly
> indicates what feature/file we're talking about.
>
> If left out intel_crtc_crc_init() because the whole crc
*I
>
On 10/4/2022 4:14 AM, Tvrtko Ursulin wrote:
On 03/10/2022 13:16, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Patch which added graceful exit for non-persistent contexts missed the
fact it is not enough to set the exiting flag on a context and let the
backend handle it from there.
GuC
On Tue, 04 Oct 2022, Andrzej Hajda wrote:
> Two small changes in intel_uncore_rmw will allow to use it more broadly:
> - write register unconditionally, for use with latch registers,
> - return old value of the register, IRQ cleanup and similar.
>
> If we really want to keep write-only-if-changed
Looks like vma and gtt mock selftests overwrite the ggtt
initialized by mock_gem_device() by calling intel_gt_assign_ggtt()
and mock_init_ggtt() functions.
The side effect seems to be mock_destroy_device() tries to
release the ggtt already released by mock_fini_ggtt() instead of
releasing the ggtt
On 04/10/2022 09:20, Niranjana Vishwanathapura wrote:
Looks like vma and gtt mock selftests overwrite the ggtt
initialized by mock_gem_device() by calling intel_gt_assign_ggtt()
and mock_init_ggtt() functions.
The side effect seems to be mock_destroy_device() tries to
release the ggtt already
On Mon, 26 Sep 2022, Ville Syrjala wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index b8dce4e9ac54..d419f4f98d28 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++
On Tue, Oct 04, 2022 at 11:33:10AM +0100, Matthew Auld wrote:
> For these types of display buffers, we need to able to CPU access some
> part of the backing memory in prepare_plane_clear_colors(). As a result
> we need to ensure we always place in the mappable part of lmem, which
> becomes
It turns out that on production DG2/ATS HW we should have support for
PS64. This feature allows to provide a 64K TLB hint at the PTE level,
which is a lot more flexible than the current method of enabling 64K GTT
pages for the entire page-table, since that leads to all kinds of
annoying
On some platforms we potentially have different alignment restrictions
depending on the memory type. We also now have different alignment
restrictions for the same region across different kernel versions.
Extend the region query to return the minimum required GTT alignment.
Testcase:
On Tue, Oct 04, 2022 at 03:35:44PM +0300, Ville Syrjälä wrote:
> On Mon, Oct 03, 2022 at 08:28:50PM +0200, Thorsten Leemhuis wrote:
> >
> >
> > On 03.10.22 19:48, Ville Syrjälä wrote:
> > > On Mon, Oct 03, 2022 at 08:45:18PM +0300, Ville Syrjälä wrote:
> > >> On Sat, Oct 01, 2022 at 12:07:39PM
On Fri, 30 Sep 2022, Matt Roper wrote:
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
> b/drivers/gpu/drm/i915/i915_reg_defs.h
> index 8f486f77609f..e823869b9afd 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -104,22 +104,16 @@ typedef
On platforms like DG2, it looks like the dpt path here is missing the
migrate-to-lmem step on discrete platforms.
v2:
- Move the vma_pin() under the for_i915_gem_ww(), otherwise the
object can be moved after dropping the lock and then doing the pin.
Fixes: 33e7a975103c ("drm/i915/xelpd:
For these types of display buffers, we need to able to CPU access some
part of the backing memory in prepare_plane_clear_colors(). As a result
we need to ensure we always place in the mappable part of lmem, which
becomes necessary on small-bar systems.
v2(Nirmoy & Ville):
- Add some commentary
In the next patch we want to move the object (if the current resource is
not compatible), to the mappable part of lmem for some display buffers.
Currently that requires being able to unset the I915_BO_ALLOC_GPU_ONLY
hint.
Signed-off-by: Matthew Auld
Cc: Jianshui Yu
Cc: Ville Syrjälä
Cc: Nirmoy
The copy is async (if there even is one), but when later updating the
GGTT we always sync against the binding, which will in turn sync against
any moves.
Signed-off-by: Matthew Auld
Cc: Jianshui Yu
Cc: Ville Syrjälä
Cc: Nirmoy Das
Reviewed-by: Nirmoy Das
---
On small-bar systems we could be given something non-mappable here,
which leads to nasty oops. Make this nicer by checking if the resource
is mappable or not, and return an error otherwise.
v2: drop GEM_BUG_ON(flags & I915_BO_ALLOC_GPU_ONLY)
Signed-off-by: Matthew Auld
Cc: Jianshui Yu
Cc:
== Series Details ==
Series: drm/i915/display: Don't use port enum as register offset (rev8)
URL : https://patchwork.freedesktop.org/series/108833/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Tue, Oct 04, 2022 at 03:40:55PM +0200, Greg Kroah-Hartman wrote:
> On Tue, Oct 04, 2022 at 06:46:10AM -0500, David Matthew Mattli wrote:
> > Thorsten Leemhuis writes:
> >
> > > On 03.10.22 19:48, Ville Syrjälä wrote:
> > >> On Mon, Oct 03, 2022 at 08:45:18PM +0300, Ville Syrjälä wrote:
> > >>>
On Tue, 04 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> I had to stare at the pps stuff again while dealing with the -stable
> pps regression. While doing that I figured I'd try to make it so we
> don't accidentally use the wrong pps during the panle probe when we
> don't yet have
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: enable PS64 support for DG2
URL : https://patchwork.freedesktop.org/series/109384/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12210 -> Patchwork_109384v1
On Tue, Oct 04, 2022 at 02:19:15PM +0100, Matthew Auld wrote:
> For these types of display buffers, we need to able to CPU access some
> part of the backing memory in prepare_plane_clear_colors(). As a result
> we need to ensure we always place in the mappable part of lmem, which
> becomes
On 04/10/2022 10:29, Tvrtko Ursulin wrote:
On 03/10/2022 20:24, Ashutosh Dixit wrote:
PMU and sysfs use different wakeref's to "interpret" zero freq. Sysfs
uses
runtime PM wakeref (see intel_rps_read_punit_req and
intel_rps_read_actual_frequency). PMU uses the GT parked/unparked
wakeref. In
On Tue, Oct 04, 2022 at 02:19:13PM +0100, Matthew Auld wrote:
> On platforms like DG2, it looks like the dpt path here is missing the
> migrate-to-lmem step on discrete platforms.
>
> v2:
> - Move the vma_pin() under the for_i915_gem_ww(), otherwise the
> object can be moved after dropping
On Tue, Oct 04, 2022 at 06:46:10AM -0500, David Matthew Mattli wrote:
> Thorsten Leemhuis writes:
>
> > On 03.10.22 19:48, Ville Syrjälä wrote:
> >> On Mon, Oct 03, 2022 at 08:45:18PM +0300, Ville Syrjälä wrote:
> >>> On Sat, Oct 01, 2022 at 12:07:39PM +0200, Thorsten Leemhuis wrote:
> On
On 04.10.2022 16:03, Jani Nikula wrote:
> On Tue, 04 Oct 2022, Balasubramani Vivekanandan
> wrote:
> > Prior to display version 12, platforms had DDI ports A,B,C,D,E,F
> >
> > represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of
> >
> > the ports
On 10/4/2022 3:19 PM, Matthew Auld wrote:
For these types of display buffers, we need to able to CPU access some
part of the backing memory in prepare_plane_clear_colors(). As a result
we need to ensure we always place in the mappable part of lmem, which
becomes necessary on small-bar systems.
== Series Details ==
Series: drm/i915/display: Don't use port enum as register offset (rev8)
URL : https://patchwork.freedesktop.org/series/108833/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12211 -> Patchwork_108833v8
On Tue, Oct 04, 2022 at 04:44:35PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 04, 2022 at 03:40:55PM +0200, Greg Kroah-Hartman wrote:
> > On Tue, Oct 04, 2022 at 06:46:10AM -0500, David Matthew Mattli wrote:
> > > Thorsten Leemhuis writes:
> > >
> > > > On 03.10.22 19:48, Ville Syrjälä wrote:
> >
From: Ville Syrjälä
Restate the vlv_pipe_check() stuff in terms of PPS index
(rather than pipe, which it is on VLV/CHV) so that we can
reuse this same mechanim on other platforms as well.
Cc: Animesh Manna
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_pps.c | 27
From: Ville Syrjälä
Currently on bxt/glk we just grab the power sequencer index from
the VBT data even though it may not have been parsed yet. That
could lead us to using the incorrect power sequencer during the
initial panel probe.
To avoid that let's try to read out the current state of the
Enable the SDP split configuration for DP2.0.
v2: Move the register handling out of compute config function (JaniN)
v3: Patch styling and register access based on platform support (JaniN)
Bspec: 67768
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_audio.c| 12
On Tue, 04 Oct 2022, Balasubramani Vivekanandan
wrote:
> Prior to display version 12, platforms had DDI ports A,B,C,D,E,F
>
> represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of
>
> the ports were in the same order as the ports. So the port
On 10/4/2022 1:49 PM, Matthew Auld wrote:
On some platforms we potentially have different alignment restrictions
depending on the memory type. We also now have different alignment
restrictions for the same region across different kernel versions.
Extend the region query to return the minimum
Get the small-bar related stuff at: 525e93f6317a ("drm/i915/uapi: add
NEEDS_CPU_ACCESS hint"), and drop the local related bits.
Signed-off-by: Matthew Auld
Cc: Andrzej Hajda
Cc: Nirmoy Das
Reviewed-by: Nirmoy Das
---
include/drm-uapi/i915_drm.h| 182 +
rsvd1 is u64 here.
Signed-off-by: Matthew Auld
Cc: Andrzej Hajda
Cc: Nirmoy Das
Reviewed-by: Nirmoy Das
---
tests/i915/i915_query.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 2744421c..b92d7593 100644
---
No longer reserved, in the near future this will be the GTT alignment.
Signed-off-by: Matthew Auld
Cc: Andrzej Hajda
Cc: Nirmoy Das
Reviewed-by: Nirmoy Das
---
tests/i915/i915_query.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index
Make sure we can always place an object at some GTT address, so
long as we adhere to the min GTT alignment for the given region.
Signed-off-by: Matthew Auld
Cc: Andrzej Hajda
Cc: Nirmoy Das
Reviewed-by: Nirmoy Das
---
tests/i915/gem_create.c | 117
1
Ensure the kernel is reporting "normal" values here, based on our
current expectations.
v2:
- Split the rsvd0 check out, so we can in theory land that patch by
itself (since that will fix the kernel failure vs old igt and could
be merged early).
- s/4096/PAGE_SIZE/ (Nirmoy)
This is a prep patch for a patch series in which register offset of the
DDI ports are not calculated using the port enums but using a different
datastructure part of the device info.
So the device info is passed as a parameter to the macro DDI_BUF_CTL but
unused yet.
Signed-off-by: Balasubramani
With the index required for DDI register offset calculation available in
the device info, the macros which used port enums to calculate the DDI
register offsets i.e. DDI_BUF_CTL and DDI_CLK_SEL are updated to make
use of the index rather than enum directly.
Any new macros access that DDI registers
Port enums are no more used in the DDI register offset caculcation. We
can remove the platform specific port redefinitions. Along with it we
also get rid of the code required for handling these special
definitions.
Signed-off-by: Balasubramani Vivekanandan
---
port_identifier function was broken when TypeC ports were using enum
aliases. It would return wrong string for TypeC ports.
With unique enums for DDI ports now, fix port_identifier to cover all
ports.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_display.h |
Prior to display version 12, platforms had DDI ports A,B,C,D,E,F
represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of
the ports was in the same order as the ports. So the port enums
were directly used as index to calculate the register offset of the
ports.
Starting in display
DDI_CLK_SEL is an another macro which returns the register offset based
on DDI port enum. So DDI_CLK_SEL has to be prepared for the new method
being developed for calculating the register offsets of DDI ports.
Macro receives i915 private structure as new parameter for the upcoming
changes.
DDI port enums PORT_G/H/I were added in the commit -
"6c8337dafaa9 drm/i915/tgl: Add additional ports for Tiger Lake" to
identify new ports added in the platform.
In the subsequent commits those ports were identified by new enums
PORT_TC1/TC2/TC3.. to differentiate TypeC ports from non-TypeC.
From: Ville Syrjälä
Rename a few functions from intel_crtc_foo_init() to
intel_foo_crtc_init() so that the namespaec clearly
indicates what feature/file we're talking about.
If left out intel_crtc_crc_init() because the whole crc
stuff uses intel_crtc_ as its namespace currently.
Suggested-by:
== Series Details ==
Series: Simplify uncore register updates
URL : https://patchwork.freedesktop.org/series/109374/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12207_full -> Patchwork_109374v1_full
Summary
---
On 04.10.2022 01:45, Andi Shyti wrote:
Hi Andrzej,
[...]
@@ -847,7 +847,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
}
if (!dev_priv->display.vbt.int_lvds_support) {
- drm_dbg_kms(_priv->drm,
+ drm_dbg_kms(dev,
On Mon, 03 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Only report DRRS capability for the connector if its fixed_modes
> list contains at least two modes capable of seamless DRRS switch
> between them.
>
> Signed-off-by: Ville Syrjälä
Makes sense,
Reviewed-by: Jani Nikula
>
== Series Details ==
Series: drm/i915/pmu: Match frequencies reported by PMU and sysfs
URL : https://patchwork.freedesktop.org/series/109372/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12206_full -> Patchwork_109372v1_full
On Tue, 04 Oct 2022, Andrzej Hajda wrote:
> On 04.10.2022 09:22, Jani Nikula wrote:
>> On Tue, 04 Oct 2022, Andrzej Hajda wrote:
>>> Alias is shorter and more readable.
>> But it's preferrable to *not* have struct drm_device * around at all,
>> only struct drm_i915_private *.
>>
>> So this is
== Series Details ==
Series: drm/i915/slpc: Update frequency debugfs for SLPC (rev2)
URL : https://patchwork.freedesktop.org/series/109328/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12207_full -> Patchwork_109328v2_full
On Mon, 26 Sep 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Start to clean up the mess around DPLL IDs a bit by removing
> the nasty assumption that the index of the DPLL in the
> arrays matches its ID. Fortunately we did have a WARN
> i nthere to cathc mistakes, but better to not has
Hi Jani,
On Tue, Oct 04, 2022 at 11:46:38AM +0300, Jani Nikula wrote:
> On Tue, 04 Oct 2022, Andrzej Hajda wrote:
> > On 04.10.2022 09:22, Jani Nikula wrote:
> >> On Tue, 04 Oct 2022, Andrzej Hajda wrote:
> >>> Alias is shorter and more readable.
> >> But it's preferrable to *not* have struct
On 2022-09-23 at 18:01:37 +0200, Andrzej Hajda wrote:
> Tests on DG2 show that context cancel can take even 350ms,
> due to error state capturing in guc_handle_context_reset.
> Since it happens only in debug mode and tests runs in debug mode
> it should be fine to adjust the timeout.
> Let's
On 04/10/2022 12:22, Ville Syrjälä wrote:
On Tue, Oct 04, 2022 at 11:33:08AM +0100, Matthew Auld wrote:
On platforms like DG2, it looks like the dpt path here is missing the
migrate-to-lmem step on discrete platforms.
Fixes: 33e7a975103c ("drm/i915/xelpd: First stab at DPT support")
On Mon, Oct 03, 2022 at 08:28:50PM +0200, Thorsten Leemhuis wrote:
>
>
> On 03.10.22 19:48, Ville Syrjälä wrote:
> > On Mon, Oct 03, 2022 at 08:45:18PM +0300, Ville Syrjälä wrote:
> >> On Sat, Oct 01, 2022 at 12:07:39PM +0200, Thorsten Leemhuis wrote:
> >>> On 30.09.22 14:26, Jerry Ling wrote:
>
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: enable PS64 support for DG2
URL : https://patchwork.freedesktop.org/series/109384/
State : warning
== Summary ==
Error: dim checkpatch failed
88944e5bbc43 drm/i915: enable PS64 support for DG2
-:15: ERROR:GIT_COMMIT_ID:
On Tue, 04 Oct 2022, Andrzej Hajda wrote:
> Alias is shorter and more readable.
But it's preferrable to *not* have struct drm_device * around at all,
only struct drm_i915_private *.
So this is kind of going the wrong way.
BR,
Jani.
>
> Signed-off-by: Andrzej Hajda
> ---
>
On 03/10/2022 20:32, Matt Roper wrote:
On Mon, Oct 03, 2022 at 09:56:18AM +0100, Tvrtko Ursulin wrote:
Hi Matt,
On 01/10/2022 01:45, Matt Roper wrote:
MTL's media GT only has a single type of steering ("OAADDRM") which
selects between media slice 0 and media slice 1. We'll always steer to
For these types of display buffers, we need to able to CPU access some
part of the backing memory in prepare_plane_clear_colors(). As a result
we need to ensure we always place in the mappable part of lmem, which
becomes necessary on small-bar systems.
v2(Nirmoy & Ville):
- Add some commentary
On small-bar systems we could be given something non-mappable here,
which leads to nasty oops. Make this nicer by checking if the resource
is mappable or not, and return an error otherwise.
v2: drop GEM_BUG_ON(flags & I915_BO_ALLOC_GPU_ONLY)
Signed-off-by: Matthew Auld
Cc: Jianshui Yu
Cc:
In the next patch we want to move the object (if the current resource is
not compatible), to the mappable part of lmem for some display buffers.
Currently that requires being able to unset the I915_BO_ALLOC_GPU_ONLY
hint.
Signed-off-by: Matthew Auld
Cc: Jianshui Yu
Cc: Ville Syrjälä
Cc: Nirmoy
The copy is async (if there even is one), but when later updating the
GGTT we always sync against the binding, which will in turn sync against
any moves.
Signed-off-by: Matthew Auld
Cc: Jianshui Yu
Cc: Ville Syrjälä
Cc: Nirmoy Das
Reviewed-by: Nirmoy Das
---
On platforms like DG2, it looks like the dpt path here is missing the
migrate-to-lmem step on discrete platforms.
Fixes: 33e7a975103c ("drm/i915/xelpd: First stab at DPT support")
Signed-off-by: Matthew Auld
Cc: Jianshui Yu
Cc: Ville Syrjälä
Cc: Nirmoy Das
---
On Tue, 04 Oct 2022, Andi Shyti wrote:
> Hi Jani,
>
> On Tue, Oct 04, 2022 at 11:46:38AM +0300, Jani Nikula wrote:
>> On Tue, 04 Oct 2022, Andrzej Hajda wrote:
>> > On 04.10.2022 09:22, Jani Nikula wrote:
>> >> On Tue, 04 Oct 2022, Andrzej Hajda wrote:
>> >>> Alias is shorter and more readable.
In the next patch we want to move the object (if the current resource is
not compatible), to the mappable part of lmem for some display buffers.
Currently that requires being able to unset the I915_BO_ALLOC_GPU_ONLY
hint.
Signed-off-by: Matthew Auld
Cc: Jianshui Yu
Cc: Ville Syrjälä
Cc: Nirmoy
On platforms like DG2, it looks like the dpt path here is missing the
migrate-to-lmem step on discrete platforms.
v2:
- Move the vma_pin() under the for_i915_gem_ww(), otherwise the
object can be moved after dropping the lock and then doing the pin.
Fixes: 33e7a975103c ("drm/i915/xelpd:
On small-bar systems we could be given something non-mappable here,
which leads to nasty oops. Make this nicer by checking if the resource
is mappable or not, and return an error otherwise.
v2: drop GEM_BUG_ON(flags & I915_BO_ALLOC_GPU_ONLY)
Signed-off-by: Matthew Auld
Cc: Jianshui Yu
Cc:
For these types of display buffers, we need to able to CPU access some
part of the backing memory in prepare_plane_clear_colors(). As a result
we need to ensure we always place in the mappable part of lmem, which
becomes necessary on small-bar systems.
v2(Nirmoy & Ville):
- Add some commentary
Hi Matt,
On 10/3/2022 7:24 PM, Matthew Auld wrote:
Ensure the kernel is reporting "normal" values here, based on our
current expectations.
Signed-off-by: Matthew Auld
Cc: Andrzej Hajda
Cc: Nirmoy Das
---
tests/i915/i915_query.c | 12 ++--
1 file changed, 10 insertions(+), 2
The copy is async (if there even is one), but when later updating the
GGTT we always sync against the binding, which will in turn sync against
any moves.
Signed-off-by: Matthew Auld
Cc: Jianshui Yu
Cc: Ville Syrjälä
Cc: Nirmoy Das
Reviewed-by: Nirmoy Das
---
== Series Details ==
Series: series starting with [v5,1/5] drm/i915: remove the TODO in
pin_and_fence_fb_obj
URL : https://patchwork.freedesktop.org/series/109382/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12210 -> Patchwork_109382v1
On 04.10.2022 09:22, Jani Nikula wrote:
On Tue, 04 Oct 2022, Andrzej Hajda wrote:
Alias is shorter and more readable.
But it's preferrable to *not* have struct drm_device * around at all,
only struct drm_i915_private *.
So this is kind of going the wrong way.
I guess this is some
== Series Details ==
Series: drm/i915/selftests: Fix overwriting ggtt
URL : https://patchwork.freedesktop.org/series/109379/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12208 -> Patchwork_109379v1
Summary
---
On Tue, Oct 04, 2022 at 11:33:08AM +0100, Matthew Auld wrote:
> On platforms like DG2, it looks like the dpt path here is missing the
> migrate-to-lmem step on discrete platforms.
>
> Fixes: 33e7a975103c ("drm/i915/xelpd: First stab at DPT support")
> Signed-off-by: Matthew Auld
> Cc: Jianshui
On 04/10/2022 12:28, Ville Syrjälä wrote:
On Tue, Oct 04, 2022 at 11:33:10AM +0100, Matthew Auld wrote:
For these types of display buffers, we need to able to CPU access some
part of the backing memory in prepare_plane_clear_colors(). As a result
we need to ensure we always place in the
On Tue, Oct 04, 2022 at 12:51:11PM +0100, Matthew Auld wrote:
> On 04/10/2022 12:28, Ville Syrjälä wrote:
> > On Tue, Oct 04, 2022 at 11:33:10AM +0100, Matthew Auld wrote:
> >> For these types of display buffers, we need to able to CPU access some
> >> part of the backing memory in
On Mon, 03 Oct 2022, Vinay Belgaumkar wrote:
> Move it to the RPS source file.
The idea was that the 1st patch would be non-functional code
movement. This is still a functional change.
Or you can do the functional changes first, and then move code, as long
as you don't combine code movement
On Tue, 27 Sep 2022, Animesh Manna wrote:
> From display gen12 onwards to support dual EDP two instances of pps added.
> Currently backlight controller and pps instance can be mapped together
> for a specific panel. Extended support for gen12 for dual EDP usage.
Frankly the dual PPS support was
Hi G.G.
On Mon, Oct 03, 2022 at 08:02:42PM +0300, Gwan-gyeong Mun wrote:
> Remove unused function prototype; intel_gt_create_kobj()
>
> Cc: Andi Shyti
> Signed-off-by: Gwan-gyeong Mun
and pushed in intel-drm-intel-gt-next!
Thank you!
Andi
> ---
> drivers/gpu/drm/i915/gt/intel_gt_sysfs.h |
On Tue, 04 Oct 2022, "Jiri Slaby (SUSE)" wrote:
> When DRM_I915=y and BACKLIGHT_CLASS_DEVICE=m, the build fails:
> ld: drivers/gpu/drm/i915/display/intel_backlight.o: in function
> `intel_backlight_device_register':
> intel_backlight.c:(.text+0x5587): undefined reference to
>
On Mon, 26 Sep 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No one really cares how we store the shared_dplls. Currently
> it happens to be an array, but we could change that to a more
> flexible scheme at some point. Hide the implementation details
> behind an iterator macro.
>
> The
On Tue, 04 Oct 2022, "Jiri Slaby (SUSE)" wrote:
> The last user of macros from that include was removed in 2018 by the
> commit below.
>
> Fixes: 6cc42152b02b ("drm/i915: Remove support for legacy debugfs crc
> interface")
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc:
== Series Details ==
Series: series starting with [v5,1/5] drm/i915: remove the TODO in
pin_and_fence_fb_obj
URL : https://patchwork.freedesktop.org/series/109382/
State : warning
== Summary ==
Error: dim checkpatch failed
0fc08f3e0045 drm/i915: remove the TODO in pin_and_fence_fb_obj
== Series Details ==
Series: series starting with [v5,1/5] drm/i915: remove the TODO in
pin_and_fence_fb_obj
URL : https://patchwork.freedesktop.org/series/109382/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: drm/i915/selftests: Fix overwriting ggtt
URL : https://patchwork.freedesktop.org/series/109379/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12208_full -> Patchwork_109379v1_full
Summary
On Mon, 03 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Now that we track the VBT drrs type per-panel we can move the
> has_drrs_modes() check to the panel init rather than doing it
> for every intel_panel_drrs_type() call.
And we also get the correct DRRS type logging hint early
On 03/10/2022 20:24, Ashutosh Dixit wrote:
PMU and sysfs use different wakeref's to "interpret" zero freq. Sysfs uses
runtime PM wakeref (see intel_rps_read_punit_req and
intel_rps_read_actual_frequency). PMU uses the GT parked/unparked
wakeref. In general the GT wakeref is held for less time
On 03/10/2022 13:16, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Patch which added graceful exit for non-persistent contexts missed the
fact it is not enough to set the exiting flag on a context and let the
backend handle it from there.
GuC backend cannot handle it because it runs
On Tue, Oct 04, 2022 at 12:54:33PM +0100, Matthew Auld wrote:
> On 04/10/2022 12:22, Ville Syrjälä wrote:
> > On Tue, Oct 04, 2022 at 11:33:08AM +0100, Matthew Auld wrote:
> >> On platforms like DG2, it looks like the dpt path here is missing the
> >> migrate-to-lmem step on discrete platforms.
>
On Thu, Sep 08, 2022 at 05:06:02AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Document and future-proof preemption control policy
> URL : https://patchwork.freedesktop.org/series/108275/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from
On Fri, 16 Sep 2022, Ankit Nautiyal wrote:
> Fix issues in HFVSDB parsing for DSC support.
> Also minor refactoring in Logging.
>
> Split from original patch into a new series.
> https://patchwork.freedesktop.org/patch/495193/
>
> v2: Minor styling fixes.
Thanks for the patches, pushed to
== Series Details ==
Series: series starting with [v5,1/5] drm/i915: remove the TODO in
pin_and_fence_fb_obj
URL : https://patchwork.freedesktop.org/series/109389/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: series starting with [v5,1/5] drm/i915: remove the TODO in
pin_and_fence_fb_obj
URL : https://patchwork.freedesktop.org/series/109389/
State : warning
== Summary ==
Error: dim checkpatch failed
bc460e1488f8 drm/i915: remove the TODO in pin_and_fence_fb_obj
== Series Details ==
Series: drm/i915: Clean up some namespacing
URL : https://patchwork.freedesktop.org/series/109393/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12214 -> Patchwork_109393v1
Summary
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