The only missing part is hot plug notification for DP -- most DP monitors in
the market don't support DP audio well. So I cannot test this for now.
btw, we'd like to buy a Philips 221P3LPYEB that _seems_ to have DP
audio support. I'd appreciate if any one can help confirm.
Thanks,
Fengguang
https://bugzilla.redhat.com/show_bug.cgi?id=750006
Signed-off-by: Adam Jackson a...@redhat.com
---
drivers/gpu/drm/i915/intel_lvds.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index
On Wed, 26 Oct 2011 10:53:11 -0400, Adam Jackson a...@redhat.com wrote:
On Wed, 2011-10-19 at 10:28 -0400, Adam Jackson wrote:
I assume the SDVO LVDS options block in the VBT would tell us what bits
are correct to program here, but intel_bios.h documents only the layout
of that structure,
This is based on original Keith Packard's patch for enabling rc6 by
default, with the only change that we do only enable RC6 by default on IVB
onwards.
Due to the random issues related to RC6 on SNB when VTd is enabled, we'll
not enable them by default on this platform yet. It can always be
The change which added support for default settings for fbc has not
changed the variable type of i915_enable_fbc from unsigned int to int. So
we were unable to get into the default ('-1') state with the default
settings.
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Eugeni
This adds a default setting for semaphores parameter, and enables
semaphores by default on IVB.
For now, as semaphores interaction with VTd causes random issues on SNB,
we do not enable them by default. But they can still be enabled via the
semaphores=1 kernel parameter.
CC: Daniel Vetter
Fix function name in comments, a left-over from when i965_reset was
renamed to i915_reset.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
This prevents an in-kernel division by zero which happens when we are
asking for i915_chipset_val too quickly, or within a race condition
between the power monitoring thread and userspace accesses via debugfs.
The issue can be reproduced easily via the following command:
while ``; do cat
This allows to avoid talking to a non-responding bus repeatedly until we
finally timeout after 15 attempts. We can do this by catching the -ENXIO
error, provided by i2c_algo_bit:bit_doAddress call.
Within the bit_doAddress we already try 3 times to get the edid data, so
if the routine tells us
After checking the specs and discussing with Jesse, turns out CxSR is not
available on Ironlake and gen5, and its advertisement on the device
description is misleading.
Acked-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
Hi,
here comes my queue of patches for next 3.2 push.
patch1 removes CxSR on ILK, following the specifications
patch2 improved edid timings by reducing number of unnecessary retries
patch3 prevents a division-by-zero in kernel when querying for gpu power on ILK
patch4,5 fix typos in comments
No effect besides printing the result in dmesg if debugging is enabled.
Signed-off-by: Adam Jackson a...@redhat.com
---
drivers/gpu/drm/i915/intel_sdvo.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
On 11/28/11 12:28 PM, Keith Packard wrote:
On Wed, 26 Oct 2011 10:53:11 -0400, Adam Jacksona...@redhat.com wrote:
On Wed, 2011-10-19 at 10:28 -0400, Adam Jackson wrote:
I assume the SDVO LVDS options block in the VBT would tell us what bits
are correct to program here, but intel_bios.h
2011/11/28 Adam Jackson a...@redhat.com
On 11/28/11 12:28 PM, Keith Packard wrote:
On Wed, 26 Oct 2011 10:53:11 -0400, Adam Jacksona...@redhat.com wrote:
On Wed, 2011-10-19 at 10:28 -0400, Adam Jackson wrote:
I assume the SDVO LVDS options block in the VBT would tell us what bits
are
On Mon, Nov 28, 2011 at 04:15:21PM -0200, Eugeni Dodonov wrote:
This is based on original Keith Packard's patch for enabling rc6 by
default, with the only change that we do only enable RC6 by default on IVB
onwards.
Due to the random issues related to RC6 on SNB when VTd is enabled, we'll
The problem this patch solves is that the forcewake accounting
necessary for register reads is protected by dev-struct_mutex. But the
hangcheck and error_capture code need to access registers without
grabbing this mutex because we hold it while waiting for the gpu.
So a new lock is required.
This was forgotten in the original multi-threaded forcewake
conversion:
commit 8d715f0024f64ad1b1be85d8c081cf577944c847
Author: Keith Packard kei...@keithp.com
Date: Fri Nov 18 20:39:01 2011 -0800
drm/i915: add multi-threaded forcewake support
Signed-Off-by: Daniel Vetter
We currently have 3 register for which we must not grab forcewake for:
FORCEWAKE, FROCEWAKE_MT and ECOBUS.
- FROCEWAKE is excluded in the NEEDS_FORCE_WAKE macro and accessed
with _NOTRACE.
- FROCEWAKE_MT is just accessed with _NOTRACE.
- ECOBUS is only excluded in the macro.
In fear of an
... like for forcewake, which protects everything _but_ display.
Expect more things (like gtt abstractions, rings, inter-ring sync)
to come.
Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.c |6 +++---
drivers/gpu/drm/i915/i915_drv.h |8
Hi all,
Changes since the last submission:
- fixed issues pointed out by Chris Wilson on irc.
- fixed an oops on pre-snb, shame on me for that one.
- added two new patches to only bind objects to the global gtt when required.
- added a new patch so that userspace can find out whether ppgtt is on.
To implement a PPGTT for drm/i915 that fully aliases the GTT, we also
need to properly alias the scratch page.
Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/char/agp/intel-gtt.c |9 -
include/drm/intel-gtt.h |2 ++
2 files changed, 6 insertions(+), 5
We need this because ppgtt page directory entries need to be in the
global gtt pagetable.
Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/char/agp/intel-gtt.c |1 +
include/drm/intel-gtt.h |2 ++
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git
This just adds the setup and teardown code for the ppgtt PDE and the
last-level pagetables, which are fixed for the entire lifetime, at
least for the moment.
v2: Kill the stray debug printk noted by and improve the pte
definitions as suggested by Chris Wilson.
Signed-Off-by: Daniel Vetter
This adds support to bind/unbind objects and wires it up. Objects are
only put into the ppgtt when necessary, i.e. at execbuf time.
Objects are still unconditionally put into the global gtt.
v2: Kill the quick hack and explicitly pass cache_level to ppgtt_bind
like for the global gtt function.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_reg.h | 18 ++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9f5dc8..7227446 100644
---
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_debugfs.c | 38 +++
1 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e0bb93d..e3da225
v2: Chris Wilson suggested to allocate the error_state with kzalloc
for better paranioa. Also kill existing spurious clears of the
error_state while at it.
Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_debugfs.c |8 ++--
drivers/gpu/drm/i915/i915_drv.h
Name the function accordingly. Suggested by Chris Wilson.
Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.c |4 ++--
drivers/gpu/drm/i915/i915_drv.h |4 ++--
drivers/gpu/drm/i915/intel_display.c |8
3 files changed, 8
v2: Don't try to enable ppgtt on pre-snb.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.c |2 ++
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_gem.c | 39 +++
3 files changed, 42
And track the existence of such a binding similar to the aliasing
ppgtt case. Speeds up binding/unbinding in the common case where we
only need a ppgtt binding (which is accessed in a cpu coherent fashion
by the gpu) and no gloabl gtt binding (which needs uc writes for the
ptes).
Signed-Off-by:
And track the existence of such a binding similar to the aliasing
ppgtt case. Speeds up binding/unbinding in the common case where we
only need a ppgtt binding (which is accessed in a cpu coherent fashion
by the gpu) and no gloabl gtt binding (which needs uc writes for the
ptes).
This patch just
PIPE_CONTROL on snb needs global gtt mappings in place to workaround a
hw gotcha. No other commands need such a workaround. Luckily we can
detect a PIPE_CONTROL commands easily because they have a write_domain
= I915_GEM_DOMAIN_INSTRUCTION (and nothing else has that).
Signed-off-by: Daniel Vetter
Now that everything is in place, only bind to the global gtt
when actually required. Patch split-up suggested by Chris Wilson.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_gem.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git
This is based on original Keith Packard's patch for enabling rc6 by
default, with the only change that we do only enable RC6 by default on IVB
onwards.
Due to the random issues related to RC6 on SNB when VTd is enabled, we'll
not enable them by default on this platform yet. It can always be
On Mon, Nov 28, 2011 at 10:24:58PM -0200, Eugeni Dodonov wrote:
This is based on original Keith Packard's patch for enabling rc6 by
default, with the only change that we do only enable RC6 by default on IVB
onwards.
Due to the random issues related to RC6 on SNB when VTd is enabled, we'll
On Mon, 28 Nov 2011 22:24:54 +0100, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
And track the existence of such a binding similar to the aliasing
ppgtt case. Speeds up binding/unbinding in the common case where we
only need a ppgtt binding (which is accessed in a cpu coherent fashion
by the
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