On Mon, May 26, 2014 at 7:26 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, May 22, 2014 at 05:48:06PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Because of the upcoming vblank interrupt driven watermark update
mechanism we will have use
This is a note to let you know that I've just added the patch titled
drm/i915: Disable self-refresh for untiled fbs on i915gm
to the 3.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
This is a note to let you know that I've just added the patch titled
drm/i915: quirk invert brightness for Acer Aspire 5336
to the 3.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
On Wed, May 21, 2014 at 11:07:21AM +0200, Daniel Vetter wrote:
Hi Greg,
This is a set of drm/i915 patches which didn't apply cleanly on for 3.14. All
absed on 3.14.4. I've left out the bdw patches for now and will sign up
someone
else for that task.
Thanks for the patches, all now
This is a note to let you know that I've just added the patch titled
drm/i915: Fix unsafe loop iteration over vma whilst unbinding them
to the 3.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the
This is a note to let you know that I've just added the patch titled
drm/i915: move power domain init earlier during system resume
to the 3.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch
On Wed, 04 Jun 2014, Ben Widawsky b...@bwidawsk.net wrote:
On Tue, Jun 03, 2014 at 02:52:30PM -0700, Kenneth Graunke wrote:
rendercopy was failing to emit 3DSTATE_WM_DEPTH_STENCIL, which is a new
packet on Broadwell. Mesa emits this packet.
This appears to fix various tests on a fresh boot,
On Wed, 04 Jun 2014, Stéphane Marchesin marc...@chromium.org wrote:
On Tue, Jun 3, 2014 at 1:26 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jun 3, 2014 at 6:40 PM, Stéphane Marchesin marc...@chromium.org
wrote:
On Tue, Apr 29, 2014 at 1:30 PM, Jani Nikula jani.nik...@intel.com wrote:
Hi
On Wed, Jun 4, 2014 at 12:57 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
Touching the VGA resources on an IVB EFI machine causes hard hangs when
we then kick out the efifb. Ouch.
Apparently this also prevents unclaimed register errors on
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Matt Roper
Sent: Friday, May 23, 2014 2:30 AM
To: dri-de...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 6/6] drm/i915: Switch to unified plane cursor
On Wed, 04 Jun 2014, David Herrmann dh.herrm...@gmail.com wrote:
Hi
On Wed, Jun 4, 2014 at 12:57 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
Touching the VGA resources on an IVB EFI machine causes hard hangs when
we then kick out the efifb.
On Tue, 03 Jun 2014, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
The panel power sequencer on vlv doesn't appear to accept changes to its
T12 power down duration during warm reboots. This change forces a delay
for warm reboots to the T12 panel timing as
From: Ville Syrjälä ville.syrj...@linux.intel.com
The EBUSY checking is very fragile currently in case there's any kind
extra delay in the test loop. At least the flip-vs-rmfb fails reliably
on my IVB.
So to make the test less fragile remove the EBUSY check from all the
current flip tests, and
Hi
On Wed, Jun 4, 2014 at 2:20 PM, Jani Nikula jani.nik...@linux.intel.com wrote:
On Wed, 04 Jun 2014, David Herrmann dh.herrm...@gmail.com wrote:
You rely on compiler-optimizations here. dummy_con is not available
if !CONFIG_DUMMY_CONSOLE, but you use it. This causes linker-failure
if
2014-05-22 11:48 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
After we've disabled the planes, it seems like a good idea wait for
the vblank driven watermark updates to finish before we turn off the
vblank interrupts and eventually the entire
Hi,
I took [1] as a base to test DRI3 on Ubuntu/precise AMD64.
Unfortunately, the packages from this repo have no DRI3 support.
So, I packaged some missing stuff, built mesa-10.1.4 and intel-ddx
from Git manually.
In the end I got somehow running a DRI3 system here.
$ grep -A2 intel_drv
2014-06-03 16:32 GMT-03:00 Ville Syrjälä ville.syrj...@linux.intel.com:
On Tue, Jun 03, 2014 at 03:50:12PM -0300, Paulo Zanoni wrote:
2014-05-22 11:48 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add a mechanism by which you can queue up
From: Michel Thierry michel.thie...@intel.com
HDC_CHICKEN0 bit 14 (Fence Destination To SLM Disable) must be
programmed by software to 1h (Disable) to work around a LSLM unit issue.
WaDisableFenceDestinationToSLM is only needed for BDW E,F step.
Issue: APDEV-3096
Signed-off-by: Michel Thierry
Hi Chris,
On 3 June 2014 16:12, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Mon, Jun 02, 2014 at 02:18:14PM +0100, Sam Jansen wrote:
Hello intel-gfx,
I'm working on an application using VA-API for H264 encode+decode, and
JPEG decode on an Atom E3815. Unfortunately we've hit
On Wed, Jun 4, 2014 at 2:11 AM, Jani Nikula jani.nik...@intel.com wrote:
On Wed, 04 Jun 2014, Stéphane Marchesin marc...@chromium.org wrote:
On Tue, Jun 3, 2014 at 1:26 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jun 3, 2014 at 6:40 PM, Stéphane Marchesin marc...@chromium.org
wrote:
On
On Wed, Jun 04, 2014 at 11:01:01AM -0300, Paulo Zanoni wrote:
This function is only called at init/resume. It populates the software
state with something that matches the current hardware state. I guess
a comment explaning the purpose of the function is the best we can do
here, or do you
On Wed, Jun 04, 2014 at 03:56:19PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The EBUSY checking is very fragile currently in case there's any kind
extra delay in the test loop. At least the flip-vs-rmfb fails reliably
on my IVB.
So to
On Wed, Jun 04, 2014 at 09:32:54AM +0100, tim.g...@intel.com wrote:
From: Tim Gore tim.g...@intel.com
In Makefile.sources, kms_fence_pin_leak was in the Multi test list,
ie tests with subtests, whereas it is actually simple/single test.
This was confusing the Android script for enumerating
On Tue, Jun 03, 2014 at 05:51:01PM -0300, Paulo Zanoni wrote:
2014-05-22 11:48 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We need to perform watermark programming before and after changing the
plane configuration. Add two new vfuncs to do
On Wed, Jun 04, 2014 at 06:37:44PM +0200, Sedat Dilek wrote:
DRI2 or DRI3 running here?
I did some more testing and played with UXA/SNA for intel-ddx.
$ egrep -i 'dri2|dri3|present|sna|uxa' Xorg.0.log_UXA
[ 8471.151] (II) intel(0): DRI2: Enabled
[ 8471.151] (II) intel(0): DRI3:
On Wed, Jun 4, 2014 at 6:52 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, Jun 04, 2014 at 06:37:44PM +0200, Sedat Dilek wrote:
DRI2 or DRI3 running here?
I did some more testing and played with UXA/SNA for intel-ddx.
$ egrep -i 'dri2|dri3|present|sna|uxa' Xorg.0.log_UXA
[
2014-05-22 11:48 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Pull the code to locate the other active crtc out from
haswell_mode_set_planes_workaround() into a separate function.
This will have another use later.
Signed-off-by: Ville Syrjälä
On Wed, Jun 4, 2014 at 6:58 PM, Sedat Dilek sedat.di...@gmail.com wrote:
On Wed, Jun 4, 2014 at 6:52 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, Jun 04, 2014 at 06:37:44PM +0200, Sedat Dilek wrote:
DRI2 or DRI3 running here?
I did some more testing and played with UXA/SNA for
2014-05-22 11:48 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
When we switch between one active pipe and multiple active pipes, the
display FIFO gets repartitioned. Disable the LP1+ waterwarks while that
is happening to make sure we don't get any
2014-05-22 11:48 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently ilk_disable_lp_wm() just disabled LP1+ watermarks directly.
However there's nothing preventing someone else from re-enabling them
immediately. To make sure sure LP1+
2014-05-22 11:48 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
When the primary plane is disabled, pick the 5/6 DDB split to give the
sprite as much FIFO space as possible.
The normal heuristic of just looking at the highest valid WM level won't
2014-05-22 11:48 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
ILK and IVB don't like switching between sprite only and primary only
configurations when LP1+ watermarks have been enabled in the recent
past. Like WaCxSRDisabledForSpriteScaling we
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index e768207..b5448d8 100644
---
2014-05-22 11:48 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
If we mark the LP1+ watermarks as disabled every time sprite scaling
is enabled, we end doing pointless work applying watermarks even though
nothing has changed. This is an artifact of
This is breaking -nightly build!
On Wed, Jun 4, 2014 at 11:47 AM, Rodrigo Vivi rodrigo.v...@gmail.com
wrote:
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Wed, May 28, 2014 at 5:57 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, May 27, 2014 at 04:50:14PM -0700, Rodrigo Vivi wrote:
Some registers set during setup might not be persistent after
suspend/resume.
This was causing bugs for some people that was unable to get PSR entry
state
On Wed, Jun 04, 2014 at 03:06:18PM +0100, michel.thie...@intel.com wrote:
From: Michel Thierry michel.thie...@intel.com
HDC_CHICKEN0 bit 14 (Fence Destination To SLM Disable) must be
programmed by software to 1h (Disable) to work around a LSLM unit issue.
WaDisableFenceDestinationToSLM is
This allows the system to enter the lowest power mode during system freeze.
v2: delete force wake timer at suspend (Imre)
v3: add GT work suspend function (Imre)
Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
2014-06-04 15:47 GMT-03:00 Rodrigo Vivi rodrigo.v...@gmail.com:
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
Yeah, this seems to make -nightly compile.
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
1 file changed, 1 insertion(+), 1
On Fri, 2014-05-30 at 11:48 -0700, Jesse Barnes wrote:
From: Kristen Carlson Accardi kris...@linux.intel.com
This matches the runtime suspend paths and allows the system to enter
the lowest power mode at freeze time.
v2: move disable_pc8 call to thaw_early (Imre)
move enable_pc8 to
This allows the system to enter the lowest power mode during system freeze.
v2: delete force wake timer at suspend (Imre)
v3: add GT work suspend function (Imre)
v4: use uncore forcewake reset (Daniel)
Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com
Signed-off-by: Jesse Barnes
From: Clint Taylor clinton.a.tay...@intel.com
Remove OUI read function from the lower half interrupt handler. Upon
closing the eDP panel lid an HPD interrupt is generated. The lower half
handler calls intel_dp_probe_oui() as part of intel_dp_detect().
intel_dp_probe_oui() enables eDP VDD and
Hi folks,
when switching resolutions with xrandr (or otherwise) on the 830MG
chipset, I usually get a Pipe A underrun error,
sometimes resulting in a completely black screen. To my understanding,
the internal screen is connected to pipe B on
this laptop, thus I wonder why I get the error.
BDW uses IVB cursor offsets.
Whithout this patch it is not possible to use multiple outputs with cursor
on BDW.
The cursor gets completely crazy because update position uses the wrong
cursor register for the second pipe.
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
On Wed, Jun 04, 2014 at 05:09:30PM -0700, Rodrigo Vivi wrote:
BDW uses IVB cursor offsets.
Whithout this patch it is not possible to use multiple outputs with cursor
on BDW.
The cursor gets completely crazy because update position uses the wrong
cursor register for the second pipe.
I just noticed and verified this patch fixes this bug:
https://bugs.freedesktop.org/show_bug.cgi?id=79621
On Wed, Jun 4, 2014 at 5:16 PM, Ben Widawsky b...@bwidawsk.net wrote:
On Wed, Jun 04, 2014 at 05:09:30PM -0700, Rodrigo Vivi wrote:
BDW uses IVB cursor offsets.
Whithout this patch
Move rc6_residency_check to subtest, add new rc6_residency_counter subtest
for pm_rc6_residency IGT case.
Test results run on platforms show as below:
On HSW
---
[root@x-hswu opt]# ./pm_rc6_residency
IGT-Version: 1.6-g35b31df (x86_64) (Linux:
From: Dave Airlie airl...@redhat.com
for MST I need to reuse these, so split them out early.
Signed-off-by: Dave Airlie airl...@redhat.com
---
drivers/gpu/drm/i915/intel_ddi.c | 27 ---
drivers/gpu/drm/i915/intel_display.c | 31 ++-
2
Another round of the MST support for i915 haswell.
This relies on the aux locking and i915 irq rework patches I posted
already.
this also splits out some more i915 rework into earlier patches.
The main fix is not talking to devices if HPD isn't asserted, at
least on the dock I have it will
From: Dave Airlie airl...@redhat.com
This is required to get fbcon probing to work on new connectors,
callers should acquire the mode config lock before calling these.
Signed-off-by: Dave Airlie airl...@redhat.com
---
drivers/gpu/drm/drm_fb_helper.c | 53
From: Dave Airlie airl...@redhat.com
This property will be used by the MST code to provide userspace
with a path to parse so it can recognise connectors around hotplugs.
Signed-off-by: Dave Airlie airl...@redhat.com
---
drivers/gpu/drm/drm_crtc.c | 26 ++
From: Dave Airlie airl...@redhat.com
this is just prep work for mst support.
Signed-off-by: Dave Airlie airl...@redhat.com
---
drivers/gpu/drm/i915/intel_ddi.c | 18 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git
From: Dave Airlie airl...@redhat.com
DP MST will need connectors that aren't connected to specific
encoders, add some checks in advance to avoid oopses.
Signed-off-by: Dave Airlie airl...@redhat.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 16 +---
drivers/gpu/drm/i915/i915_irq.c
From: Dave Airlie airl...@redhat.com
This can be called to update things after dynamic connectors/encoders
are created/deleted.
Signed-off-by: Dave Airlie airl...@redhat.com
---
drivers/gpu/drm/drm_crtc.c | 9 +
include/drm/drm_crtc.h | 1 +
2 files changed, 10 insertions(+)
diff
From: Dave Airlie airl...@redhat.com
use the mst helper code to dump the topology in debugfs.
v0.2: drop is_mst check - as we want to dump other info
Signed-off-by: Dave Airlie airl...@redhat.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 23 +++
1 file changed, 23
From: Dave Airlie airl...@redhat.com
---
drivers/gpu/drm/i915/intel_dp_mst.c | 10 ++
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index
On Wed, 2014-05-28 at 15:27 +0530, sourab gupta wrote:
On Mon, 2014-04-14 at 09:45 +, Gupta, Sourab wrote:
From: Akash Goel akash.g...@intel.com
This workaround is needed on VLV for the HW context feature.
It is used after adding the mi_set_context command in ring buffer
for Hw
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