On Tue, 12 Feb 2013, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, Feb 12, 2013 at 07:06:59PM +0200, Jani Nikula wrote:
Keep all the platform output selection in intel_output_setup(), and don't
scatter it around.
I see this as doing the opposite. You are littering an already over
It is customary to end sysfs attributes with a newline.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_sysfs.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915
Amending
commit 4518f611ba21ba165ea3714055938a8984a44ff9
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Wed Jan 23 16:16:35 2013 +0100
drm/i915: dump UTS_RELEASE into the error_state
CC: sta...@vger.kernel.org
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
on top of drm-intel
Previously FBC disabling due to per-chip default was logged as being
disabled per module parameter. Distinguish between the two.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
only compile tested...
---
drivers/gpu/drm/i915/i915_debugfs.c |5 -
drivers/gpu/drm/i915/i915_drv.h
Previously FBC disabling due to per-chip default was logged as being
disabled per module parameter. Distinguish between the two.
v2: Don't even squawk in the debug log if FBC is explicitly disabled (Chris
Wilson).
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915
On Thu, 14 Feb 2013, Ben Widawsky b...@bwidawsk.net wrote:
On Thu, Feb 14, 2013 at 10:42:11AM +0200, Jani Nikula wrote:
It is customary to end sysfs attributes with a newline.
As best I can tell, you are correct. Have you tested powertop with this
change? If not, can you?
Good point
On Wed, 20 Feb 2013, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Caching the PIPESTAT enable bits has been deemed pointless. Just
read them from the register itself.
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Ville Syrjälä
:
commit 2f4f649a69a9eb51f6e98130e19dd90a260a4145
Author: Jani Nikula jani.nik...@intel.com
Date: Mon Nov 12 14:33:44 2012 +0200
drm/i915: do not ignore eDP bpc settings from vbt
But that's not enough, since at least the panel on my ASUS Zenbook
Prime here is also unhappy if the bpc is too
On Tue, 26 Feb 2013, Rodrigo Vivi rodrigo.v...@gmail.com wrote:
Adding Enable and Disable PSR functionalities. This includes setting the
PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config,
enabling PSR in the sink via DPCD register and finally enabling PSR on
the host.
On Thu, 28 Feb 2013, James Courtier-Dutton james.dut...@gmail.com wrote:
Bisect done on tree:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
Worked on 3.7.
Broken on 3.8
Problem: Backlight not coming on after resume.
git finally bisected for my Samsung Serial 7
Hi James -
On Fri, 01 Mar 2013, James Courtier-Dutton james.dut...@gmail.com wrote:
James, try to revert that commit. Does it fix?
If so, you should check the output of intel_reg_dumper at broken and
working states.
Can someone point me to a datasheet that relates to this bit of code, so
On Fri, 01 Mar 2013, Jesse Barnes jbar...@virtuousgeek.org wrote:
Slightly different than other platforms.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_reg.h | 22
The more the merrier.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
lib/intel_reg.h |5 +
tools/intel_reg_dumper.c |5 +
2 files changed, 10 insertions(+)
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 99d97bb..db07064 100644
--- a/lib/intel_reg.h
+++ b/lib
On Sat, 02 Mar 2013, Jesse Barnes jbar...@virtuousgeek.org wrote:
From: Pallavi G pallav...@intel.com
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Update
vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll
On Sat, 02 Mar 2013, Jesse Barnes jbar...@virtuousgeek.org wrote:
The Gunit has a separate reg for this, so allocate some stolen space for
the power context and initialize the reg.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h|2 ++
On Sat, 02 Mar 2013, Jesse Barnes jbar...@virtuousgeek.org wrote:
From: Pallavi G pallav...@intel.com
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Update
vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll
On Sat, 02 Mar 2013, Jesse Barnes jbar...@virtuousgeek.org wrote:
From: Ben Widawsky b...@bwidawsk.net
Disable all Gunit clock gating and make set the allow force wake bit.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_gem.c |4
On Sat, 02 Mar 2013, Jesse Barnes jbar...@virtuousgeek.org wrote:
PPS register offsets have changed in Valleyview.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
I also had this as a quick fix to the backlight access; it's also
incomplete wrt the backlight registers.
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -121,6 +121,9 @@ static int is_backlight_combination_mode(struct drm_device
*dev)
{
struct
On Sat, 02 Mar 2013, Jesse Barnes jbar...@virtuousgeek.org wrote:
Fix up a couple of places where we messed with PCH bits on VLV.
I think there's at least a few more spots that need !IS_VALLEYVIEW():
---
} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
if
On the series, excluding the places I commented on,
Acked-by: Jani Nikula jani.nik...@intel.com
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On Tue, 05 Mar 2013, Chris Li l...@chrisli.org wrote:
On Mon, Mar 4, 2013 at 3:16 PM, Chris Li l...@chrisli.org wrote:
Two things to test:
- Can you please check whether any of the backlight drivers in
/sys/class/backlight does anything? You need to frob the brightness
file. Please also list
Even if power power is good for grepping.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5479363..be43f71 100644
on opregion brightness changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_panel.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index a3730e0..725d726 100644
On Wed, 13 Mar 2013, Ben Widawsky b...@bwidawsk.net wrote:
Interrupts, clock gating, and gmbus are all within the, this will hang
the CPU range when we have PCH_NOP.
There is a bit of a hack in init clock gating. We want to do most of the
block gating, but the part we skip will hang the
On Thu, 14 Mar 2013, Chris Li l...@chrisli.org wrote:
Hi, I attach the two demsg and with and without the bad commit
on the intel nightly branch. Without the bad commit it actually works.
However, on the tip of intel nightly. the moeset work around does not work
there any more.
Hi Chris,
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+ } else
+ final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
I've been assimilated, I dislike not having braces in all branches if
one branch requires them... but that's bikeshedding. On the stuff that
matters,
Reviewed-by: Jani Nikula jani.nik...@intel.com
I think these should DTRT, but with backlight and BIOS you never seem to
know...
BR,
Jani.
Jani Nikula (5):
drm/i915: group backlight related stuff into a struct
drm/i915: protect backlight enable and level with spinlock
drm/i915: don't pretend we support ASLE ALS, PFIT, or PFMB
drm/i915
No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 11 +
drivers/gpu/drm/i915/intel_panel.c | 44 ++--
2 files changed, 29 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915
Backlight is fiddled both through backlight sysfs files and asle
interrupts. Protect the relevant data.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h|1 +
drivers/gpu/drm/i915/intel_panel.c | 16
2 files changed, 17 insertions
In theory, this should prevent the BIOS from requesting them from us, and
this should be the right thing.
In practice, this is not always the case, and might surprise the BIOS.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c |4 +---
1 file changed
In theory, the BIOS should not even request these from us now that we
aren't claiming we support these, but when it does anyway, don't pretend it
succeeded. It should be the right thing to do, but might confuse the BIOS.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915
With the previous work asle and gse interrupt handlers should now be
functionally the same. Drop the duplicated code.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |1 -
drivers/gpu/drm/i915/i915_irq.c |4 ++--
drivers/gpu/drm/i915
On Tue, 02 Apr 2013, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Extract the PIPECONF setup into i9xx_set_pipeconf(). This makes the
=Gen4/VLV code follow the same pattern as the Gen5+ codepaths.
Reviewed-by: Jani Nikula jani.nik...@intel.com
On Tue, 02 Apr 2013, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
VLV has the color range selection bit in the PIPECONF register.
Configure it appropriately.
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj
on VLV, but since we now have to use the PIPECONF color range bit for
DP, we might as well do the same for HDMI.
I don't have any additional information on this. The patch does what it
says above, so for that:
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Ville Syrjälä
On Fri, 05 Apr 2013, Ben Widawsky b...@bwidawsk.net wrote:
Only the very first switch doesn't take the path.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Fri, 05 Apr 2013, Ben Widawsky b...@bwidawsk.net wrote:
On Fri, Apr 05, 2013 at 10:09:58AM +0300, Jani Nikula wrote:
Same goes for the unlikely in patches 4/7. (Yes, patch_es_ 4/7 - there's
*two* patches 4/7 in the series! :o)
I don't see two, weird.
Hmm, it's not only my mail setup
Per the spec change.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
Untested.
---
drivers/gpu/drm/i915/intel_display.c |7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b884932..1dffaf7 100644
Workaround to avoid intermittent aux channel failures, per spec change.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
Untested.
---
drivers/gpu/drm/i915/intel_dp.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu
Workaround to avoid intermittent aux channel failures, per spec change.
v2: Don't mess with cpu dp aux divider (Paulo Zanoni)
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
Untested.
---
drivers/gpu/drm/i915/intel_dp.c |8 ++--
1 file changed, 6 insertions(+), 2 deletions
cleanup.
A small wrinkle is the introduced asymmetry in backlight
setup/cleanup. This could be solved by adding refcounting, but it seems
overkill considering that there should only ever be one backlight device.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=55701
Signed-off-by: Jani Nikula
Hi Egbert -
Up front, I haven't been following this series or read any of the
previous review comments. Please bear with me, and feel free to direct
me to earlier comments if I'm in contradiction.
On Tue, 09 Apr 2013, Egbert Eich e...@freedesktop.org wrote:
From: Egbert Eich e...@suse.de
Add
this
connector is hotplug capable.
On init/reset we make sure the polled state of the connectors
is (re)set to the default value, the HPD interrupts are marked
enabled.
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Egbert Eich e...@suse.de
---
drivers/gpu/drm/i915/i915_irq.c | 13
On Tue, 09 Apr 2013, Egbert Eich e...@freedesktop.org wrote:
From: Egbert Eich e...@suse.de
To disable previously enabled HPD IRQs we need to reset them and
set the enabled ones individually.
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Egbert Eich e...@suse.de
On Tue, 09 Apr 2013, Egbert Eich e...@freedesktop.org wrote:
From: Egbert Eich e...@suse.de
This patch disables hotplug interrupts if an 'interrupt storm'
has been detected.
Noise on the interrupt line renders the hotplug interrupt useless:
each hotplug event causes the devices to be
On Tue, 09 Apr 2013, Egbert Eich e...@freedesktop.org wrote:
From: Egbert Eich e...@suse.de
We disable hoptplug detection when we encounter a hotplug event
storm. Still hotplug detection is required on some outputs (like
Display Port). The interrupt storm may be only temporary (on certain
On Tue, 09 Apr 2013, Egbert Eich e...@freedesktop.org wrote:
From: Egbert Eich e...@suse.de
This way it is possible to limit 're'-detect() of displays to connectors
which have received an HPD event.
I'd like you to be more explicit that this patch doesn't in fact add
such stuff in itself.
for someone(tm) to do this.
Apart from the bikesheds below,
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Egbert Eich e...@suse.de
---
drivers/gpu/drm/i915/i915_irq.c | 37 +++--
1 file changed, 31 insertions(+), 6 deletions(-)
diff --git
the system load.
Thus disable the hotplug interrupts and fall back to periodic
device polling.
v2: Fixed cleanup typo.
v3: Fixed format issues, clarified a variable name,
changed pr_warn() to DRM_INFO() as suggested by
Jani Nikula jani.nik...@linux.intel.com.
Signed-off-by: Egbert Eich e
loop start value,
Removed superfluous test for Ivybridge and Haswell,
Restructured loop to avoid deep nesting (all suggested by Ville Syrjälä)
v4: Fixed two bugs pointed out by Jani Nikula.
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Egbert Eich e...@suse.de
, removed some noisy debug
logging as suggested by Jani Nikula.
Okay, I'm not generally enthusiastic about adding #if 0 stuff. If we're
going to remove that later anyway, we might just as well add the noisy
debug print and remove *that* later. I'll just dodge this and let Daniel
decide. Both versions
On Thu, 11 Apr 2013, Egbert Eich e...@suse.de wrote:
Instead of calling into the DRM helper layer to poll all connectors for
changes in connected displays probe only those connectors which have
received a hotplug event.
Signed-off-by: Egbert Eich e...@suse.de
Reviewed-by: Jani Nikula
On Thu, 11 Apr 2013, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Thu, Apr 11, 2013 at 04:29:10PM +0200, Daniel Vetter wrote:
We can only enable the pfit if the pipe. Ensure that this is obied
^
obeyed or something?
cleanup.
A small wrinkle is the introduced asymmetry in backlight
setup/cleanup. This could be solved by adding refcounting, but it seems
overkill considering that there should only ever be one backlight device.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=55701
Signed-off-by: Jani Nikula
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_panel.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index 5d3e9d7..0362f5c 100644
--- a/drivers/gpu/drm/i915
Patches 1-2 are for locking, 3-4 are related only by being backlight fixes.
I haven't tested these much...
BR,
Jani.
Jani Nikula (4):
drm/i915: keep max backlight internal to intel_panel.c
drm/i915: protect backlight registers and data with a spinlock
drm/i915: ensure single
.
Clean up intel_panel_get_max_backlight() and usage internally.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h |4 +--
drivers/gpu/drm/i915/intel_opregion.c |4 +--
drivers/gpu/drm/i915/intel_panel.c| 51 +++--
3
than is strictly
necessary, including non-modeset case, for simplicity.
v2: Cover register access, save/restore, i915_read_blc_pwm_ctl() and code
paths leading there.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c |1 +
drivers/gpu/drm/i915
With the previous work asle and gse interrupt handlers should now be
functionally the same. Drop the duplicated code.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |1 -
drivers/gpu/drm/i915/i915_irq.c |4 ++--
drivers/gpu/drm/i915
There's still stuff to do on opregion cleanup, but here are some potentially
risky and/or controversial ones...
Jani Nikula (3):
drm/i915: don't pretend we support ASLE ALS, PFIT, or PFMB
drm/i915/opregion: don't pretend we did something when we didn't
drm/i915: drop code duplication
In theory, the BIOS should not even request these from us now that we
aren't claiming we support these, but when it does anyway, don't pretend it
succeeded. It should be the right thing to do, but might confuse the BIOS.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915
In theory, this should prevent the BIOS from requesting them from us, and
this should be the right thing.
In practice, this is not always the case, and might surprise the BIOS.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c |4 +---
1 file changed
On Fri, 12 Apr 2013, Jani Nikula jani.nik...@intel.com wrote:
Backlight cleanup in the eDP connector destroy callback caused the
backlight device to be removed on some systems that first initialized LVDS
and then attempted to initialize eDP. Prevent multiple backlight
initializations
On Mon, 15 Apr 2013, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Fri, Apr 12, 2013 at 03:18:37PM +0300, Jani Nikula wrote:
Backlight data and registers are fiddled through LVDS/eDP modeset
enable/disable hooks, backlight sysfs files, asle interrupts, and register
save/restore. Protect
addressed (by patches or
counter-arguments ;)
Reviewed-by: Jani Nikula jani.nik...@intel.com
}
ret = dev_priv-gtt.gtt_probe(dev, dev_priv-gtt.total,
--
1.8.2.1
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http
. We should
have seen those by now, so I don't mind.
Please drop the inline here too. Otherwise,
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +---
1 file changed
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 34 --
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 367b534..0b3b9ac
per paste. from pastebin.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0b3b9ac..2b348d3
On the series,
Reviewed-by: Jani Nikula jani.nik...@intel.com
On Mon, 22 Apr 2013, Kenneth Graunke kenn...@whitecape.org wrote:
Sandybridge/Ivybridge, Bay Trail, and Haswell all have slightly
different page table entry formats. Rather than polluting one function
with generation checks
-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c |9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 299208d..9f76f76
On Mon, 22 Apr 2013, Damien Lespiau damien.lesp...@intel.com wrote:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 31 +++
1 file changed, 7 insertions(+), 24 deletions
On Mon, 22 Apr 2013, Damien Lespiau damien.lesp...@intel.com wrote:
This way, when adding a device flag we don't have to manually maintain
that list.
\o/-by: and
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915
On Mon, 22 Apr 2013, Damien Lespiau damien.lesp...@intel.com wrote:
DEV_INFO_FOR_FLAG() now takes 2 parameters:
• A function to apply to the flag
• A separator
Oooh, fancy bullets. ;)
Tiny bikeshed, is leaving out #undefs for the temp macros intentional?
Reviewed-by: Jani Nikula jani.nik
that have bit
31 of FPGA_DBG able to signal unclaimed writes.
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 1 +
3
\
func(has_bsd_ring) sep \
func(has_blt_ring) sep \
- func(has_llc)
+ func(has_llc) sep \
+ func(has_ddi)
We could just decide to keep something last and insert new stuff before
that.
Reviewed-by: Jani Nikula jani.nik...@intel.com
#define DEFINE_FLAG(name) u8 name:1
I think this could be squashed together with the previous patch, but
either way,
Reviewed-by: Jani Nikula jani.nik...@intel.com
On Mon, 22 Apr 2013, Damien Lespiau damien.lesp...@intel.com wrote:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 2
On Tue, 23 Apr 2013, Jani Nikula jani.nik...@linux.intel.com wrote:
On Mon, 22 Apr 2013, Damien Lespiau damien.lesp...@intel.com wrote:
DEV_INFO_FOR_FLAG() now takes 2 parameters:
• A function to apply to the flag
• A separator
Oooh, fancy bullets. ;)
Tiny bikeshed, is leaving out
On Tue, 23 Apr 2013, Jesse Barnes jbar...@virtuousgeek.org wrote:
We need to hold the rps lock around punit access.
Reviewed-by: Jani Nikula jani.nik...@intel.com
And a semi-related question while at it... we will need punit access
also for non-rps stuff. Shall we just bundle them under
On Tue, 23 Apr 2013, Jesse Barnes jbar...@virtuousgeek.org wrote:
On VLV, the Punit doesn't automatically drop the GPU to it's minimum
voltage level when entering RC6, so we arm a timer to do it for us from
the RPS interrupt handler. It'll generally only fire when we go idle
(or if for some
On the series,
Reviewed-by: Jani Nikula jani.nik...@intel.com
On Tue, 23 Apr 2013, Jesse Barnes jbar...@virtuousgeek.org wrote:
On VLV, the Punit doesn't automatically drop the GPU to it's minimum
voltage level when entering RC6, so we arm a timer to do it for us from
the RPS interrupt
add a WARN_ON to ensure we obey that piece of ordering
constraint. Long term I want to lock down the setup/teardown code in a
similar way to how we painstakingly check modeset sequence constraints
already.
Cc: Jesse Barnes jbar...@virtuousgeek.org
Cc: Jani Nikula jani.nik...@intel.com
Signed
handling the hotplug work can re-arm the polling
handler. Spotted by Jani Nikula.
Reviewed-by: Jani Nikula jani.nik...@intel.com
Cc: Jesse Barnes jbar...@virtuousgeek.org
Cc: Jani Nikula jani.nik...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915
With the previous work asle and gse interrupt handlers should now be
functionally the same. Drop the duplicated code.
v2: Drop intel_opregion_gse_intr() also in the !CONFIG_ACPI path. (Damien)
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2
This was supposed to be in-reply-to [1] but I screwed up.
Jani.
[1] http://mid.gmane.org/20130424182351.gb3...@strange.amr.corp.intel.com
On Wed, 24 Apr 2013, Jani Nikula jani.nik...@intel.com wrote:
With the previous work asle and gse interrupt handlers should now be
functionally the same
The version at Daniel's fdi-dither branch (which is without the hack in
drm/i915: force bpp for eDP panels) is
Tested-by: Jani Nikula jani.nik...@intel.com
on VLV.
On Fri, 19 Apr 2013, Daniel Vetter daniel.vet...@ffwll.ch wrote:
Hi all,
This fixes all the bugs I've found in my various
v2: Make TRANSCODER_EDP handling more explicit. (Imre)
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h|4
drivers/gpu/drm/i915/intel_panel.c |7 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
Jani Nikula (6):
drm/i915: cleanup opregion technology enabled indicator defines
drm/i915: manage opregion asle driver readiness properly
drm/i915: untie opregion init and asle irq/pipestat enable
drm/i915: cleanup redundant checks from intel_enable_asle
drm/i915: cleanup opregion asle
Move near other defines, add TCHE in the name. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers
Only set ASLE driver readiness (ARDY) and technology enabled indicator
(TCHE) once per opregion init. There should be no need to do that at irq
postinstall time. Also clear driver readiness at fini.
While at it, add defines for driver readiness.
Signed-off-by: Jani Nikula jani.nik...@intel.com
Realize that intel_enable_asle() is never called on PCH-split platforms
or on VLV. Rip out the GSE irq enable for PCH-split platforms, which
also happens to be incorrect for IVB+.
This should not cause any functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm
Both intel_opregion_enable_asle() and intel_enable_asle() have shrunk
considerably. Merge them together into a static function in i915_irq.c,
and rename to better reflect the purpose and the related platforms.
No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers
Enable asle pipestat earlier in i915/i965 irq postinstall to not need
irq_lock in i915_enable_asle_pipestat().
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm
-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c |2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index 5b6d202..4e69799 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b
From: Chris Wilson ch...@chris-wilson.co.uk
This replaceable mainboard only has a VGA-out, yet it claims to also
have a connected LVDS header.
Reported-by: annndd...@gmail.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63860
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
dmi_check_system() matches the D510MO no LVDS quirk for D510MOV
too. Reverse quirk the quirk.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_lvds.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
Warn on missing locking in pipestat enable/disable, and fix calls that
would trigger this.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
Daniel, is this more to your liking?
I don't have a machine handy to actually test this right now...
---
drivers/gpu/drm/i915/i915_irq.c | 21
On Fri, 03 May 2013, Imre Deak imre.d...@intel.com wrote:
Currently the driver's assumed behavior for a modeset with an attached
FB is that the corresponding connector will be switched to DPMS ON mode
if it happened to be in DPMS OFF (or another power save mode). This
wasn't enforced though if
On Fri, 03 May 2013, Daniel Vetter dan...@ffwll.ch wrote:
On Fri, May 03, 2013 at 11:17:42AM +0200, dl...@gmx.de wrote:
From: Jan-Simon Möller dl...@gmx.de
Description:
intel_gmbus_is_forced_bit is no extern as its body is right below.
Likewise for intel_gmbus_is_port_valid.
This fixes a
On Tue, 30 Apr 2013, Daniel Vetter daniel.vet...@ffwll.ch wrote:
We need to track this correctly. While at it shovel the boolean
to track whether the sdvo is in tv mode or not into pipe_config.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36997
Bug scrubbing, should this be:
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