Checking with hweight8 if plane configuration had
changed seems to be wrong as different plane configs
can result in a same hamming weight.
So lets check the bitmask itself.
v2: Fixed "from" field which got corrupted for some weird reason
Reviewed-by: Manasi Navare
Signed-off-by:
min_cdclk hook, instead of using
a condition(Manasi Navare)
v12: - Fixed rebase conflict
v13: - Added spaces after declarations to make checkpatch happy.
Signed-off-by: Stanislav Lisovskiy
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_bw.c
min_cdclk hook, instead of using
a condition(Manasi Navare)
v12: - Fixed rebase conflict
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 119 ++-
drivers/gpu/drm/i915/display/intel_bw.h | 10 ++
drivers/gpu/drm/i915/display/inte
Removed duplicate include and fixed comment > 80 chars.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c| 43 --
drivers/gpu/drm/i915/display/intel_bw.h| 2 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i
Removed duplicate include and fixed comment > 80 chars.
v2: Added newline after system include and between functions
Reviewed-by: Chris Wilson
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c| 44 --
drivers/gpu/drm/i915/display/intel_b
retraining
when needed.
There were some issues, when we had several problems with dp mst
and at the same time the log was floode by messages about
"channel eq not ok, need retraining" however the actual training
seems to be never done.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gp
the issues in test, however
not clear - anyway marking this as fixing the
"Adjust CDCLK accordingly to our DBuf bw needs".
Signed-off-by: Stanislav Lisovskiy
Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs")
---
drivers/gpu/drm/i915/display/
the issues in test, however
not clear - anyway marking this as fixing the
"Adjust CDCLK accordingly to our DBuf bw needs".
v2: - s/pipe/crtc->pipe/
- save a bit of instructions by
skipping inactive pipes, without
getting 0 DBuf slice mask for it.
Signed-off-by: Stanis
We still need "Bump up CDCLK" workaround otherwise getting
underruns - however currently it blocks 8K as CDCLK = Pixel rate,
in 8K case would require CDCLK to be around 1 Ghz which is not
possible.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cd
le Syrjälä)
- Use type specific min_t, max_t(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/int
This reverts commit 82ea174dc5425d4e85e25d0c4ba961a2e494392a.
Signed-off-by: Stanislav Lisovskiy
Fixes: cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs")
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 12
1 file changed, 12 insertions(+)
Removed excessive parenthesis and placed && on
previous line in DBUF state checker.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/in
mask/unmask only those which
are returned, trying to manipulate those beyond causes a
failure from PCode. So switched back to generating mask
from 1 - num_qgv_points, where num_qgv_points is the actual
amount of points, advertised by PCode.
Signed-off-by: Stanislav Lisovskiy
Cc
GV point, based on the current video
mode requirements.
Bspec: 64631, 53998
Signed-off-by: Stanislav Lisovskiy
Cc: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 100 +++-
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915/i915_reg.h | 3
issues.
Solution: check also mbus_join, in addition to slices mask.
Cc: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Jani Nikula
Signed-off-by: Gwan-gyeong Mun
Cc: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++---
drivers/gpu/drm/i915/i915_pci.c| 1 +
drivers/gpu/drm/i915/i915_reg.h| 2
issues.
Solution: check also mbus_join, in addition to slices mask.
Cc: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
From: Gwan-gyeong Mun
CDCLK crawl feature allows to change CDCLK frequency
without disabling the actual PLL and doesn't require
a full modeset.
Cc: Mika Kahola
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Jani Nikula
Signed-off-by: Gwan-gyeong Mun
Cc: Stanislav Lisovskiy
---
drivers
According to BSpec there is now also a code 0x02,
which corresponds to QGV point being rejected,
this code so lets extend mask to check this.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
to 0xf, as we have now
3:2 bits for PSF GV points(Matt Roper)
- Replaced val2 with NULL from PCode request, since its not being
used(Matt Roper)
- Replaced %d to 0x%x for better readability(thanks for spotting)
Signed-off-by: Stanislav Lisovskiy
Cc: Matt Roper
---
drivers/gpu
to 0xf, as we have now
3:2 bits for PSF GV points(Matt Roper)
- Replaced val2 with NULL from PCode request, since its not being
used(Matt Roper)
- Replaced %d to 0x%x for better readability(thanks for spotting)
Signed-off-by: Stanislav Lisovskiy
Cc: Matt Roper
---
drivers/gpu
and commit message(Matt)
v3: - s/adl_/adls_/ - Matt Roper
- Do not return error but just zero qi->num_psf_points,
if we can't get PSF GV points(Matt Roper)
- s/GEN13_/ADLS_/ - Matt Roper
Signed-off-by: Stanislav Lisovskiy
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/disp
GV point, based on the current video
mode requirements.
Bspec: 64631, 53998
Signed-off-by: Stanislav Lisovskiy
Cc: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 100 +++-
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915/i915_reg.h | 3
TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.
Cc: Matt Roper
Cc: Maarten Lankhorst
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Matt Roper
Signed-off-by: Juha-Pekka Heikkilä
Lankhorst
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Matt Roper
Signed-off-by: Juha-Pekka Heikkilä
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++
drivers/gpu/drm/i915/display/intel_fb.c | 12 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
.../drm/i915
/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
- Removed unneeded fencing code
Cc: Imre Deak
Cc: Matt Roper
Cc: Maarten Lankhorst
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Matt Roper
Signed-off-by: Juha-Pekka Heikkilä
---
drivers/gpu/drm/i915/display/intel_display.c | 2
Bug in the register unit which results in WM1 register
used when only WM0 is enabled on cursor.
Software workaround is when only WM0 enabled on cursor,
copy contents of CUR_WM_0[30:0] (exclude the enable bit)
into CUR_WM_1[30:0].
HSDES: 14012656716
Signed-off-by: Stanislav Lisovskiy
e Tile F mentionings
- Moved has_4tile from adlp to DG2(Ramalingam)
- Check specifically for DG2, but not the Display13(Imre)
Cc: Imre Deak
Cc: Matt Roper
Cc: Maarten Lankhorst
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Matt Roper
Signed-off-by: Juha-Pekka Heikkilä
---
drivers/
Tile4 patch still needs an ack from userspace,
IGT tests and some essential fixes, related to
new .plane_caps attribute being added.
This reverts commit 3c542cfa8266e3364938d055b3d548b7bed7f08e.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 1
description for Tile 4 in drm uapi
header(Nanley Chery)
Cc: Matt Roper
Cc: Maarten Lankhorst
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Matt Roper
Signed-off-by: Juha-Pekka Heikkilä
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_fb.c
brackets (Ville Syrjälä)
HSDES: 14012656716
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
re Deak)
- Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
(Imre Deak)
Reviewed-by: Imre Deak
Cc: Imre Deak
Cc: Matt Roper
Cc: Maarten Lankhorst
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Matt Roper
Signed-off-by: Juha-Pekka Heikkilä
---
drivers/gpu/drm/i915/display/i
re Deak)
- Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
(Imre Deak)
v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
- Removed redundant newline(Imre Deak)
Reviewed-by: Imre Deak
Cc: Imre Deak
Cc: Matt Roper
Cc: Maarten Lankhorst
Signed-off-by: Stanislav Lisovskiy
Signe
c: Maarten Lankhorst
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Matt Roper
Signed-off-by: Juha-Pekka Heikkilä
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_fb.c | 11 ++
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
of 64B x 8 rows.
Signed-off-by: Stanislav Lisovskiy
---
include/uapi/drm/drm_fourcc.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 7f652c96845b..a146c6df1066 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b
Do mapping using CONTIGUOUS flag - otherwise
i915_gem_object_is_contiguous warn is triggered.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers
description for Tile 4 in drm uapi
header(Nanley Chery)
v4: - Extracted drm_fourcc changes to separate patch(Nanley Chery)
Cc: Matt Roper
Cc: Maarten Lankhorst
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Matt Roper
Signed-off-by: Juha-Pekka Heikkilä
---
drivers/gpu/drm/i915
This optimization allows to achieve higher perfomance
during async flips.
For the first async flip we have to still temporarily
switch to sync flip, in order to reprogram plane
watermarks, so this requires taking into account
old plane state's do_async_flip flag.
Signed-off-by: Stanislav
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b
There might be various logical contructs when we might want
to enable async flip, so lets calculate those and set this
flag, so that there is no need in long conditions in other
places.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
drivers/gpu
Sometimes we might need to change the way we calculate
watermarks, based on which particular plane it is calculated
for. Thus it would be convenient to pass plane_id to those
functions.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 16 ++--
1 file changed
Sometimes we might need to change the way we calculate
watermarks, based on which particular plane it is calculated
for. Thus it would be convenient to pass plane struct to those
functions.
v2: Pass plane instead of plane_id
Signed-off-by: Stanislav Lisovskiy
---
.../gpu/drm/i915/display
There might be various logical contructs when we might want
to enable async flip, so lets calculate those and set this
flag, so that there is no need in long conditions in other
places.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
drivers/gpu
new_plane_state->do_async_flip
check from needs_async_flip_wm_override condition
(Ville Syrjälä)
- Extract dg2_async_flip_optimization to separate
function(Ville Syrjälä)
- Check for plane->async_flip instead of plane_id
(Ville Syrjälä)
Signed-off-by: Stanislav Lis
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
Signed-off-by: Stanislav
it affects
display buffer bandwidth requirements.
v2: - Removed excessive debugs(Jani Nikula)
- Switched to drm_dbg_kms(Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 56 ++--
1 file changed, 53 insertions(+), 3 deletions(-)
diff
Using i915_gem_object_pin_map_unlocked instead of
i915_gem_object_lmem_io_map, would eliminate the need
of using I915_BO_ALLOC_CONTIGUOUS, when calling
i915_vma_pin_iomap, because it supports non-contiguous
allocation as well.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915
it affects
display buffer bandwidth requirements.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 63 +++-
1 file changed, 60 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display
.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index fda8b701..095b79950788 100644
--- a/drivers/gpu/drm
.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index fda8b701..095b79950788 100644
--- a/drivers/gpu/drm
Cannot use PIN_MAPPABLE pin on MTL because there's no mappable window.
Change dpt allocation as per suggestion from Chris.
v2: - Added forgotten/dropped include
Signed-off-by: Stanslav Lisovskiy
Signed-off-by: Juha-Pekka Heikkilä
Cc: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_dpt.c
] i915 :00:02.0: [drm:__snb_pcode_rw [i915]] Returning EAGAIN
retry 4
[ 22.319158] i915 :00:02.0: [drm:__snb_pcode_rw [i915]] Returning EAGAIN
retry 5
[ 22.319224] i915 :00:02.0: [drm:__snb_pcode_rw [i915]] Returning EAGAIN
retry 6
Signed-off-by: Stanislav Lisovskiy
---
drivers
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/dp/drm_dp.c| 25 +
include/drm/dp
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (2):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Add DSC support to MST path
drivers/gpu/drm/dp/drm_dp.c | 25
drivers/gpu/drm/i915/display/intel_dp.c | 75
check(Imre Deak)
v6: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
Acked-by: Imre Deak
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 75 +-
drivers
: - Added comment(Jose Souza)
- Fixed 15% calculation(Jose Souza)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (2):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Add DSC support to MST path
drivers/gpu/drm/dp/drm_dp.c | 25
drivers/gpu/drm/i915/display/intel_dp.c | 75
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/dp/drm_dp.c| 25 +
include/drm/dp
-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 75 +-
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 143
3 files changed, 191 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm
description for Tile 4 in drm uapi
header(Nanley Chery)
v4: - Extracted drm_fourcc changes to separate patch(Nanley Chery)
Reviewed-by: Imre Deak
Cc: Matt Roper
Cc: Maarten Lankhorst
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Matt Roper
Signed-off-by: Juha-Pekka Heikkilä
Tile4 in bspec format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY.
Stanislav Lisovskiy (2):
drm/i915: Introduce new Tile 4 format
drm/i915/dg2: Tile 4 plane format support
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display
of 64B x 8 rows.
Reviewed-by: Imre Deak
Acked-by: Nanley Chery
Signed-off-by: Stanislav Lisovskiy
---
include/uapi/drm/drm_fourcc.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index fc0c1454d275..b73fe6797fc3
Tile4 in bspec format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY.
Stanislav Lisovskiy (2):
drm/i915: Introduce new Tile 4 format
drm/i915/dg2: Tile 4 plane format support
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
Signed-off-by: Stanislav
new_plane_state->do_async_flip
check from needs_async_flip_wm_override condition
(Ville Syrjälä)
- Extract dg2_async_flip_optimization to separate
function(Ville Syrjälä)
- Check for plane->async_flip instead of plane_id
(Ville Syrjälä)
Signed-off-by: Stanislav Lis
Limitting the WM levels to 0 for DG2 during async flips,
allows to slightly increase the perfomance, as recommended
by HW team.
Stanislav Lisovskiy (4):
drm/i915: Pass plane to watermark calculation functions
drm/i915: Introduce do_async_flip flag to intel_plane_state
drm/i915: Use wm0 only
Sometimes we might need to change the way we calculate
watermarks, based on which particular plane it is calculated
for. Thus it would be convenient to pass plane struct to those
functions.
v2: Pass plane instead of plane_id
Signed-off-by: Stanislav Lisovskiy
---
.../gpu/drm/i915/display
-initialized, but set
explicitly, so that the logic is clear as well.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
3 files
-off-by: Stanislav Lisovskiy
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 20 +--
3 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915
-initialized, but set
explicitly, so that the logic is clear as well.
v3: - Clear do_async_flip in intel_plane_duplicate_state(Ville Syrjälä)
- Check with do_async_flip also when calling
intel_crtc_{enable,disable}_flip_done(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu
Rename "needs_async_flip_wm_override" to
"intel_plane_do_async_flip" and move all the required
checks there (Ville Syrjälä)
- Rename "dg2_async_flip_optimization" to
"use_minimal_wm0_only" (Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
dri
dg2_need_min_ddb to need_min_ddb thus making
it more universal.
- Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
- Use rate = 0 instead of just setting extra = 0, thus
letting other planes to use extra ddb and avoiding WARN
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
Limitting the WM levels to 0 for DG2 during async flips,
allows to slightly increase the performance, as recommended
by HW team.
Stanislav Lisovskiy (4):
drm/i915: Pass plane to watermark calculation functions
drm/i915: Introduce do_async_flip flag to intel_plane_state
drm/i915: Use wm0
Limitting the WM levels to 0 for DG2 during async flips,
allows to slightly increase the performance, as recommended
by HW team.
Stanislav Lisovskiy (4):
drm/i915: Pass plane to watermark calculation functions
drm/i915: Introduce do_async_flip flag to intel_plane_state
drm/i915: Use wm0
intel_crtc_get_plane static again(Ville Syrjälä)
- s/cursor_plane/plane(Ville Syrjälä)
- Pass plane to skl_compute_wm_* instead of plane_id(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
.../gpu/drm/i915/display/intel_atomic_plane.h | 1 +
drivers/gpu/drm/i915/intel_pm.c
-initialized, but set
explicitly, so that the logic is clear as well.
v3: - Clear do_async_flip in intel_plane_duplicate_state(Ville Syrjälä)
- Check with do_async_flip also when calling
intel_crtc_{enable,disable}_flip_done(Ville Syrjälä)
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav
/use/ to match
the wm0 counterpart(Ville Syrjälä)
- Added plane->async_flip check to use_min_ddb(now
passing plane as a parameter to do that)(Ville Syrjälä)
- Account for use_min_ddb also when calculating total data rate
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovs
p
argument list(Ville Syrjälä)
- Use plane->base.dev to grab i915 pointer in
intel_plane_do_async_flip(Ville Syrjälä)
- Remove const modifier from plane parameter in
use_minimal_wm0_only(Ville Syrjälä)
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
Use for_each_intel_plane_on_crtc instead of for_each_intel_plane_id
to get plane->async_flip check and account for all planes(Ville Syrjälä)
- Fix line wrapping(Ville Syrjälä)
- Set plane data rate conditionally, avoiding on redundant assignment
(Ville Syrjälä)
Signed-off-by: Stanislav Lis
call site(Ville Syrjälä)
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 24 +++-
drivers/gpu/drm/i915/intel_pm.c | 13 ++-
2 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/driver
(Ville Syrjälä)
- Handle use_min_ddb case in skl_plane_relative_data_rate instead of
icl_get_total_relative_data_rate(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/dr
PCode,
rather than to find out that we had a time out, which is anyway
quite obvious, if the function fails.
v2: Make it status ? status : ret(thanks Vinod for the hint)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pcode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
PCode,
rather than to find out that we had a time out, which is anyway
quite obvious, if the function fails.
v2: Make it status ? status : ret(thanks Vinod for the hint)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pcode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
anymore.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 71 ++---
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
2 files changed, 67 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
---
include/drm/dp
-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 75 +-
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 143
3 files changed, 191 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (2):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Add DSC support to MST path
drivers/gpu/drm/i915/display/intel_dp.c | 75 +-
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers
the DISPLAY_VER.
Signed-off-by: Stanislav Lisovskiy
---
.../drm/i915/display/intel_display_debugfs.c | 71 +++
.../drm/i915/display/intel_display_types.h| 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 6 +-
3 files changed, 78 insertions(+), 1 deletion(-)
diff
the DISPLAY_VER.
v3: - Switch to intel_connector from drm_connector(Jani Nikula)
- Remove redundant modeset lock(Jani Nikula)
- Use kstrtobool_from_user for boolean value(Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
---
.../drm/i915/display/intel_display_debugfs.c | 72
the DISPLAY_VER.
v3: - Switch to intel_connector from drm_connector(Jani Nikula)
- Remove redundant modeset lock(Jani Nikula)
- Use kstrtobool_from_user for boolean value(Jani Nikula)
v4: - Apply the changes to proper function(Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c| 7 ---
drivers/gpu/drm/i915/display/intel_bw.h| 1 +
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 13 +
3 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu
For validation purposes, it might be useful to be able to
force Bigjoiner mode, even if current dotclock/resolution
do not require that.
Lets add such to option to debugfs.
Signed-off-by: Stanislav Lisovskiy
---
.../drm/i915/display/intel_display_debugfs.c | 71 +++
.../drm
MBUS join state needed to be changed, preventing
fastset to be done in certain cases.
This patch series attempts to fix that.
Stanislav Lisovskiy (2):
drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly
drm/i915: Implement vblank synchronized MBUS join changes
drivers/gpu/drm
display
MBUS registers should be updated with correspondent values _before_
Dbuf reallocation happens, however if we are switching from single
display to multiple then it should happen _after_ DDB reallocation(i.e
plane programming).
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display
and dbox programming into to pre/post plane update parts,
how it should be done according to BSpec.
Signed-off-by: Stanislav Lisovskiy
Tested-by: Khaled Almahallawy
---
drivers/gpu/drm/i915/display/intel_display.c | 2 --
drivers/gpu/drm/i915/display/skl_watermark.c | 36 +++-
Couple of crucial fixes for skl_pcode_request function.
1) Correctly handle the error and do retires until timeout
2) Return PCode request status, when failure happens
Stanislav Lisovskiy (2):
drm/i915: Fix skl_pcode_try_request function
drm/i915: Swap ret and status returned from
-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pcode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pcode.c
b/drivers/gpu/drm/i915/intel_pcode.c
index 391a37492ce5..fb6c43e8a02f 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu
PCode,
rather than to find out that we had a time out, which is anyway
quite obvious, if the function fails.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pcode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pcode.c
b/drivers/gpu
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (2):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Add DSC support to MST path
drivers/gpu/drm/dp/drm_dp.c | 25
drivers/gpu/drm/i915/display/intel_dp.c | 138
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/dp/drm_dp.c| 25 +
include/drm/dp/drm_dp_helper.h | 11 ++-
2 files
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