purposes(Manasi Navare)
- Properly process ret == EDEADLK, thus fixing the
regression caused by WARN triggered with modeset_lock.
v5: - Removed redundant check(Imre Deak)
Acked-by: Imre Deak
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 138
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/dp/drm_dp.c| 25 +
include/drm/dp/drm_dp_helper.h | 11 ++-
2 files
Otherwise we seem to get FIFO underruns. It is being disabled
anyway, so kind of logical to write those as zeroes, even if
disabling is temporary.
Signed-off-by: Stanislav Lisovskiy
---
.../drm/i915/display/skl_universal_plane.c| 2 +-
drivers/gpu/drm/i915/intel_pm.c | 46
We seem to need this W/A same way as for TGL, in order
to fix some of the underruns, which we currently have and
those not related to PSR.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
We set it to be equal to pixel rate here, just same as
we have already for TGL, as that seems to be currently
the only solution to fix underruns, not related to PSR.
Stanislav Lisovskiy (1):
drm/i915/dg2: Bump up CDCLK for DG2
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
1 file
We seem to cause FIFO underruns by doing that.
Also it doesn't make sense.
Stanislav Lisovskiy (1):
drm/i915: Do not enable PSR2/selective fetch if there are no planes
drivers/gpu/drm/i915/display/intel_psr.c | 6 ++
1 file changed, 6 insertions(+)
--
2.24.1.485.gad05a3d8e5
We seem to enable PSR2 and selective fetch even if there are no active
planes. That seems to causes FIFO underruns at least for ADLP.
Those are gone if we don't do that. Just adding simple check
in intel_psr2_sel_fetch_config_valid seems to do the trick.
Signed-off-by: Stanislav Lisovskiy
configuration, which isn't the
case here.
So added that drm_dp_mst_check here, so that we can make sure
that try all the bpps before we fail.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff
We are using almost same code to loop through bpps while calling
drm_dp_atomic_find_vcpi_slots - lets remove this duplication by
introducing a new function intel_dp_mst_find_vcpi_slots_for_bpp
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 88
We are using almost same code to loop through bpps while calling
drm_dp_atomic_find_vcpi_slots - lets remove this duplication by
introducing a new function intel_dp_mst_find_vcpi_slots_for_bpp
v2: Fix pbn_div calculation - shouldn't matter if its DSC or not.
Signed-off-by: Stanislav Lisovskiy
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
ion in intel_dp_dsc_compute_config
(don't remember when I lost it)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 73 -
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 157
3 fi
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (4):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Fix intel_dp_mst_compute_link_config
drm/i915: Add DSC support to MST path
drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate
ion in intel_dp_dsc_compute_config
(don't remember when I lost it)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 73 -
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 157
3 fi
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
---
include/drm/display/drm_dp.h
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (2):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Add DSC support to MST path
drivers/gpu/drm/i915/display/intel_dp.c | 73 -
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers
We would be using almost same code to loop through bpps while calling
drm_dp_atomic_find_vcpi_slots - lets remove this duplication by
introducing a new function intel_dp_mst_find_vcpi_slots_for_bpp
v2: Fix pbn_div calculation - shouldn't matter if its DSC or not.
Signed-off-by: Stanislav
ion in intel_dp_dsc_compute_config
(don't remember when I lost it)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 73 +--
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 136
3 fi
configuration, which isn't the
case here.
So added that drm_dp_mst_check here, so that we can make sure
that try all the bpps before we fail.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++--
1 file changed, 14
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (4):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Fix intel_dp_mst_compute_link_config
drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate
function
drm/i915: Add DSC support to MST
Lets start to use REG_BIT* macros, instead of (x << 0) like expressions.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/i915_reg.h | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/dr
drm_dp_atomic_find_vcpi_slots no longer exists and needs
to be used as drm_dp_atomic_find_time_slots.
Also rename the function itself.
Signed-off-by: Stanislav Lisovskiy
Fixes: 7ae5ab441402 ("Extract drm_dp_atomic_find_vcpi_slots cycle to separate
function")
---
drivers/gpu/drm/i9
configuration, which isn't the
case here.
So added that drm_dp_mst_check here, so that we can make sure
that try all the bpps before we fail.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff
ion in intel_dp_dsc_compute_config
(don't remember when I lost it)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 73 -
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 157
3 fi
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (4):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Fix intel_dp_mst_compute_link_config
drm/i915: Add DSC support to MST path
drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate
We are using almost same code to loop through bpps while calling
drm_dp_atomic_find_vcpi_slots - lets remove this duplication by
introducing a new function intel_dp_mst_find_vcpi_slots_for_bpp
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 85
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 73 +---
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 125
3 files changed, 173 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i
configuration, which isn't the
case here.
So added that drm_dp_mst_check here, so that we can make sure
that try all the bpps before we fail.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++--
1 file changed, 14
, constant_n no longer needed.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 48 +++--
1 file changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (4):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Fix intel_dp_mst_compute_link_config
drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate
function
drm/i915: Add DSC support to MST
off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 73 +--
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 127
3 files changed, 175 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i
configuration, which isn't the
case here.
So added that drm_dp_mst_check here, so that we can make sure
that try all the bpps before we fail.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++--
1 file changed, 14
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 52 +++--
1 file changed, 39 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 24d6a287a6e3
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (4):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Fix intel_dp_mst_compute_link_config
drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate
function
drm/i915: Add DSC support to MST
: - Rebased
- Added a debug to see that we at least try reserving
VCPI slots using DSC, because currently its not visible
from the logs, thus making debugging more tricky.
- Moved timeslots to numerator, where it should be.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
---
include/drm/display/drm_dp.h
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (2):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Add DSC support to MST path
drivers/gpu/drm/i915/display/intel_dp.c | 76 +-
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers
config computation, because we need to know already
by this moment if uncompressed amount of VCPI slots
needed can fit, otherwise we need to use DSC.
(thanks to Vinod Govindapillai for pointing this out)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
---
include/drm/display/drm_dp.h
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (2):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Add DSC support to MST path
drivers/gpu/drm/i915/display/intel_dp.c | 76 --
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers
- lets use -1
in order to make sure all the next gens support it by
default(Juha-Pekka Heikkila)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 8b0e4defa3f1..1f1f7f5f6501 100644
--- a/drivers
commit subject(Rodrigo Vivi)
- Fixed the error message if check fails(Rodrigo Vivi)
Signed-off-by: Stanislav Lisovskiy
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm
/intel/-/issues/6860
Fixes: 52f14682ac4d ("drm/i915: Bpp/timeslot calculation fixes for DP MST DSC")
Reviewed-by: Manasi Navare
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/d
According to spec, we should check if output_bpp * pixel_rate is less
than DDI clock * 72, if UHBR is used.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b
We now accept timeslots param exactly how the variable
sounds: amount of timeslots, but not ratio timeslots/64.
So for SST case(when we have all timeslots for use), it
should be 64, but not 1.
This caused some issues in the tests.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915
There was a specific SW workaround requested, which should prevent
some watermark issues happening, which requires copying highest
enabled wm level to those disabled wm levels(bit 31 is of course
still needs to be cleared).
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display
We have some Tile4 tests now skipping, which were
supposed to be working. So lets make them work, by
adding display_ver 14 as supported.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_fb.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
It was reported that we might get a hung and loss of register access in
some cases when CDCLK PLL is disabled and then enabled, while squashing
is enabled.
As a workaround it was proposed by HW team that SW should disable squashing
when CDCLK PLL is being reenabled.
Signed-off-by: Stanislav
and enable squashing later, if needed.
Stanislav Lisovskiy (1):
drm/i915: Implement workaround for CDCLK PLL disable/enable
drivers/gpu/drm/i915/display/intel_cdclk.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
--
2.37.3
multiple blank lines
v3: Rename intel_dp_dsc_nearest_vesa_bpp to intel_dp_dsc_nearest_valid_bpp
to reflect its meaning more properly.
(Manasi Navare)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 50 +
drivers/gpu/drm/i915/display
to intel_dp_dsc_nearest_valid_bpp
(Manasi Navare)
Reviewed-by: Manasi Navare
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 69 ++---
drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 69 +
3 files
-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e3e7c305fece..b95051fed23d 100644
--- a/drivers/gpu/drm
According to BSpec UHBR might hit hw limitation which must be checked.
So this series adds first some generic checker function, which might
be used to add this or similar checks in future, then we introduce
that particular UHBR check.
Stanislav Lisovskiy (2):
drm/i915: Add generic constraint
There are might be multiple contraints which we need to check while determining
if we can use desired compressed bpp, so might be good idea to add a special
helper, so that we don't overcomplicate the main bpp calculation function.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915
It was reported that we might get a hung and loss of register access in
some cases when CDCLK PLL is disabled and then enabled, while squashing
is enabled.
As a workaround it was proposed by HW team that SW should disable squashing
when CDCLK PLL is being reenabled.
Signed-off-by: Stanislav
(Rodrigo Vivi)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7e16b655c833
align those with
VESA bpps and only then calculate required timeslots amount.
Some MST hubs started to work only after third change was made.
v2: Make kernel test robot happy(claimed there was unitialzed use,
while there is none)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915
multiple blank lines
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 50 +
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 -
3 files changed, 32 insertions(+), 20 deletions(-)
diff
off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 57 +
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 125
3 files changed, 173 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i
align those with
VESA bpps and only then calculate required timeslots amount.
Some MST hubs started to work only after third change was made.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 52 ++---
drivers/gpu/drm/i915/display/intel_dp.h | 3
-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 51 -
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
2 files changed, 33 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
configuration, which isn't the
case here.
So added that drm_dp_mst_check here, so that we can make sure
that try all the bpps before we fail.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++--
1 file changed, 14
, constant_n no longer needed.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 48 +++--
1 file changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (6):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Fix intel_dp_mst_compute_link_config
drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate
function
drm/i915: Add DSC support to MST
There are might be multiple contraints which we need to check while determining
if we can use desired compressed bpp, so might be good idea to add a special
helper, so that we don't overcomplicate the main bpp calculation function.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915
According to BSpec UHBR might hit hw limitation which must be checked.
So this series adds first some generic checker function, which might
be used to add this or similar checks in future, then we introduce
that particular UHBR check.
Stanislav Lisovskiy (2):
drm/i915: Add generic constraint
clock (32 bit per lane for DP2) instead of port
clock in the formula(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
the less demanding could
be used, thus resulting in waste of power.
BSpec: 64636
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm
ved redundant kernel-doc and indentation(Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 156 +++--
drivers/gpu/drm/i915/i915_reg.h| 14 ++
2 files changed, 159 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i
- Limit this to only DISPLAY_VER <= 13
HSDES: 1406899791
BSPEC: 49259
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
ved redundant kernel-doc and indentation(Jani Nikula)
v4: - Fixed some checkpatch warnings
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 156 +++--
drivers/gpu/drm/i915/i915_reg.h| 14 ++
2 files changed, 159 insertions(+), 11 deleti
hen any pipe power well will disable or enable.
v2: - Make intel_cdclk_need_serialize static to make CI compiler happy.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 174 +++--
drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +
drivers/gpu/
According to spec, we should check if output_bpp * pixel_rate is less
than DDI clock * 72, if UHBR is used.
v2: - s/pipe_config/crtc_state/ (Jani Nikula)
- Merged previous patch into that one, to remove empty function(Jani Nikula)
HSDES: 1406899791
BSPEC: 49259
Signed-off-by: Stanislav
hen any pipe power well will disable or enable.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 174 +++--
drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +
drivers/gpu/drm/i915/i915_reg.h| 14 ++
3 files changed, 176 inserti
output BPP's can only be chosen within range of 8 to 27(BSpec 49259).
This all applied together allows to fix existing FIFO underruns, which we
have in many DSC tests.
BSpec: 49259
HSDES: 18027167222
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 21
-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index bf391a6cd8d6..83c98791fea3 100644
--- a/drivers/gpu/drm/i915/display
kernel-doc and indentation(Jani Nikula)
v4: - Fixed some checkpatch warnings
v5: - According to HW team comments that change should affect only DG2,
fix correspodent platform check to account this.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 156
For obvious reasons, we use compressed bpp instead of pipe bpp for
DSC DP SST case. Lets be consistent and use compressed bpp instead of
pipe bpp, also in DP MST DSC case.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
1 file changed, 1 insertion
DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH.
This might also allow us to get rid of an ugly compressed bpp recalculation,
which we had to add to make some MST hubs usable.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 76 ++---
1 file changed, 52 insertions(+), 24 deletions
DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH.
This might also allow us to get rid of an ugly compressed bpp recalculation,
which we had to add to make some MST hubs usable.
v2: - Fix operator precedence
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 76 ++---
1 file changed
, as it seems that we needed this anyway on
all of those(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/skl_watermark.c | 26 +++-
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers
any power well
will disable or enable.
v2: - Fixed identation(Stanislav Lisovskiy)
- Made conditions more specific(in the commit we declare that
we do this for DG2 only, however that commit changes >= to
== for many other platforms.(Stanislav Lisovskiy)
v3: - Refactored co
any power well
will disable or enable.
v2: - Fixed identation(Stanislav Lisovskiy)
- Made conditions more specific(in the commit we declare that
we do this for DG2 only, however that commit changes >= to
== for many other platforms.(Stanislav Lisovskiy)
Signed-off-by: Jigar
kernel-doc and indentation(Jani Nikula)
v4: - Fixed some checkpatch warnings
v5: - According to HW team comments that change should affect only DG2,
fix correspodent platform check to account this.
v6: - Added one more missing IS_DG2 check(Vinod Govindapillai)
Signed-off-by: Stanislav
.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 7d9578ebae556
fix it as described in BSpec 68907.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display
ump up CDCLK many times for similar reasons.
v2: - Use new intel_dsc_get_num_vdsc_instances to determine number of VDSC
engines, instead of slice count(Ankit Nautiyal)
v3: - s/u8/int/ (Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.
-compressed case it can be usualy lower)
However if we have 2 DSC engines CDCLK can be ~pixel clock / 2 and so on.
Lets do the estimation more properly based on amount of VDSC engines used.
That most likely is going to fix some FIFO underruns, we are currently
having.
Stanislav Lisovskiy (2):
drm/i915
VDSC code.
v2: - s/u8/int/ (Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 15 +++
drivers/gpu/drm/i915/display/intel_vdsc.h | 1 +
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
VDSC code.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 15 +++
drivers/gpu/drm/i915/display/intel_vdsc.h | 1 +
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915
-compressed case it can be usualy lower)
However if we have 2 DSC engines CDCLK can be ~pixel clock / 2 and so on.
Lets do the estimation more properly based on amount of VDSC engines used.
That most likely is going to fix some FIFO underruns, we are currently
having.
Stanislav Lisovskiy (2):
drm/i915
ump up CDCLK many times for similar reasons.
v2: - Use new intel_dsc_get_num_vdsc_instances to determine number of VDSC
engines, instead of slice count(Ankit Nautiyal)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13 +++--
1 file chang
.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0490c6412ab5..68958ba0ef49 100644
--- a/drivers/gpu
.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3ba4a2fef98a..9c587b40cf42 100644
--- a/drivers/gpu/drm/i915
601 - 700 of 786 matches
Mail list logo
