On Wed, 2012-06-27 at 22:10 +1000, Benjamin Herrenschmidt wrote:
From: David Gibson da...@gibson.dropbear.id.au
This adds support for then new reset htab ioctl which allows qemu
to properly cleanup the MMU hash table when the guest is reset. With
the corresponding kernel support, reset of a
On 07/10/2012 06:57 AM, Xiao Guangrong wrote:
On 07/10/2012 01:05 AM, Avi Kivity wrote:
Currently we check that the mmu root exits before every entry. Use the
existing KVM_REQ_MMU_RELOAD mechanism instead, by making it really reload
the mmu, and by adding the request to mmu initialization
On Tue, 2012-07-10 at 17:25 +1000, Benjamin Herrenschmidt wrote:
On Wed, 2012-06-27 at 22:10 +1000, Benjamin Herrenschmidt wrote:
From: David Gibson da...@gibson.dropbear.id.au
This adds support for then new reset htab ioctl which allows qemu
to properly cleanup the MMU hash table when
On 07/09/2012 01:25 PM, Christian Borntraeger wrote:
On 09/07/12 08:20, Raghavendra K T wrote:
Currently Pause Looop Exit (PLE) handler is doing directed yield to a
random VCPU on PL exit. Though we already have filtering while choosing
the candidate to yield_to, we can do better.
Problem is,
On 07/09/2012 05:42 PM, Jan Kiszka wrote:
As Avi noted recently, there is a problem in way we inject interrupts
into the userspace APIC under KVM: The TRP check over the iothread may
race with the VCPU raising the TPR value while in KVM mode. Patch 3
addresses this issue.
The other two
H_CEDE should enable the vcpu's MSR:EE bit. It does on HV KVM (it's
burried in the assembly code though) and as far as I can tell, qemu
does it as well.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
Alex, you probably want that in -now- (and maybe even in stable).
Without
On Mon, Jul 09, 2012 at 08:05:40PM +0300, Avi Kivity wrote:
It's a write-only bit, set by the timer and cleared by the main loop.
Remove it. Retain the definition since ppc uses it.
Signed-off-by: Avi Kivity a...@redhat.com
---
arch/x86/kvm/timer.c | 8 ++--
arch/x86/kvm/x86.c | 1
On 07/10/2012 11:50 AM, Gleb Natapov wrote:
On Mon, Jul 09, 2012 at 08:05:40PM +0300, Avi Kivity wrote:
It's a write-only bit, set by the timer and cleared by the main loop.
Remove it. Retain the definition since ppc uses it.
Signed-off-by: Avi Kivity a...@redhat.com
---
On 07/10/2012 03:17 AM, Andrew Theurer wrote:
On Mon, 2012-07-09 at 11:50 +0530, Raghavendra K T wrote:
Currently Pause Looop Exit (PLE) handler is doing directed yield to a
random VCPU on PL exit. Though we already have filtering while choosing
the candidate to yield_to, we can do better.
On 07/10/2012 03:17 AM, Andrew Theurer wrote:
On Mon, 2012-07-09 at 11:50 +0530, Raghavendra K T wrote:
Currently Pause Looop Exit (PLE) handler is doing directed yield to a
random VCPU on PL exit. Though we already have filtering while choosing
the candidate to yield_to, we can do better.
Hi,
Am 09.07.2012 22:37, schrieb Juan Quintela:
Please send in any agenda items you are interested in covering.
Steps towards CPU hotplug:
* how to model CPUState as a DeviceState
* coordination of APIC-related x86 CPU remodelling
Thanks,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5,
On 10.07.2012, at 10:16, Benjamin Herrenschmidt wrote:
On Tue, 2012-07-10 at 17:25 +1000, Benjamin Herrenschmidt wrote:
On Wed, 2012-06-27 at 22:10 +1000, Benjamin Herrenschmidt wrote:
From: David Gibson da...@gibson.dropbear.id.au
This adds support for then new reset htab ioctl which
On Mon, Jul 09, 2012 at 04:34:50PM +0300, Avi Kivity wrote:
On 07/09/2012 04:23 PM, Xiao Guangrong wrote:
On 07/09/2012 08:49 PM, Avi Kivity wrote:
On 07/09/2012 02:23 PM, Gleb Natapov wrote:
kvm-unit-tests.git has a test for xchg to mmio. Does it still work?
I agree this code has to
On 07/10/2012 01:36 PM, Gleb Natapov wrote:
On Mon, Jul 09, 2012 at 04:34:50PM +0300, Avi Kivity wrote:
On 07/09/2012 04:23 PM, Xiao Guangrong wrote:
On 07/09/2012 08:49 PM, Avi Kivity wrote:
On 07/09/2012 02:23 PM, Gleb Natapov wrote:
kvm-unit-tests.git has a test for xchg to mmio.
On Tue, Jul 10, 2012 at 01:45:15PM +0300, Avi Kivity wrote:
On 07/10/2012 01:36 PM, Gleb Natapov wrote:
On Mon, Jul 09, 2012 at 04:34:50PM +0300, Avi Kivity wrote:
On 07/09/2012 04:23 PM, Xiao Guangrong wrote:
On 07/09/2012 08:49 PM, Avi Kivity wrote:
On 07/09/2012 02:23 PM, Gleb
On 07/10/2012 04:00 AM, Rik van Riel wrote:
On 07/09/2012 02:20 AM, Raghavendra K T wrote:
+bool kvm_arch_vcpu_check_and_update_eligible(struct kvm_vcpu *vcpu)
+{
+ bool eligible;
+
+ eligible = !vcpu-arch.plo.pause_loop_exited ||
+ (vcpu-arch.plo.pause_loop_exited
+
On 07/10/2012 03:17 AM, Andrew Theurer wrote:
On Mon, 2012-07-09 at 11:50 +0530, Raghavendra K T wrote:
Currently Pause Looop Exit (PLE) handler is doing directed yield to a
random VCPU on PL exit. Though we already have filtering while choosing
the candidate to yield_to, we can do better.
On Feb 29, 2012, at 7:20 PM, Olivia Yin wrote:
From: Liu Yu yu@freescale.com
So that we can call it when improving SPE switch like book3e did for fp
switch.
Signed-off-by: Liu Yu yu@freescale.com
Signed-off-by: Olivia Yin hong-hua@freescale.com
---
v2: add Signed-off-by
On 07/10/2012 01:48 PM, Gleb Natapov wrote:
But the code is already here, why drop it?
The read cache is not effective for multiple disjunct reads.
What do you mean?
If an instruction reads from several sources in mmio, then the first
read will be flushed from the cache by the
On Tue, Jul 10, 2012 at 11:39:57AM +0300, Dor Laor wrote:
On 07/01/2012 06:08 PM, Michael S. Tsirkin wrote:
Support the new PV EOI flag in kvm - it recently got merged
into kvm.git. Set by default with -cpu kvm.
Set for -cpu qemu by adding +kvm_pv_eoi.
Clear by adding -kvm_pv_eoi to -cpu
On Tue, Jul 10, 2012 at 03:50:39PM +0300, Avi Kivity wrote:
On 07/10/2012 01:48 PM, Gleb Natapov wrote:
But the code is already here, why drop it?
The read cache is not effective for multiple disjunct reads.
What do you mean?
If an instruction reads from several sources in
Dear Experts,
Sorry to bother you. I am Shouyu, a postgraduate student of Beihang
University in China.
I am doing a research on “deterministic replay for KVM”, but I came up with
some questions which has bothered me for two weeks and I can’t work it out by
myself, so I have to ask for your
On Tue, 2012-07-10 at 17:24 +0530, Raghavendra K T wrote:
On 07/10/2012 03:17 AM, Andrew Theurer wrote:
On Mon, 2012-07-09 at 11:50 +0530, Raghavendra K T wrote:
Currently Pause Looop Exit (PLE) handler is doing directed yield to a
random VCPU on PL exit. Though we already have filtering
Hi
We discussed this
- cpu_index: is that transmited? Yes (Juan). we need to be sure that
cpu_common and cpu use the same index/whatever it is changed
- We used cpu_index for SEABIOS interface as apic_id (Eduardo)
- cpu_hotplug makes that difficult. How to pass the apic_id to
seabios
This is expected behaviour. Modern OS's rely heavily on timer
interrupts. If you are disabling them completely the OS will not
execute the usual way. Though if you are injecting timer interrupts
which are synchronous with the record process, the guest should run
without any problems.
On Tue, Jul
https://bugzilla.kernel.org/show_bug.cgi?id=44271
Alan a...@lxorguk.ukuu.org.uk changed:
What|Removed |Added
Status|NEW |NEEDINFO
On 07/10/2012 04:01 PM, Gleb Natapov wrote:
On Tue, Jul 10, 2012 at 03:50:39PM +0300, Avi Kivity wrote:
On 07/10/2012 01:48 PM, Gleb Natapov wrote:
But the code is already here, why drop it?
The read cache is not effective for multiple disjunct reads.
What do you mean?
Hello,
We're using qemu-kvm on Debian 6 for a VM farm (currently 16 hosts), on HP
blade hardware. We're experiencing issues on our Debian 5 and 6 guests
after we migrate them between hosts. This issue does not occur with the
qemu-kvm binary version 0.14.1 (compiled from source), but does occur
On Thu, Jul 05, 2012 at 09:49:40AM -0700, Chegu Vinod wrote:
Changes since v2:
- Using unsigned long * for the node_cpumask[].
- Use bitmap_new() instead of g_malloc0() for allocation.
- Don't rely on max_cpus since it may not be initialized
before the numa related qemu options
Hi,
Am 10.07.2012 16:55, schrieb Juan Quintela:
We discussed this
- CPU VMState series by Juan
Question: Could we assign CPU-specific VMStateDescription to
DeviceState::vmsd?
- cpu_index: is that transmited? Yes (Juan). we need to be sure that
cpu_common and cpu use the same
Currently Pause Looop Exit (PLE) handler is doing directed yield to a
random VCPU on PL exit. Though we already have filtering while choosing
the candidate to yield_to, we can do better.
Problem is, for large vcpu guests, we have more probability of yielding
to a bad vcpu. We are not able to
From: Raghavendra K T raghavendra...@linux.vnet.ibm.com
Currently PLE handler can repeatedly do a directed yield to same vcpu
that has recently done PL exit. This can degrade the performance.
Try to yield to most eligible guy instead by alternate yielding.
Precisely, give chance to a VCPU which
On 07/10/2012 03:31 PM, Raghavendra K T wrote:
From: Raghavendra K Traghavendra...@linux.vnet.ibm.com
Noting pause loop exited vcpu helps in filtering right candidate to yield.
Yielding to same vcpu may result in more wastage of cpu.
Signed-off-by: Raghavendra K
* Raghavendra K T raghavendra...@linux.vnet.ibm.com wrote:
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
@@ -1595,6 +1595,9 @@ void kvm_vcpu_on_spin(struct kvm_vcpu *me)
continue;
if (waitqueue_active(vcpu-wq))
Hi Avi,
This is my current patch queue for ppc. Please pull.
It contains the following changes:
* VERY IMPORTANT (please forward to -stable):
Fix H_CEDE with PR KVM and newer guest kernels
* Prepare some of the booke code for 64 bit support
* BookE: Fix ESR flag in DSI
* BookE: Add
From: Bharat Bhushan r65...@freescale.com
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/hw_irq.h |2 ++
arch/powerpc/kvm/booke.c | 21 +
2 files changed, 23 insertions(+), 0
From: Bharat Bhushan r65...@freescale.com
Watchdog is taken at critical exception level. So this patch
is tested with host watchdog exception happening when guest
is running.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
From: Benjamin Herrenschmidt b...@kernel.crashing.org
H_CEDE should enable the vcpu's MSR:EE bit. It does on HV KVM (it's
burried in the assembly code though) and as far as I can tell, qemu
does it as well.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: Alexander
From: Bharat Bhushan r65...@freescale.com
rfci instruction and CSRR0/1 registers are emulated.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
Signed-off-by: Alexander Graf
From: Mihai Caraman mihai.cara...@freescale.com
tlbilxva emulation was using an u32 variable for guest effective address.
Replace it with gva_t type to handle 64-bit guests.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
From: Paul Mackerras pau...@samba.org
At the moment we call kvmppc_pin_guest_page() in kvmppc_update_vpa()
with two spinlocks held: the vcore lock and the vcpu-vpa_update_lock.
This is not good, since kvmppc_pin_guest_page() calls down_read() and
get_user_pages_fast(), both of which can sleep.
From: Bharat Bhushan bharat.bhus...@freescale.com
Qemu and KVM linux/kvm.h were not in sync.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v2:
- No change (same as [PATCH 1/4] Synchronize the linux-headers)
linux-headers/linux/kvm.h |3 +++
1 files changed, 3
This patch adds the support to enable KVM emulated watchdog
if KVM supports (use the capability enablement in watchdog handler).
Also added the support to handle the exit caused by watchdog
(KVM_EXIT_WDT). In the handling we clear the TSR register.
Watchdog state machine is cleared whenever VM
On Wed, 2012-06-27 at 22:10 +1000, Benjamin Herrenschmidt wrote:
From: David Gibson da...@gibson.dropbear.id.au
This adds support for then new reset htab ioctl which allows qemu
to properly cleanup the MMU hash table when the guest is reset. With
the corresponding kernel support, reset of a
On Tue, 2012-07-10 at 17:25 +1000, Benjamin Herrenschmidt wrote:
On Wed, 2012-06-27 at 22:10 +1000, Benjamin Herrenschmidt wrote:
From: David Gibson da...@gibson.dropbear.id.au
This adds support for then new reset htab ioctl which allows qemu
to properly cleanup the MMU hash table when
H_CEDE should enable the vcpu's MSR:EE bit. It does on HV KVM (it's
burried in the assembly code though) and as far as I can tell, qemu
does it as well.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
Alex, you probably want that in -now- (and maybe even in stable).
Without
On 10.07.2012, at 10:16, Benjamin Herrenschmidt wrote:
On Tue, 2012-07-10 at 17:25 +1000, Benjamin Herrenschmidt wrote:
On Wed, 2012-06-27 at 22:10 +1000, Benjamin Herrenschmidt wrote:
From: David Gibson da...@gibson.dropbear.id.au
This adds support for then new reset htab ioctl which
On Feb 29, 2012, at 7:20 PM, Olivia Yin wrote:
From: Liu Yu yu@freescale.com
So that we can call it when improving SPE switch like book3e did for fp
switch.
Signed-off-by: Liu Yu yu@freescale.com
Signed-off-by: Olivia Yin hong-hua@freescale.com
---
v2: add Signed-off-by
Hi Avi,
This is my current patch queue for ppc. Please pull.
It contains the following changes:
* VERY IMPORTANT (please forward to -stable):
Fix H_CEDE with PR KVM and newer guest kernels
* Prepare some of the booke code for 64 bit support
* BookE: Fix ESR flag in DSI
* BookE: Add
From: Bharat Bhushan r65...@freescale.com
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/hw_irq.h |2 ++
arch/powerpc/kvm/booke.c | 21 +
2 files changed, 23 insertions(+), 0
From: Mihai Caraman mihai.cara...@freescale.com
ESR register is required by Data Storage Interrupt handling code.
Add the specific flag to the interrupt handler.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
From: Mihai Caraman mihai.cara...@freescale.com
64-bit host needs to remain in 64-bit mode when an exception take place.
Set interrupt computaion mode in EPCR register.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
From: Varun Sethi varun.se...@freescale.com
Add support for std/ld emulation.
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/emulate.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git
From: Benjamin Herrenschmidt b...@kernel.crashing.org
H_CEDE should enable the vcpu's MSR:EE bit. It does on HV KVM (it's
burried in the assembly code though) and as far as I can tell, qemu
does it as well.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: Alexander
From: Bharat Bhushan r65...@freescale.com
rfci instruction and CSRR0/1 registers are emulated.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
Signed-off-by: Alexander Graf
From: Mihai Caraman mihai.cara...@freescale.com
tlbilxva emulation was using an u32 variable for guest effective address.
Replace it with gva_t type to handle 64-bit guests.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
From: Paul Mackerras pau...@samba.org
At the moment we call kvmppc_pin_guest_page() in kvmppc_update_vpa()
with two spinlocks held: the vcore lock and the vcpu-vpa_update_lock.
This is not good, since kvmppc_pin_guest_page() calls down_read() and
get_user_pages_fast(), both of which can sleep.
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