Currently, kdump just makes all the logical processors leave VMX operation by
executing VMXOFF instruction, so any VMCSs active on the logical processors may
be corrupted. But, sometimes, we need the VMCSs to debug guest images contained
in the host vmcore. To prevent the corruption, we should
This patch provides a way to VMCLEAR VMCSs related to guests
on all cpus before executing the VMXOFF when doing kdump. This
is used to ensure the VMCSs in the vmcore updated and
non-corrupted.
Signed-off-by: Zhang Yanfei zhangyan...@cn.fujitsu.com
---
arch/x86/include/asm/kexec.h |2 ++
The vmclear function will be assigned to the callback function pointer
when loading kvm-intel module. And the bitmap indicates whether we
should do VMCLEAR operation in kdump. The bits in the bitmap are
set/unset according to different conditions.
Signed-off-by: Zhang Yanfei
On Wed, Dec 05, 2012 at 06:02:59AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 01:55:17AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-04:
On Tue, Dec 04, 2012 at 06:39:50AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on
On Wed, Dec 05, 2012 at 01:32:15AM +0800, yi li wrote:
My test:
1:guest os has 2 vcpu and has a virtio netcard, also host os just has
2 cpu cores, and do not do any smp_affinity
What about running the same test but on 32 host cpus. I expect result to
be much different.
2:using the jprobe
On Sat, Nov 10, 2012 at 03:45:32PM +, Christoffer Dall wrote:
From: Marc Zyngier marc.zyng...@arm.com
Add the init code for the hypervisor, the virtual machine, and
the virtual CPUs.
An interrupt handler is also wired to allow the VGIC maintenance
interrupts, used to deal with level
On Sat, Nov 10, 2012 at 03:45:39PM +, Christoffer Dall wrote:
From: Marc Zyngier marc.zyng...@arm.com
If we have level interrupts already programmed to fire on a vcpu,
there is no reason to kick it after injecting a new interrupt,
as we're guaranteed that we'll exit when the level
This patch implements the ethtool_{set|get}_channels method of virtio-net to
allow user to change the number of queues when the device is running on demand.
Signed-off-by: Jason Wang jasow...@redhat.com
---
drivers/net/virtio_net.c | 43 +++
1 files
This patch adds the multiqueue (VIRTIO_NET_F_RFS) support to virtio_net
driver. VIRTIO_NET_F_RFS capable device could allow the driver to do packet
transmission and reception through multiple queue pairs and does the packet
steering to get better performance. By default, one one queue pair is
To support multiqueue transmitq/receiveq, the first step is to separate queue
related structure from virtnet_info. This patch introduce send_queue and
receive_queue structure and use the pointer to them as the parameter in
functions handling sending/receiving.
Signed-off-by: Krishna Kumar
Hi all:
This series is an update version of multiqueue virtio-net driver based on
Krishna Kumar's work to let virtio-net use multiple rx/tx queues to do the
packets reception and transmission. Please review and comments.
A protype implementation of qemu-kvm support could by found in
On Wed, Dec 05, 2012 at 10:43:58AM +, Will Deacon wrote:
On Sat, Nov 10, 2012 at 03:45:39PM +, Christoffer Dall wrote:
From: Marc Zyngier marc.zyng...@arm.com
If we have level interrupts already programmed to fire on a vcpu,
there is no reason to kick it after injecting a new
On Wed, Dec 05, 2012 at 03:43:41AM +, Zhang, Yang Z wrote:
@@ -5657,12 +5673,20 @@ static int vcpu_enter_guest(struct kvm_vcpu
*vcpu)
}
if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
+ /* update archtecture specific hints for APIC
+ *
For the sake of public education, let me rewrite this patch a bit to
illustrate why atomic_t's are bad, and then people can review this
instead.
Every change I've made here is functionally equivalent to the behaviour
of the atomic type; I have not added any new bugs here that aren't
present in
On Tue, Dec 04, 2012 at 01:13:30PM +0100, Julian Stecklina wrote:
VMX behaves now as SVM wrt to FPU initialization. Code has been moved to
generic code path. General-purpose registers are now cleared on reset and
INIT. SVM code properly initializes EDX.
Looks good overall, small bug bellow
VMX behaves now as SVM wrt to FPU initialization. Code has been moved to
generic code path. General-purpose registers are now cleared on reset and
INIT. SVM code properly initializes EDX.
Signed-off-by: Julian Stecklina jstec...@os.inf.tu-dresden.de
---
arch/x86/kvm/cpuid.c | 1 +
On 05/12/12 10:58, Russell King - ARM Linux wrote:
On Wed, Dec 05, 2012 at 10:43:58AM +, Will Deacon wrote:
On Sat, Nov 10, 2012 at 03:45:39PM +, Christoffer Dall wrote:
From: Marc Zyngier marc.zyng...@arm.com
If we have level interrupts already programmed to fire on a vcpu,
there is
On Wed, Dec 05, 2012 at 12:17:57PM +, Marc Zyngier wrote:
On 05/12/12 10:58, Russell King - ARM Linux wrote:
On Wed, Dec 05, 2012 at 10:43:58AM +, Will Deacon wrote:
On Sat, Nov 10, 2012 at 03:45:39PM +, Christoffer Dall wrote:
From: Marc Zyngier marc.zyng...@arm.com
If we
I am deeply sorry.
I was busy first time I read this, so I postponed answering and ended up
forgetting.
Sorry
include/linux/sched.h:
unsigned long long run_delay; /* time spent waiting on a runqueue */
So if you are out of the runqueue, you won't get steal time accounted,
and then I truly
On Wed, Oct 17, 2012 at 06:05:55PM +0200, Michael S. Tsirkin wrote:
We can deliver certain interrupts, notably MSIX,
from atomic context.
Here's an untested patch to do this (compiled only).
Changes from v2:
Don't inject broadcast interrupts directly
Changes from v1:
Tried to address
On Wed, Dec 05, 2012 at 01:00:59PM +0100, Julian Stecklina wrote:
VMX behaves now as SVM wrt to FPU initialization. Code has been moved to
generic code path. General-purpose registers are now cleared on reset and
INIT. SVM code properly initializes EDX.
Signed-off-by: Julian Stecklina
On 05/12/12 12:29, Russell King - ARM Linux wrote:
On Wed, Dec 05, 2012 at 12:17:57PM +, Marc Zyngier wrote:
On 05/12/12 10:58, Russell King - ARM Linux wrote:
On Wed, Dec 05, 2012 at 10:43:58AM +, Will Deacon wrote:
On Sat, Nov 10, 2012 at 03:45:39PM +, Christoffer Dall wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 06:02:59AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 01:55:17AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-04:
On Tue, Dec 04, 2012 at 06:39:50AM +, Zhang, Yang Z wrote:
https://bugzilla.kernel.org/show_bug.cgi?id=50921
--- Comment #18 from Gleb g...@redhat.com 2012-12-05 14:15:30 ---
Created an attachment (id=88501)
-- (https://bugzilla.kernel.org/attachment.cgi?id=88501)
patch to implement aad (b5) instruction.
Can you see if this patch helps?
--
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 03:43:41AM +, Zhang, Yang Z wrote:
@@ -5657,12 +5673,20 @@ static int vcpu_enter_guest(struct kvm_vcpu
*vcpu)
}
if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
+ /* update archtecture specific hints
https://bugzilla.kernel.org/show_bug.cgi?id=50921
Gleb g...@redhat.com changed:
What|Removed |Added
Attachment #88501|patch to implement aad (b5) |patch to implement aad (D5)
VMX behaves now as SVM wrt to FPU initialization. Code has been moved to
generic code path. General-purpose registers are now cleared on reset and
INIT. SVM code properly initializes EDX.
Signed-off-by: Julian Stecklina jstec...@os.inf.tu-dresden.de
---
arch/x86/kvm/cpuid.c | 1 +
Thus spake Gleb Natapov g...@redhat.com:
-ret = fx_init(vmx-vcpu);
-if (ret != 0)
-goto out;
-
Label out is now unused. Compiler complains.
5th time's the charm. ;) Patch is updated.
Julian
--
To unsubscribe from this list: send the line unsubscribe kvm in
the body of a
On Wed, Dec 05, 2012 at 01:51:36PM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 06:02:59AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 01:55:17AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on
On Wed, Dec 05, 2012 at 02:16:52PM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 03:43:41AM +, Zhang, Yang Z wrote:
@@ -5657,12 +5673,20 @@ static int vcpu_enter_guest(struct kvm_vcpu
*vcpu)
}
if
On Wed, Dec 05, 2012 at 01:55:13AM +0800, Xiantao Zhang wrote:
From: Zhang Xiantao xiantao.zh...@intel.com
This two bits{bit 6 in exit_qualification, and bit 24 in
VMX_EPT_VPID_CAP_MSR}
are not available in SDM, remove them for consistence.
Zhang Xiantao (2):
kvm: remove unnecessary
On Wed, Dec 05, 2012 at 01:40:24PM +, Marc Zyngier wrote:
Admittedly, the whole sequence should be rewritten to be clearer. What
it does is If we're running a guest and there is no active interrupt,
then kick the guest.
On the whole this entire thing should be written clearer; from the
On Wed, Dec 05, 2012 at 03:26:19PM +0100, Julian Stecklina wrote:
VMX behaves now as SVM wrt to FPU initialization. Code has been moved to
generic code path. General-purpose registers are now cleared on reset and
INIT. SVM code properly initializes EDX.
Signed-off-by: Julian Stecklina
From: Marc Zyngier marc.zyng...@arm.com
A bug in the KVM GIC init code set the priority mask to the
highest possible value, while the reset value should be zero.
Now that the kernel bug is fixed, kvm-tool must properly configure
its GIC CPU interface in order to receive the boot IPI. Just set
Cosmetic patch to correct the pre-processor guards for arm in
kvm-cpu-arch.h. It's not something to lose sleep over but I find it
incredibly irritating!
Signed-off-by: Will Deacon will.dea...@arm.com
---
tools/kvm/arm/include/kvm/kvm-cpu-arch.h | 6 +++---
1 file changed, 3 insertions(+), 3
Currently, only x86 has architecture command-line options (for setting
the BIOS video mode) however this is likely to become more common in the
future.
This patch adds some simple macros and a struct definition to allow
architectures to augment the command-line options with private
definitions.
Zhang Yanfei zhangyan...@cn.fujitsu.com writes:
Currently, kdump just makes all the logical processors leave VMX operation by
executing VMXOFF instruction, so any VMCSs active on the logical processors
may
be corrupted. But, sometimes, we need the VMCSs to debug guest images
contained
in
On Mon, 2012-12-03 at 12:58 +0200, Michael S. Tsirkin wrote:
Add RFS support to virtio network device.
Add a new feature flag VIRTIO_NET_F_RFS for this feature, a new
configuration field max_virtqueue_pairs to detect supported number of
virtqueues as well as a new command VIRTIO_NET_CTRL_RFS
On Tue, Dec 04, 2012 at 07:17:11AM +0800, Xiao Guangrong wrote:
There are two cases we need to adjust page size in set_spte:
1): the one is other vcpu creates new sp in the window between mapping_level()
and acquiring mmu-lock.
2): the another case is the new sp is created by itself
On Mon, Dec 03, 2012 at 04:39:30PM -0700, Alex Williamson wrote:
In order to make the memslots array grow on demand, move the private
slots to the lower indexes of the array. The private slots are
assumed likely to be in use, so if we didn't do this we'd end up
allocating the full memslots
On Mon, Dec 03, 2012 at 04:39:36PM -0700, Alex Williamson wrote:
struct kvm_memory_slot is currently 52 bytes (LP64), not counting the
arch data. On x86 this means the memslot array to support a tiny 32+3
entries (user+private) is over 2k. We'd like to support more slots
so that we can
On Mon, Dec 03, 2012 at 04:39:24PM -0700, Alex Williamson wrote:
This allows us to resize this structure and therefore the number of
memslots as part of the RCU update.
Why is this necessary? struct memslots is updated, message above
conflicts with that.
If there is a reason, id_to_index
On Mon, Dec 03, 2012 at 04:39:05PM -0700, Alex Williamson wrote:
Memory slots are currently a fixed resource with a relatively small
limit. When using PCI device assignment in a qemu guest it's fairly
easy to exhaust the number of available slots. I posted patches
exploring growing the
On Mon, Dec 03, 2012 at 03:01:03PM +0800, Yang Zhang wrote:
Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
manually, which is fully taken care of by the hardware. This needs
some special awareness into existing interrupr injection path:
- for pending interrupt, instead of
On Wed, Dec 05, 2012 at 01:14:38PM +0200, Gleb Natapov wrote:
On Wed, Dec 05, 2012 at 03:43:41AM +, Zhang, Yang Z wrote:
@@ -5657,12 +5673,20 @@ static int vcpu_enter_guest(struct kvm_vcpu
*vcpu)
}
if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
On Wed, 2012-12-05 at 19:32 -0200, Marcelo Tosatti wrote:
On Mon, Dec 03, 2012 at 04:39:05PM -0700, Alex Williamson wrote:
Memory slots are currently a fixed resource with a relatively small
limit. When using PCI device assignment in a qemu guest it's fairly
easy to exhaust the number of
On Wed, 2012-12-05 at 19:22 -0200, Marcelo Tosatti wrote:
On Mon, Dec 03, 2012 at 04:39:24PM -0700, Alex Williamson wrote:
This allows us to resize this structure and therefore the number of
memslots as part of the RCU update.
Why is this necessary? struct memslots is updated, message
On Wed, 2012-12-05 at 19:24 -0200, Marcelo Tosatti wrote:
On Mon, Dec 03, 2012 at 04:39:30PM -0700, Alex Williamson wrote:
In order to make the memslots array grow on demand, move the private
slots to the lower indexes of the array. The private slots are
assumed likely to be in use, so if
On Wed, 2012-12-05 at 19:26 -0200, Marcelo Tosatti wrote:
On Mon, Dec 03, 2012 at 04:39:36PM -0700, Alex Williamson wrote:
struct kvm_memory_slot is currently 52 bytes (LP64), not counting the
arch data. On x86 this means the memslot array to support a tiny 32+3
entries (user+private) is
On Wed, Dec 05, 2012 at 03:17:13AM +, Zhang, Yang Z wrote:
Marcelo Tosatti wrote on 2012-12-05:
On Mon, Dec 03, 2012 at 03:01:02PM +0800, Yang Zhang wrote:
- APIC read doesn't cause VM-Exit
- APIC write becomes trap-like
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
The current eventfd code assumes that when we have eventfd, we also have
irqfd for in-kernel interrupt delivery. This is not necessarily true. On
PPC we don't have an in-kernel irqchip yet, but we can still support easily
support eventfd.
Signed-off-by: Alexander Graf ag...@suse.de
---
From: Paul Mackerras pau...@samba.org
This adds basic emulation of the PURR and SPURR registers. We assume
we are emulating a single-threaded core, so these advance at the same
rate as the timebase. A Linux kernel running on a POWER7 expects to
be able to access these registers and is not
From: Paul Mackerras pau...@samba.org
This fixes a bug where adding a new guest HPT entry via the H_ENTER
hcall would lose the changed bit in the reverse map information
for the guest physical page being mapped. The result was that the
KVM_GET_DIRTY_LOG could return a zero bit for the page even
From: Michael Ellerman mich...@ellerman.id.au
Signed-off-by: Michael Ellerman mich...@ellerman.id.au
Signed-off-by: Alexander Graf ag...@suse.de
---
MAINTAINERS |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4376c52..7034467 100644
---
From: Mihai Caraman mihai.cara...@freescale.com
GET_VCPU define will not be implemented for 64-bit for performance reasons
so get rid of it also on 32-bit.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
From: Mihai Caraman mihai.cara...@freescale.com
Implement ONE_REG interface for EPCR register adding KVM_REG_PPC_EPCR to
the list of ONE_REG PPC supported registers.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
[agraf: remove HV dependency, use get/put_user]
Signed-off-by: Alexander
From: Mihai Caraman mihai.cara...@freescale.com
Add interrupt handling support for 64-bit bookehv hosts. Unify 32 and 64 bit
implementations using a common stack layout and a common execution flow starting
from kvm_handler_common macro. Update documentation for 64-bit input register
values. This
From: Mihai Caraman mihai.cara...@freescale.com
Add EPCR support in booke mtspr/mfspr emulation. EPCR register is defined only
for 64-bit and HV categories, we will expose it at this point only to 64-bit
virtual processors running on 64-bit HV hosts.
Define a reusable setter function for vcpu's
From: Mihai Caraman mihai.cara...@freescale.com
Extend MAS2 EPN mask to retain most significant bits on 64-bit hosts.
Use this mask in tlb effective address accessor.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
In BookE, EPCR is defined and valid when either the HV or the 64bit
category are implemented. Reflect this in the field definition.
Today the only KVM target on 64bit is HV enabled, so there is no
change in actual source code, but this keeps the code closer to the
spec and doesn't build up
From: Mihai Caraman mihai.cara...@freescale.com
When delivering guest IRQs, update MSR computation mode according to guest
interrupt computation mode found in EPCR.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
[agraf: remove HV dependency in the code]
Signed-off-by: Alexander Graf
From: Mihai Caraman mihai.cara...@freescale.com
Add emulation helper for getting instruction ea and refactor tlb instruction
emulation to use it.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
[agraf: keep rt variable around]
Signed-off-by: Alexander Graf ag...@suse.de
---
From: Mihai Caraman mihai.cara...@freescale.com
Mask high 32 bits of MAS2's effective page number in tlbwe emulation for guests
running in 32-bit mode.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/e500_tlb.c |2 ++
From: Mihai Caraman mihai.cara...@freescale.com
Mask high 32 bits of effective address in emulation layer for guests running
in 32-bit mode.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
[agraf: fix indent]
Signed-off-by: Alexander Graf ag...@suse.de
---
From: Mihai Caraman mihai.cara...@freescale.com
Include header file for get_tb() declaration.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/booke.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git
From: Paul Mackerras pau...@samba.org
When we change or remove a HPT (hashed page table) entry, we can do
either a global TLB invalidation (tlbie) that works across the whole
machine, or a local invalidation (tlbiel) that only affects this core.
Currently we do local invalidations if the VM has
From: Mihai Caraman mihai.cara...@freescale.com
64-bit GCC 4.5.1 warns about an uninitialized variable which was guarded
by a flag. Initialize the variable to make it happy.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
[agraf: reword comment]
Signed-off-by: Alexander Graf
From: Paul Mackerras pau...@samba.org
Currently, if a machine check interrupt happens while we are in the
guest, we exit the guest and call the host's machine check handler,
which tends to cause the host to panic. Some machine checks can be
triggered by the guest; for example, if the guest
From: Paul Mackerras pau...@samba.org
The mask of MSR bits that get transferred from the guest MSR to the
shadow MSR included MSR_DE. In fact that bit only exists on Book 3E
processors, and it is assigned the same bit used for MSR_BE on Book 3S
processors. Since we already had MSR_BE in the
From: Paul Mackerras pau...@samba.org
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current-thread.fpr[] array. Ultimately this was because the
vcpu-arch.vsr[] array is sized to be able to store both
From: Paul Mackerras pau...@samba.org
Currently, if the guest does an H_PROTECT hcall requesting that the
permissions on a HPT entry be changed to allow writing, we make the
requested change even if the page is marked read-only in the host
Linux page tables. This is a problem since it would for
From: Paul Mackerras pau...@samba.org
This uses a bit in our record of the guest view of the HPTE to record
when the HPTE gets modified. We use a reserved bit for this, and ensure
that this bit is always cleared in HPTE values returned to the guest.
The recording of modified HPTEs is only done
From: Paul Mackerras pau...@samba.org
With HV-style KVM, we maintain reverse-mapping lists that enable us to
find all the HPT (hashed page table) entries that reference each guest
physical page, with the heads of the lists in the memslot-arch.rmap
arrays. When we reset the HPT (i.e. when we
From: Paul Mackerras pau...@samba.org
This fixes a bug in the code which allows userspace to read out the
contents of the guest's hashed page table (HPT). On the second and
subsequent passes through the HPT, when we are reporting only those
entries that have changed, we were incorrectly
Hi Marcelo / Gleb,
This is my current patch queue for ppc. Please pull.
Major changes this time around include:
- Book3S PR: Multiple fixes for POWER7 hosts
- Book3S HV: Prepare for full state exposure (live migration)
- Add eventfd support
- BookE: Add final bits for 64bit BookE
From: Paul Mackerras pau...@samba.org
This makes a HPTE removal function, kvmppc_do_h_remove(), available
outside book3s_hv_rm_mmu.c. This will be used by the HPT writing
code.
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
From: Paul Mackerras pau...@samba.org
A new ioctl, KVM_PPC_GET_HTAB_FD, returns a file descriptor. Reads on
this fd return the contents of the HPT (hashed page table), writes
create and/or remove entries in the HPT. There is a new capability,
KVM_CAP_PPC_HTAB_FD, to indicate the presence of the
From: Paul Mackerras pau...@samba.org
This restructures the code that creates HPT (hashed page table)
entries so that it can be called in situations where we don't have a
struct vcpu pointer, only a struct kvm pointer. It also fixes a bug
where kvmppc_map_vrma() would corrupt the guest R4 value.
In order to support the generic eventfd infrastructure on PPC, we need
to call into the generic KVM in-kernel device mmio code.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/Kconfig |1 +
arch/powerpc/kvm/Makefile |4 +++-
arch/powerpc/kvm/powerpc.c | 17
On Wed, Dec 05, 2012 at 04:02:53PM -0700, Alex Williamson wrote:
On Wed, 2012-12-05 at 19:26 -0200, Marcelo Tosatti wrote:
On Mon, Dec 03, 2012 at 04:39:36PM -0700, Alex Williamson wrote:
struct kvm_memory_slot is currently 52 bytes (LP64), not counting the
arch data. On x86 this means
On 12/06/2012 05:09 AM, Marcelo Tosatti wrote:
On Tue, Dec 04, 2012 at 07:17:11AM +0800, Xiao Guangrong wrote:
There are two cases we need to adjust page size in set_spte:
1): the one is other vcpu creates new sp in the window between
mapping_level()
and acquiring mmu-lock.
2): the
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 01:51:36PM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 06:02:59AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 01:55:17AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 02:16:52PM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 03:43:41AM +, Zhang, Yang Z wrote:
@@ -5657,12 +5673,20 @@ static int vcpu_enter_guest(struct kvm_vcpu
*vcpu)
}
Marcelo Tosatti wrote on 2012-12-06:
On Mon, Dec 03, 2012 at 03:01:03PM +0800, Yang Zhang wrote:
Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
manually, which is fully taken care of by the hardware. This needs
some special awareness into existing interrupr injection path:
On Wed, 2012-12-05 at 23:45 -0200, Marcelo Tosatti wrote:
On Wed, Dec 05, 2012 at 04:02:53PM -0700, Alex Williamson wrote:
On Wed, 2012-12-05 at 19:26 -0200, Marcelo Tosatti wrote:
On Mon, Dec 03, 2012 at 04:39:36PM -0700, Alex Williamson wrote:
struct kvm_memory_slot is currently 52
Zhang, Yang Z wrote on 2012-12-06:
Marcelo Tosatti wrote on 2012-12-06:
On Mon, Dec 03, 2012 at 03:01:03PM +0800, Yang Zhang wrote:
Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
manually, which is fully taken care of by the hardware. This needs
some special awareness into
On Thu, Dec 06, 2012 at 05:02:15AM +, Zhang, Yang Z wrote:
Zhang, Yang Z wrote on 2012-12-06:
Marcelo Tosatti wrote on 2012-12-06:
On Mon, Dec 03, 2012 at 03:01:03PM +0800, Yang Zhang wrote:
Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
manually, which is fully
On Wed, Dec 05, 2012 at 09:11:40PM -0200, Marcelo Tosatti wrote:
+static int handle_apic_write(struct kvm_vcpu *vcpu)
+{
+unsigned long exit_qualification =
vmcs_readl(EXIT_QUALIFICATION);
+u32 offset = exit_qualification 0xfff;
+
+/* APIC-write VM
Gleb Natapov wrote on 2012-12-06:
On Thu, Dec 06, 2012 at 05:02:15AM +, Zhang, Yang Z wrote:
Zhang, Yang Z wrote on 2012-12-06:
Marcelo Tosatti wrote on 2012-12-06:
On Mon, Dec 03, 2012 at 03:01:03PM +0800, Yang Zhang wrote:
Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
On 12/04/2012 01:26 AM, Marcelo Tosatti wrote:
On Wed, Nov 28, 2012 at 10:40:56AM +0530, Raghavendra K T wrote:
On 11/28/2012 06:42 AM, Marcelo Tosatti wrote:
Don't understand the reasoning behind why 3 is a good choice.
Here is where I came from. (explaining from scratch for
completeness,
On Thu, Dec 06, 2012 at 02:55:16AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 01:51:36PM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 06:02:59AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on
On Tue, Dec 04, 2012 at 07:17:11AM +0800, Xiao Guangrong wrote:
There are two cases we need to adjust page size in set_spte:
1): the one is other vcpu creates new sp in the window between mapping_level()
and acquiring mmu-lock.
2): the another case is the new sp is created by itself
Gleb Natapov wrote on 2012-12-06:
On Thu, Dec 06, 2012 at 02:55:16AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 01:51:36PM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 06:02:59AM +, Zhang, Yang Z wrote:
On Thu, Dec 06, 2012 at 07:16:07AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-06:
On Thu, Dec 06, 2012 at 02:55:16AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 01:51:36PM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on
Gleb Natapov wrote on 2012-12-06:
On Thu, Dec 06, 2012 at 07:16:07AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-06:
On Thu, Dec 06, 2012 at 02:55:16AM +, Zhang, Yang Z wrote:
Gleb Natapov wrote on 2012-12-05:
On Wed, Dec 05, 2012 at 01:51:36PM +, Zhang, Yang Z wrote:
Hi Marcelo / Gleb,
This is my current patch queue for ppc. Please pull.
Major changes this time around include:
- Book3S PR: Multiple fixes for POWER7 hosts
- Book3S HV: Prepare for full state exposure (live migration)
- Add eventfd support
- BookE: Add final bits for 64bit BookE
The current eventfd code assumes that when we have eventfd, we also have
irqfd for in-kernel interrupt delivery. This is not necessarily true. On
PPC we don't have an in-kernel irqchip yet, but we can still support easily
support eventfd.
Signed-off-by: Alexander Graf ag...@suse.de
---
From: Paul Mackerras pau...@samba.org
This uses a bit in our record of the guest view of the HPTE to record
when the HPTE gets modified. We use a reserved bit for this, and ensure
that this bit is always cleared in HPTE values returned to the guest.
The recording of modified HPTEs is only done
From: Michael Ellerman mich...@ellerman.id.au
Signed-off-by: Michael Ellerman mich...@ellerman.id.au
Signed-off-by: Alexander Graf ag...@suse.de
---
MAINTAINERS |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4376c52..7034467 100644
---
From: Mihai Caraman mihai.cara...@freescale.com
Extend MAS2 EPN mask to retain most significant bits on 64-bit hosts.
Use this mask in tlb effective address accessor.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
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