Re: [PATCH 04/12] KVM: x86: Replace call-back set_tsc_khz() with a common function

On Mon, Sep 28, 2015 at 08:27:02PM -0700, Eric Northup wrote: > On Sun, Sep 27, 2015 at 10:38 PM, Haozhong Zhang > wrote: > > > Both VMX and SVM propagate virtual_tsc_khz in the same way, so this > > patch removes the call-back set_tsc_khz() and replaces it with a

Re: [PATCH v4 15/15] KVM: arm: enable trapping of all debug registers

On 2015/9/3 0:08, Christoffer Dall wrote: > On Mon, Aug 10, 2015 at 09:26:07PM +0800, Zhichao Huang wrote: >> Enable trapping of the debug registers unconditionally, allowing guests to >> use the debug infrastructure. >> >> Signed-off-by: Zhichao Huang >> Reviewed-by:

Re: [PATCH v4 13/15] KVM: arm: keep track of guest use of the debug registers

On 2015/9/3 0:01, Christoffer Dall wrote: > On Mon, Aug 10, 2015 at 09:26:05PM +0800, Zhichao Huang wrote: >> >> -static bool trap_debug32(struct kvm_vcpu *vcpu, >> +/* Indicate whether the guest has enabled any break/watch points or not. */ >> +static bool guest_debug_in_use(struct kvm_vcpu

Re: [PATCH 01/12] KVM: x86: Collect information for setting TSC scaling ratio

On Sun, Sep 27, 2015 at 10:38 PM, Haozhong Zhang wrote: > > The number of bits of the fractional part of the 64-bit TSC scaling > ratio in VMX and SVM is different. This patch makes the architecture > code to collect the number of fractional bits and other related >

Re: [PATCH 00/12] KVM: x86: add support for VMX TSC scaling

On Sun, Sep 27, 2015 at 10:37 PM, Haozhong Zhang wrote: > This patchset adds support for VMX TSC scaling feature which is > available on Intel Skylake CPU. The specification of VMX TSC scaling > can be found at >

Re: [PATCH v4 10/15] KVM: arm: implement world switch for debug registers

On 2015/9/2 22:53, Christoffer Dall wrote: >> +/* Reads cp14 registers from hardware. >> + * Writes cp14 registers in-order to the CP14 struct pointed to by r10 >> + * >> + * Assumes vcpu pointer in vcpu reg >> + * >> + * Clobbers r2-r12 >> + */ >> +.macro save_debug_state >> +

Re: [PATCH 3/3] kvm-all: notice KVM of vcpu's TSC rate after migration

On Mon, Sep 28, 2015 at 01:37:34PM -0300, Eduardo Habkost wrote: > On Mon, Sep 28, 2015 at 01:38:31PM +0800, Haozhong Zhang wrote: > > When a vcpu is created in KVM, its TSC rate is initially identical to > > the host TSC rate. If its state is migrated to a vcpu on another > > machine (target

Re: [PATCH 01/12] KVM: x86: Collect information for setting TSC scaling ratio

On Mon, Sep 28, 2015 at 08:28:57PM -0700, Eric Northup wrote: > On Sun, Sep 27, 2015 at 10:38 PM, Haozhong Zhang > wrote: > > > > The number of bits of the fractional part of the 64-bit TSC scaling > > ratio in VMX and SVM is different. This patch makes the architecture

Re: [PATCH v4 01/15] KVM: arm: plug guest debug exploit

On 2015/9/2 19:38, Christoffer Dall wrote: > > I really think that we should read the register, clear the bits you care > about (MDBGen and HDBGen) and then write back the register. > > So, if I recall correctly, this is to avoid having to set HDCR_TDE > below? > > Given Will's concerns about

Re: [PATCH 00/12] KVM: x86: add support for VMX TSC scaling

On Mon, Sep 28, 2015 at 09:00:39PM -0700, Eric Northup wrote: > On Sun, Sep 27, 2015 at 10:37 PM, Haozhong Zhang > wrote: > > This patchset adds support for VMX TSC scaling feature which is > > available on Intel Skylake CPU. The specification of VMX TSC scaling > > can

Re: [PATCH 06/12] KVM: x86: Move TSC scaling logic out of call-back adjust_tsc_offset()

On 28/09/2015 07:38, Haozhong Zhang wrote: > + > +static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, > +s64 adjustment) > +{ > + kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, false); > +} > + > +static inline void

Re: [PATCH 03/12] KVM: x86: Add a common TSC scaling function

On 28/09/2015 07:38, Haozhong Zhang wrote: > > -static u64 __scale_tsc(u64 ratio, u64 tsc) > -{ > - u64 mult, frac, _tsc; > - > - mult = ratio >> 32; > - frac = ratio & ((1ULL << 32) - 1); > - > - _tsc = tsc; > - _tsc *= mult; > - _tsc += (tsc >> 32) * frac; > -

Re: [PATCH 3/3] kvm-all: notice KVM of vcpu's TSC rate after migration

On Mon, Sep 28, 2015 at 01:38:31PM +0800, Haozhong Zhang wrote: > When a vcpu is created in KVM, its TSC rate is initially identical to > the host TSC rate. If its state is migrated to a vcpu on another > machine (target machine) which may uses a different host TSC rate, QEMU > on the target

Re: [PATCH][v2] KVM: PPC: e500: Emulate TMCFG0 TMRN register

On Fri, 2015-09-25 at 18:02 +0300, Laurentiu Tudor wrote: > Emulate TMCFG0 TMRN register exposing one HW thread per vcpu. > > Signed-off-by: Mihai Caraman > [laurentiu.tu...@freescale.com: rebased on latest kernel, use > define instead of hardcoded value, moved code

Re: [PATCH][v2] KVM: PPC: e500: Emulate TMCFG0 TMRN register

On Fri, 2015-09-25 at 18:02 +0300, Laurentiu Tudor wrote: > Emulate TMCFG0 TMRN register exposing one HW thread per vcpu. > > Signed-off-by: Mihai Caraman > [laurentiu.tu...@freescale.com: rebased on latest kernel, use > define instead of hardcoded value, moved code

Re: [PATCH 2/3] target-i386: initialize vcpu's TSC rate to the value from KVM

On Mon, Sep 28, 2015 at 01:38:30PM +0800, Haozhong Zhang wrote: > When creating a vcpu, we initialize its TSC rate to the value from > KVM (through ioctl KVM_GET_TSC_KHZ). > > Signed-off-by: Haozhong Zhang > --- > target-i386/kvm.c | 7 +++ > 1 file changed, 7

RE: [PATCH v3 5/5] KVM: arm64: Implement vGICv3 CPU interface access

Hello! > So: sorry for the noise, you can just go ahead with that native 64-bit > sysregs encoding for [SG]ET_ONE_REG as you had before. Ok, good. Take v4 then. Some issues you've commented on were fixed, some other things were left as they are (i replied to your comments, why). Let's move

Re: [PATCH 1/2] x86: kvmclock: abolish PVCLOCK_COUNTS_FROM_ZERO

On 18/09/2015 17:54, Radim Krčmář wrote: > + kvm_sched_clock_offset = kvm_clock_read(); > + pv_time_ops.sched_clock = kvm_sched_clock_read; > + set_sched_clock_stable(); > + > + printk("kvm-clock: using sched offset of %llu cycles\n", Ok to change this to KERN_DEBUG or

[PATCH v4 0/7] KVM: arm64: Implement API for vGICv3 live migration

This patchset adds necessary userspace API in order to support vGICv3 live migration. GICv3 registers are accessed using device attribute ioctls, similar to GICv2. v3 => v4: - Split pure refactoring from anything else - Documentation brought up to date - Cleaned up 'mmio' structure usage in

[PATCH v4 1/7] KVM: arm/arm64: Move endianness conversion out of vgic_attr_regs_access()

mmio_data_read() and mmio_data_write(), originally used in this function, are limited only to 32 bits. We are going to refactor this code and eventually let it do 64-bit I/O for vGICv3. Therefore, our first step is to get rid of this limitation. We open up these inlines, which consist of

[PATCH v4 7/7] Implement vGICv3 CPU interface access

The access is done similar to GICv2, using KVM_DEV_ARM_VGIC_GRP_CPU_REGS group, however attribute ID encodes corresponding system register. Access size is always 64 bits. Since CPU interface state actually affects only a single vCPU, no vGIC locking is done. Just made sure that the vCPU is not

[PATCH v4 2/7] KVM: arm/arm64: Refactor vGIC attributes handling code

Separate all implementation-independent code in vgic_attr_regs_access() and move it to vgic.c. This will allow to reuse this code for vGICv3 implementation. Signed-off-by: Pavel Fedin --- virt/kvm/arm/vgic-v2-emul.c | 118 +---

[PATCH v4 5/7] KVM: arm64: Refactor system register handlers

Replace Rt with data pointer in struct sys_reg_params. This will allow to reuse system register handling code in implementation of vGICv3 CPU interface access API. Additionally, got rid of "massive hack" in kvm_handle_cp_64(). Signed-off-by: Pavel Fedin ---

[PATCH v4 6/7] KVM: arm64: Introduce find_reg_by_id()

In order to implement vGICv3 CPU interface access, we will need to perform table lookup of system registers. We would need both index_to_params() and find_reg() exported for that purpose, but instead we export a single function which combines them both. Signed-off-by: Pavel Fedin

[PATCH v4 4/7] KVM: arm64: Implement vGICv3 distributor and redistributor access from userspace

The access is done similar to vGICv2, using KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls. Since GICv3 can handle large number of CPUs, KVM_DEV_ARM_VGIC_CPUID_MASK has been extended to 20 bits. This is enough for 1048576

[PATCH v4 3/7] KVM: arm/arm64: Fix the documentation

During refactoring we noticed some mistakes in the documentation. Correct them. Signed-off-by: Pavel Fedin --- Documentation/virtual/kvm/devices/arm-vgic.txt | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git

Re: [PATCH v3 4/4] scsi: provide UAPI version of scsi/sg.h and scsi/scsi_ioctl.h

Hi Paolo, [auto build test results on v4.3-rc2 -- if it's inappropriate base, please ignore] config: i386-randconfig-a0-201538 (attached as .config) reproduce: git checkout d88f2083643f6dfacba14b2e95217dc6e0a4be37 # save the attached .config to linux build tree make ARCH=i386 All

Re: [PATCH v3 2/4] scsi: cleanup scsi/scsi_ioctl.h

On 15-09-25 11:27 AM, Paolo Bonzini wrote: SCSI_REMOVAL_* goes together with other SCSI command constants in include/scsi/scsi.h. It is also used outside the implementation of the ioctls (and it is not part of the user API). scsi_fctargaddress/Scsi_FCTargAddress has had no in-tree use since

Re: [PATCH v3 1/4] scsi: remove old-style type names from sg.h

On 15-09-25 11:27 AM, Paolo Bonzini wrote: These will not be exported by the new linux/sg.h header, and scsi/sg.h will not have any user API after linux/sg.h is created. Since they have no user in the kernel, they can be zapped. Cc: James Bottomley Cc: Christoph

Re: [PATCH v3 4/4] scsi: provide UAPI version of scsi/sg.h and scsi/scsi_ioctl.h

On 15-09-25 11:27 AM, Paolo Bonzini wrote: Provide a UAPI version of the header in the kernel, making it easier for interested projects to use an up-to-date version of the header. The new headers are placed under uapi/linux/ so as not to conflict with the glibc-provided headers in

Re: [PATCH v3 3/4] scsi: move all obsolete ioctls to scsi_ioctl.h

On 15-09-25 11:27 AM, Paolo Bonzini wrote: Some are in scsi.h. Keep them together in preparation for exposing them in UAPI headers. Cc: James Bottomley Cc: Christoph Hellwig Cc: linux-s...@vger.kernel.org Reviewed-by: Bart Van Assche

Re: [PATCH] x86: Use entire page for the per-cpu GDT only if paravirt-enabled

* Denys Vlasenko wrote: > On 09/26/2015 09:50 PM, H. Peter Anvin wrote: > > NAK. We really should map the GDT read-only on all 64 bit systems, > > since we can't hide the address from SLDT. Same with the IDT. > > Sorry, I don't understand your point. So the problem is

Re: [RFC PATCH 0/2] kvmclock: fix ABI breakage from PVCLOCK_COUNTS_FROM_ZERO.

On 18/09/2015 17:54, Radim Krčmář wrote: > This patch series will be disabling PVCLOCK_COUNTS_FROM_ZERO flag and is > RFC because I haven't explored many potential problems or tested it. > > [1/2] uses a different algorithm in the guest to start counting from 0. > [2/2] stops exposing

[kvm:queue 20/31] arch/x86/kvm/vmx.c:2502:78: warning: left shift count >= width of type

tree: https://git.kernel.org/pub/scm/virt/kvm/kvm.git queue head: 0e67722dd743e8218b4fc7924a1ab4ffda781517 commit: 8de182e8f597f4ec81a6fca865fb709c0753ca53 [20/31] KVM: nVMX: expose VPID capability to L1 config: i386-randconfig-x006-201539 (attached as .config) reproduce: git checkout

Re: [PATCH] KVM: nVMX: expose VPID capability to L1

On 24/09/2015 08:51, Wanpeng Li wrote: > /* >* For nested guests, we don't do anything specific >* for single context invalidation. Hence, only advertise >* support for global context invalidation. >*/ > -

Re: [RFC PATCH v3] os-android: Add support to android platform

On 24/09/2015 15:21, Houcheng Lin wrote: > +if [ "$android" = "yes" ] ; then > + LIBS="-lglib-2.0 -lgthread-2.0 -lz -lpixman-1 -lintl -liconv -lc $LIBS" > + libs_qga="-lglib-2.0 -lgthread-2.0 -lz -lpixman-1 -lintl -liconv -lc" > +fi This change should not be necessary. > +#define

custom screen resolution

Hi There, I'm running Android-x86 on KVM and I need to set a custom screen resolution like 480x800. It's not a standard resolution in vga. Is there a way to do it? Thanks in advance! Jason -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to

RE: [PATCH v9 00/18] Add VT-d Posted-Interrupts support - including prerequisite series

> -Original Message- > From: Paolo Bonzini [mailto:pbonz...@redhat.com] > Sent: Friday, September 25, 2015 7:15 PM > To: Wu, Feng; alex.william...@redhat.com; j...@8bytes.org; > mtosa...@redhat.com > Cc: eric.au...@linaro.org; kvm@vger.kernel.org; > io...@lists.linux-foundation.org;

[FYI PATCH 19/20] KVM: nVMX: nested VPID emulation

From: Wanpeng Li VPID is used to tag address space and avoid a TLB flush. Currently L0 use the same VPID to run L1 and all its guests. KVM flushes VPID when switching between L1 and L2. This patch advertises VPID to the L1 hypervisor, then address space of L1 and L2 can

[FYI PATCH 20/20] KVM: vmx: disable posted interrupts if no local APIC

Uniprocessor 32-bit randconfigs can disable the local APIC, and posted interrupts require reserving a vector on the LAPIC, so they are incompatible. Signed-off-by: Paolo Bonzini --- arch/x86/kvm/vmx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

[FYI PATCH 04/20] KVM: x86: introduce lapic_in_kernel

Avoid pointer chasing and memory barriers, and simplify the code when split irqchip (LAPIC in kernel, IOAPIC/PIC in userspace) is introduced. Signed-off-by: Paolo Bonzini --- arch/x86/kvm/irq.c | 6 +++--- arch/x86/kvm/irq.h | 8 arch/x86/kvm/lapic.c | 4

[FYI PATCH 00/20] kvm/queue will be merged soon to kvm/next

Hi all, these are the patches that will be merged Real Soon Now(tm) to kvm/next. Since all of them have been lying around for a while, I am sending them out again for everyone's information. Thanks, Paolo Andrey Smetanin (3): kvm/x86: Hyper-V HV_X64_MSR_RESET msr kvm/x86: Hyper-V

[FYI PATCH 01/20] KVM: x86: set TMR when the interrupt is accepted

Do not compute TMR in advance. Instead, set the TMR just before the interrupt is accepted into the IRR. This limits the coupling between IOAPIC and LAPIC. Signed-off-by: Paolo Bonzini --- arch/x86/kvm/ioapic.c | 9 ++--- arch/x86/kvm/ioapic.h | 3 +--

Re: [PATCH v9 00/18] Add VT-d Posted-Interrupts support - including prerequisite series

On 28/09/2015 12:14, Wu, Feng wrote: > Thanks a lot for creating branch for vt-d pi. However, I cannot launch guests > with this tree. I encountered the following kernel dump, and I find that the > problematic commit is " 2260b1cde0b5472ab70ad0764b10095372e41913 " > > KVM: x86: put

[PATCH] x86: x2apic: make stub functions available even if !CONFIG_X86_LOCAL_APIC

Some CONFIG_X86_X2APIC functions, especially x2apic_enabled(), are not declared if !CONFIG_X86_LOCAL_APIC. However, the same stubs that work for !CONFIG_X86_X2APIC are okay even if there is no local APIC support at all. Avoid the introduction of #ifdefs by moving the x2apic declarations

[FYI PATCH 13/20] kvm/x86: Hyper-V HV_X64_MSR_RESET msr

From: Andrey Smetanin HV_X64_MSR_RESET msr is used by Hyper-V based Windows guest to reset guest VM by hypervisor. Necessary to support loading of winhv.sys in guest, which in turn is required to support Windows VMBus. Signed-off-by: Andrey Smetanin

[FYI PATCH 16/20] KVM: VMX: adjust interface to allocate/free_vpid

From: Wanpeng Li Adjust allocate/free_vid so that they can be reused for the nested vpid. Signed-off-by: Wanpeng Li Signed-off-by: Paolo Bonzini --- arch/x86/kvm/vmx.c | 25 - 1 file changed, 12

[FYI PATCH 18/20] KVM: nVMX: emulate the INVVPID instruction

From: Wanpeng Li Add the INVVPID instruction emulation. Reviewed-by: Wincy Van Signed-off-by: Wanpeng Li Signed-off-by: Paolo Bonzini --- arch/x86/include/asm/vmx.h | 1 + arch/x86/kvm/vmx.c

[FYI PATCH 15/20] kvm/x86: Hyper-V HV_X64_MSR_VP_RUNTIME support

From: Andrey Smetanin HV_X64_MSR_VP_RUNTIME msr used by guest to get "the time the virtual processor consumes running guest code, and the time the associated logical processor spends running hypervisor code on behalf of that guest." Calculation of this time is performed

[FYI PATCH 17/20] KVM: VMX: introduce __vmx_flush_tlb to handle specific vpid

From: Wanpeng Li Introduce __vmx_flush_tlb() to handle specific vpid. Signed-off-by: Wanpeng Li Signed-off-by: Paolo Bonzini --- arch/x86/kvm/vmx.c | 21 + 1 file changed, 13 insertions(+), 8

[FYI PATCH 12/20] kvm: add capability for any-length ioeventfds

From: Jason Wang Cc: Gleb Natapov Cc: Paolo Bonzini Signed-off-by: Jason Wang Signed-off-by: Paolo Bonzini --- Documentation/virtual/kvm/api.txt | 6 +- include/uapi/linux/kvm.h

[FYI PATCH 14/20] kvm/x86: Hyper-V HV_X64_MSR_VP_INDEX export for QEMU.

From: Andrey Smetanin Insert Hyper-V HV_X64_MSR_VP_INDEX into msr's emulated list, so QEMU can set Hyper-V features cpuid HV_X64_MSR_VP_INDEX_AVAILABLE bit correctly. KVM emulation part is in place already. Necessary to support loading of winhv.sys in guest, which in

[FYI PATCH 08/20] KVM: x86: Add EOI exit bitmap inference

From: Steve Rutherford In order to support a userspace IOAPIC interacting with an in kernel APIC, the EOI exit bitmaps need to be configurable. If the IOAPIC is in userspace (i.e. the irqchip has been split), the EOI exit bitmaps will be set whenever the GSI Routes are

[FYI PATCH 09/20] KVM: x86: Add support for local interrupt requests from userspace

From: Steve Rutherford In order to enable userspace PIC support, the userspace PIC needs to be able to inject local interrupts even when the APICs are in the kernel. KVM_INTERRUPT now supports sending local interrupts to an APIC when APICs are in the kernel. The

[FYI PATCH 11/20] kvm: add tracepoint for fast mmio

From: Jason Wang Cc: Gleb Natapov Cc: Paolo Bonzini Signed-off-by: Jason Wang Signed-off-by: Paolo Bonzini --- arch/x86/kvm/trace.h | 18 ++ arch/x86/kvm/vmx.c | 1 +

Re: [Qemu-devel] [PATCH 3/3] Target-ppc: Remove unnecessary variable

On 26/09/2015 18:15, Eric Blake wrote: > On 09/25/2015 02:37 AM, Shraddha Barke wrote: >> Compress lines and remove the variable. >> > >> +++ b/target-ppc/kvm.c >> @@ -1782,8 +1782,7 @@ uint32_t kvmppc_get_tbfreq(void) >> >> ns++; >> >> -retval = atoi(ns); >> -return retval; >>

RE: [PATCH v9 00/18] Add VT-d Posted-Interrupts support - including prerequisite series

> -Original Message- > From: Paolo Bonzini [mailto:pbonz...@redhat.com] > Sent: Monday, September 28, 2015 6:19 PM > To: Wu, Feng; alex.william...@redhat.com; j...@8bytes.org; > mtosa...@redhat.com > Cc: eric.au...@linaro.org; kvm@vger.kernel.org; > io...@lists.linux-foundation.org;

[FYI PATCH 07/20] KVM: x86: Add KVM exit for IOAPIC EOIs

From: Steve Rutherford Adds KVM_EXIT_IOAPIC_EOI which allows the kernel to EOI level-triggered IOAPIC interrupts. Uses a per VCPU exit bitmap to decide whether or not the IOAPIC needs to be informed (which is identical to the EOI_EXIT_BITMAP field used by modern x86

[FYI PATCH 06/20] KVM: x86: Split the APIC from the rest of IRQCHIP.

From: Steve Rutherford First patch in a series which enables the relocation of the PIC/IOAPIC to userspace. Adds capability KVM_CAP_SPLIT_IRQCHIP; KVM_CAP_SPLIT_IRQCHIP enables the construction of LAPICs without the rest of the irqchip. Compile tested for x86.

[FYI PATCH 05/20] KVM: x86: unify handling of interrupt window

The interrupt window is currently checked twice, once in vmx.c/svm.c and once in dm_request_for_irq_injection. The only difference is the extra check for kvm_arch_interrupt_allowed in dm_request_for_irq_injection, and the different return value (EINTR/KVM_EXIT_INTR for vmx.c/svm.c vs.

[FYI PATCH 02/20] KVM: x86: store IOAPIC-handled vectors in each VCPU

We can reuse the algorithm that computes the EOI exit bitmap to figure out which vectors are handled by the IOAPIC. The only difference between the two is for edge-triggered interrupts other than IRQ8 that have no notifiers active; however, the IOAPIC does not have to do anything special for

[FYI PATCH 03/20] KVM: x86: replace vm_has_apicv hook with cpu_uses_apicv

This will avoid an unnecessary trip to ->kvm and from there to the VPIC. Signed-off-by: Paolo Bonzini --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/irq.c | 2 +- arch/x86/kvm/lapic.c| 4 ++-- arch/x86/kvm/lapic.h| 4 ++--

Re: [PATCH 2/3] target-i386: initialize vcpu's TSC rate to the value from KVM

On Tue, Sep 29, 2015 at 09:23:39AM +0800, Haozhong Zhang wrote: > On Mon, Sep 28, 2015 at 01:17:44PM -0300, Eduardo Habkost wrote: > > On Mon, Sep 28, 2015 at 01:38:30PM +0800, Haozhong Zhang wrote: > > > When creating a vcpu, we initialize its TSC rate to the value from > > > KVM (through ioctl

Re: [PATCH 06/12] KVM: x86: Move TSC scaling logic out of call-back adjust_tsc_offset()

On Mon, Sep 28, 2015 at 10:14:19PM +0200, Paolo Bonzini wrote: > > > On 28/09/2015 07:38, Haozhong Zhang wrote: > > + > > +static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, > > + s64 adjustment) > > +{ > > +

Re: [PATCH 03/12] KVM: x86: Add a common TSC scaling function

On Mon, Sep 28, 2015 at 10:12:37PM +0200, Paolo Bonzini wrote: > > > On 28/09/2015 07:38, Haozhong Zhang wrote: > > > > -static u64 __scale_tsc(u64 ratio, u64 tsc) > > -{ > > - u64 mult, frac, _tsc; > > - > > - mult = ratio >> 32; > > - frac = ratio & ((1ULL << 32) - 1); > > - > > -

Re: [PATCH] KVM: nVMX: expose VPID capability to L1

On 9/28/15 8:05 PM, Paolo Bonzini wrote: On 24/09/2015 08:51, Wanpeng Li wrote: /* * For nested guests, we don't do anything specific * for single context invalidation. Hence, only advertise * support for global context

Re: [PATCH 2/3] target-i386: initialize vcpu's TSC rate to the value from KVM

On Mon, Sep 28, 2015 at 01:17:44PM -0300, Eduardo Habkost wrote: > On Mon, Sep 28, 2015 at 01:38:30PM +0800, Haozhong Zhang wrote: > > When creating a vcpu, we initialize its TSC rate to the value from > > KVM (through ioctl KVM_GET_TSC_KHZ). > > > > Signed-off-by: Haozhong Zhang

Re: [PATCH] x86: Use entire page for the per-cpu GDT only if paravirt-enabled

On 09/28/2015 09:58 AM, Ingo Molnar wrote: > > * Denys Vlasenko wrote: > >> On 09/26/2015 09:50 PM, H. Peter Anvin wrote: >>> NAK. We really should map the GDT read-only on all 64 bit systems, >>> since we can't hide the address from SLDT. Same with the IDT. >> >> Sorry,