From 5854070994c5002b3a37577165ed3e82f36f712d Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Sat, 8 Mar 2014 04:40:02 +0800
Subject: [PATCH] KVM: x86: Work around buggy MPX platform
Work around buggy MPX platform which support MSR_IA32_BNDCFGS
but has issue at, say, VMX
From 3a7783cd9a0556787809d3d5ecb5f2b85dd9fc02 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Mon, 3 Mar 2014 18:56:39 +0800
Subject: [PATCH] target-i386: bugfix of Intel MPX
The correct size of cpuid 0x0d sub-leaf 4 is 0x40, not 0x10.
This is confirmed by Anvin H Peter
Liu, Jinsong wrote:
Paolo Bonzini wrote:
Il 21/02/2014 18:57, Liu, Jinsong ha scritto:
- F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | F(RDSEED) |
+ F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | F(MPX) | F(RDSEED) |
F(ADX);
MPX also needs to be conditional
patch
* Add a new kvm_x86_ops member mpx_supported, to disable MPX whenever the two
VMX controls are not available
* minor rebase for VMX bit definition
Version 5:
* Add conditional mpx_supported when expose MPX to guest
Thanks,
Jinsong
Liu Jinsong (3):
KVM: x86: Intel MPX vmx and msr
From caddc009a6d2019034af8f2346b2fd37a81608d0 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Mon, 24 Feb 2014 18:11:11 +0800
Subject: [PATCH v5 1/3] KVM: x86: Intel MPX vmx and msr handle
This patch handle vmx and msr of Intel MPX feature.
Signed-off-by: Xudong Hao xudong
From 5d5a80cd172ea6fb51786369bcc23356b1e9e956 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Mon, 24 Feb 2014 18:11:55 +0800
Subject: [PATCH v5 2/3] KVM: x86: add MSR_IA32_BNDCFGS to msrs_to_save
Add MSR_IA32_BNDCFGS to msrs_to_save, and corresponding logic
to kvm_get
From 44c2abca2c2eadc6f2f752b66de4acc8131880c4 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Mon, 24 Feb 2014 18:12:31 +0800
Subject: [PATCH v5 3/3] KVM: x86: Enable Intel MPX for guest
This patch enable Intel MPX feature to guest.
Signed-off-by: Xudong Hao xudong
Paolo Bonzini wrote:
Il 24/02/2014 11:58, Liu, Jinsong ha scritto:
@@ -599,6 +599,9 @@ int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32
index, u64 xcr) u64 old_xcr0 = vcpu-arch.xcr0;
u64 valid_bits;
+if (!kvm_x86_ops-mpx_supported || !kvm_x86_ops-mpx_supported
Paolo Bonzini wrote:
Il 21/02/2014 18:57, Liu, Jinsong ha scritto:
-F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | F(RDSEED) |
+F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | F(MPX) | F(RDSEED) |
F(ADX);
MPX also needs to be conditional on mpx_supported here, like
From 24ffdce9efebf13c6ed4882f714b2b57ef1141eb Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Thu, 20 Feb 2014 17:38:26 +0800
Subject: [PATCH] KVM: x86: expose new instruction RDSEED to guest
RDSEED instruction return a random number, which supplied by a
cryptographically
From 0750e335eb5860b0b483e217e8a08bd743cbba16 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Thu, 20 Feb 2014 17:39:32 +0800
Subject: [PATCH] KVM: x86: expose ADX feature to guest
ADCX and ADOX instructions perform an unsigned addition with Carry flag and
Overflow flag
From 00c920c96127d20d4c3bb790082700ae375c39a0 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 21 Feb 2014 23:47:18 +0800
Subject: [PATCH] KVM: x86: Fix xsave cpuid exposing bug
EBX of cpuid(0xD, 0) is dynamic per XCR0 features enable/disable.
Bit 63 of XCR0 is reserved
These patches are version 4 to enable Intel MPX for KVM.
Version 1:
* Add some Intel MPX definiation
* Fix a cpuid(0x0d, 0) exposing bug, dynamic per XCR0 features enable/disable
* vmx and msr handle for MPX support at KVM
* enalbe MPX feature for guest
Version 2:
* remove generic MPX
From eb56f19c14d5603209b22b97cd53ef1716bf2804 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Sat, 22 Feb 2014 07:53:32 +0800
Subject: [PATCH v4 1/3] KVM: x86: Intel MPX vmx and msr handle
This patch handle vmx and msr of Intel MPX feature.
Signed-off-by: Xudong Hao xudong
From 7d1b41c3fdf71e4c73280e117948102f54f74be7 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Sat, 22 Feb 2014 08:10:17 +0800
Subject: [PATCH v4 2/3] KVM: x86: add MSR_IA32_BNDCFGS to msrs_to_save
Add MSR_IA32_BNDCFGS to msrs_to_save, and corresponding logic
to kvm_get
From 8b3a3b1f08c166e0c2cdc6162e6fa95d9c7ad2ec Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Sat, 22 Feb 2014 08:53:27 +0800
Subject: [PATCH v4 3/3] KVM: x86: Enable Intel MPX for guest
This patch enable Intel MPX feature to guest.
Signed-off-by: Xudong Hao xudong
Paolo Bonzini wrote:
Il 22/01/2014 13:03, Paolo Bonzini ha scritto:
Il 22/01/2014 06:29, Liu, Jinsong ha scritto:
These patches are version 3 to enalbe Intel MPX for KVM.
Version 1:
* Add some Intel MPX definiation
* Fix a cpuid(0x0d, 0) exposing bug, dynamic per XCR0 features
enable
Paolo Bonzini wrote:
Il 22/01/2014 13:03, Paolo Bonzini ha scritto:
Il 22/01/2014 06:29, Liu, Jinsong ha scritto:
These patches are version 3 to enalbe Intel MPX for KVM.
Version 1:
* Add some Intel MPX definiation
* Fix a cpuid(0x0d, 0) exposing bug, dynamic per XCR0 features
enable
Paolo Bonzini wrote:
Il 12/12/2013 12:09, Liu, Jinsong ha scritto:
Paolo Bonzini wrote:
Il 12/12/2013 06:47, Liu, Jinsong ha scritto:
Paolo Bonzini wrote:
Il 11/12/2013 09:31, Liu, Jinsong ha scritto:
Paolo, comments for version 2?
I think I commented that it's fine, I'm just waiting
Paolo Bonzini wrote:
Il 21/01/2014 16:25, Liu, Jinsong ha scritto:
Hmm? I remember I have sent out the rebased patches v3 last month
If you didn't receive them I'm OK to rebase and resend them. BTW,
what's the review remarks? I remember you commented that the patches
are fine. Any
From 3155a190ce6ebb213e6c724240f4e6620ba67a9d Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 13 Dec 2013 02:32:03 +0800
Subject: [PATCH v3 1/4] KVM/X86: Fix xsave cpuid exposing bug
EBX of cpuid(0xD, 0) is dynamic per XCR0 features enable/disable.
Bit 63 of XCR0
From c2b3b4347b4c8b0aa6b5e97c161fd4d34b0ef4d3 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 13 Dec 2013 02:34:48 +0800
Subject: [PATCH v3 4/4] KVM/X86: Enable Intel MPX for guest.
This patch enable Intel MPX feature to guest.
Signed-off-by: Xudong Hao xudong
From 31e68d752ac395dc6b65e6adf45be5324e92cdc8 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 13 Dec 2013 02:32:43 +0800
Subject: [PATCH v3 2/4] KVM/X86: Intel MPX vmx and msr handle
This patch handle vmx and msr of Intel MPX feature.
Signed-off-by: Xudong Hao xudong
From d1992769911f34cb319fe638d32ae604bd2a6ce8 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 13 Dec 2013 02:33:08 +0800
Subject: [PATCH v3 3/4] KVM/X86: add MSR_IA32_BNDCFGS to msrs_to_save
Add MSR_IA32_BNDCFGS to msrs_to_save, and corresponding logic
to kvm_get
These patches are version 3 to enalbe Intel MPX for KVM.
Version 1:
* Add some Intel MPX definiation
* Fix a cpuid(0x0d, 0) exposing bug, dynamic per XCR0 features enable/disable
* vmx and msr handle for MPX support at KVM
* enalbe MPX feature for guest
Version 2:
* remove generic MPX
Paolo Bonzini wrote:
Il 12/12/2013 06:47, Liu, Jinsong ha scritto:
Paolo Bonzini wrote:
Il 11/12/2013 09:31, Liu, Jinsong ha scritto:
Paolo, comments for version 2?
I think I commented that it's fine, I'm just waiting for a rebase
on top of the generic patches.
Paolo
Thanks
Paolo, comments for version 2?
Thanks,
Jinsong
Liu, Jinsong wrote:
These patches are version 2 to enalbe Intel MPX for KVM.
Version 1:
* Add some Intel MPX definiation
* Fix a cpuid(0x0d, 0) exposing bug, dynamic per XCR0 features
enable/disable
* vmx and msr handle for MPX
Paolo Bonzini wrote:
Il 11/12/2013 09:31, Liu, Jinsong ha scritto:
Paolo, comments for version 2?
I think I commented that it's fine, I'm just waiting for a rebase on
top of the generic patches.
Paolo
Thanks! common MPX definiation patches have been checked in tip tree (both
Qiaowei
Intel has released Memory Protection Extensions (MPX) recently.
Please refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are version2 to support Intel MPX at qemu side.
Version 1:
* Fix cpuid leaf 0x0d bug which incorrectly parsed eax and ebx;
*
From ee8b72df3b5503514b748035e6b1cb4d61f8e701 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Thu, 5 Dec 2013 08:32:12 +0800
Subject: [PATCH v3 1/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4. It also
From 12fa3564b7342c4e034b13671dc922ff23ac4b1e Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Sat, 7 Dec 2013 05:18:35 +0800
Subject: [PATCH v3 2/2] target-i386: MSR_IA32_BNDCFGS handle
Signed-off-by: Liu Jinsong jinsong@intel.com
---
target-i386/cpu.h |3
Paolo Bonzini wrote:
Il 02/12/2013 17:46, Liu, Jinsong ha scritto:
From e9ba40b3d1820b8ab31431c73226ee3ed485edd1 Mon Sep 17 00:00:00
2001
From: Liu Jinsong jinsong@intel.com
Date: Tue, 3 Dec 2013 07:02:27 +0800
Subject: [PATCH 3/4] KVM/X86: Intel MPX vmx and msr handle
Signed-off
Eric Blake wrote:
On 12/06/2013 07:06 AM, Liu, Jinsong wrote:
Intel has released Memory Protection Extensions (MPX) recently.
Please refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are version2 to support Intel MPX at qemu side.
You still
Paolo Bonzini wrote:
Il 06/12/2013 15:06, Liu, Jinsong ha scritto:
Intel has released Memory Protection Extensions (MPX) recently.
Please refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are version2 to support Intel MPX at qemu side.
Version 1
Paolo Bonzini wrote:
Il 07/12/2013 01:20, Qiaowei Ren ha scritto:
This patch defines xstate feature and extends struct xsave_hdr_struct
to support Intel MPX.
Signed-off-by: Qiaowei Ren qiaowei@intel.com
Signed-off-by: Xudong Hao xudong@intel.com
Signed-off-by: Liu Jinsong jinsong
H. Peter Anvin wrote:
On 12/06/2013 12:05 PM, Liu, Jinsong wrote:
Since Peter already said the same, please undo these changes.
Also, how is XSTATE_EAGER used? Should MPX be disabled when
xsaveopt is disabled on the kernel command line? (Liu, how would
this affect the KVM patches, too
Paolo Bonzini wrote:
Il 04/12/2013 12:30, Liu, Jinsong ha scritto:
Almost there. Migration (vmstate) is still missing.
Like this:
==
From faead85c0dbe62da896e0ed9e165d98e10216968 Mon Sep 17 00:00:00
2001
From: Liu Jinsong jinsong@intel.com
Date: Wed, 4 Dec 2013
Almost there. Migration (vmstate) is still missing.
Like this:
==
From faead85c0dbe62da896e0ed9e165d98e10216968 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Wed, 4 Dec 2013 16:56:49 +0800
Subject: [PATCH 2/2] target-i386: Intel MPX
Add some MPX
Paolo Bonzini wrote:
Il 02/12/2013 17:42, Liu, Jinsong ha scritto:
From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00
2001 From: Liu Jinsong jinsong@intel.com
Date: Tue, 3 Dec 2013 05:08:19 +0800
Subject: [PATCH 2/2] target-i386: Intel MPX
Add some MPX related
Intel has released Memory Protection Extensions (MPX) recently.
Please refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are version2 to support Intel MPX at qemu side.
Version 1:
* Fix cpuid leaf 0x0d bug which incorrectly parsed eax and ebx;
*
From cb3b12dd9873929b3a03214e3aa0ee5297e75119 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Tue, 3 Dec 2013 04:17:50 +0800
Subject: [PATCH v2 1/2] target-i386: fix cpuid leaf 0x0d
Fix cpuid leaf 0x0d which incorrectly parsed eax and ebx.
However, before this patch
From 256484fd75d4eb4d248e5e0f493f16182da59dc2 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Wed, 4 Dec 2013 16:56:49 +0800
Subject: [PATCH v2 2/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4. It also
From 57751d87392d7ee9df5698bc83b356de654453ef Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Tue, 3 Dec 2013 04:17:50 +0800
Subject: [PATCH 1/2] target-i386: fix cpuid leaf 0x0d
Fix cpuid leaf 0x0d which incorrectly parsed eax and ebx.
However, before this patch the CPUID
From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Tue, 3 Dec 2013 05:08:19 +0800
Subject: [PATCH 2/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4.
Signed-off
From fbfa537f690eca139a96c6b2636ab5130bf57716 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 29 Nov 2013 01:27:00 +0800
Subject: [PATCH 1/4] X86: Intel MPX definiation
Signed-off-by: Xudong Hao xudong@intel.com
Signed-off-by: Liu Jinsong jinsong@intel.com
From 4a2eb0a8467b4f278e59d2df209a1bc03349d088 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Tue, 3 Dec 2013 06:28:20 +0800
Subject: [PATCH 2/4] KVM/X86: Fix xsave cpuid exposing bug
EBX of cpuid(0xD, 0) is dynamic per XCR0 features enable/disable.
Bit 63 of XCR0
From e9ba40b3d1820b8ab31431c73226ee3ed485edd1 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Tue, 3 Dec 2013 07:02:27 +0800
Subject: [PATCH 3/4] KVM/X86: Intel MPX vmx and msr handle
Signed-off-by: Xudong Hao xudong@intel.com
Signed-off-by: Liu Jinsong jinsong
From 62553aebb7b72f1203fefc59dd4d8969e4216ddb Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Tue, 3 Dec 2013 07:34:32 +0800
Subject: [PATCH 4/4] KVM/X86: Enable Intel MPX for guest
Signed-off-by: Xudong Hao xudong@intel.com
Signed-off-by: Liu Jinsong jinsong
Intel has released new version of Intel Architecture Instruction Set
Extensions Programming Reference, adding new features like AVX-512,
MPX, etc. Refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These 2 patches are prepare patches at qemu side to support Intel MPX
From e4b58c7bafc4d9f913a572a1b1cfee91c92f1637 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 22 Nov 2013 00:24:16 +0800
Subject: [PATCH 1/2] target-i386: fix cpuid leaf 0x0d
Fix cpuid leaf 0x0d which incorrectly parsed eax and ebx.
Signed-off-by: Liu Jinsong jinsong
).
Signed-off-by: Liu Jinsong jinsong@intel.com
---
target-i386/cpu.c | 34 ++
target-i386/cpu.h |1 +
2 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 544b57f..7d04f28 100644
--- a/target-i386/cpu.c
+++ b
Intel has released new version of Intel Architecture Instruction Set
Extensions Programming Reference, adding new features like AVX-512,
MPX, etc. Refer to
http://download-software.intel.com/sites/default/files/319433-015.pdf
These patches are to support Intel MPX for KVM.
PATCH 1/4 is some MPX
From 3a1a011100b38a275d8c95468c12c483e316bb15 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 29 Nov 2013 01:27:00 +0800
Subject: [PATCH 1/4] X86: Intel MPX definiation
Signed-off-by: Xudong Hao xudong@intel.com
Reviewed-by: Liu Jinsong jinsong@intel.com
From b060be65e466291c91963e58c4880ec614d0b294 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 29 Nov 2013 01:27:53 +0800
Subject: [PATCH 2/4] KVM/X86: Fix xsave cpuid exposing bug
EBX of cpuid(0xD, 0) is dynamic per XCR0 features enable/disable.
Bit 63 of XCR0
From 11ae33723027c7b8e53a8c109f127800d7f0ad6e Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 29 Nov 2013 01:28:19 +0800
Subject: [PATCH 3/4] KVM/X86: Enable Intel MPX for guest
Enable Intel Memory Protection Extension for guest.
Signed-off-by: Xudong Hao xudong
From 7532bdffe9f74db65f6eff733cb227a66bef932e Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Sat, 30 Nov 2013 00:27:02 +0800
Subject: [PATCH 4/4] KVM/X86: Intel MPX vmx and msr handle
Signed-off-by: Xudong Hao xudong@intel.com
Reviewed-by: Liu Jinsong jinsong
Paolo Bonzini wrote:
Il 29/11/2013 14:15, Liu, Jinsong ha scritto:
From e4b58c7bafc4d9f913a572a1b1cfee91c92f1637 Mon Sep 17 00:00:00
2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 22 Nov 2013 00:24:16 +0800
Subject: [PATCH 1/2] target-i386: fix cpuid leaf 0x0d
Fix cpuid leaf
Paolo Bonzini wrote:
Il 29/11/2013 14:17, Liu, Jinsong ha scritto:
From aac033473bc88befe39a9add99820c0a7118ac90 Mon Sep 17 00:00:00
2001
From: root root@ljs.(none)
Date: Fri, 22 Nov 2013 00:24:35 +0800
Subject: [PATCH 2/2] target-i386: Intel MPX support
Expose cpuid leaf (0xd, 3
Paolo Bonzini wrote:
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index a8ce117..e30d4ce 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -75,7 +75,7 @@ void kvm_update_cpuid(struct kvm_vcpu *vcpu)
(best-eax | ((u64)best-edx 32))
Paolo Bonzini wrote:
Il 19/08/2013 16:59, Andreas Färber ha scritto:
qemu-kvm is no longer maintained since 1.3 so it should not be
occurring any more.
Please use a prefix of target-i386: (the directory name) to signal
where you are changing code, i.e. x86 only.
bugfix is not a very
Paolo Bonzini wrote:
The patch looks good. Please repost it with checkpatch.pl failures
fixed.
Paolo
Thanks Stefan and Paolo! Updated patch attached.
Regards,
Jinsong
===
From a0ddf948d40e42de862543157a5668a1c12faae6 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong
Andreas Färber wrote:
Am 19.08.2013 16:31, schrieb Liu, Jinsong:
Paolo Bonzini wrote:
The patch looks good. Please repost it with checkpatch.pl failures
fixed.
Paolo
Thanks Stefan and Paolo! Updated patch attached.
Regards,
Jinsong
===
From
From 1273f8b2e5464ec987facf9942fd3ccc0b69087e Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Mon, 19 Aug 2013 09:33:30 +0800
Subject: [PATCH] qemu-kvm bugfix for IA32_FEATURE_CONTROL
This patch is to fix the bug https://bugs.launchpad.net/qemu-kvm/+bug/1207623
From 1273f8b2e5464ec987facf9942fd3ccc0b69087e Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Mon, 19 Aug 2013 09:33:30 +0800
Subject: [PATCH] qemu-kvm bugfix for IA32_FEATURE_CONTROL
This patch is to fix the bug https://bugs.launchpad.net/qemu-kvm/+bug/1207623
Hi,
I'm recently debugging a qemu-kvm issue. I add some print code like
'fprintf(stderr, ...)', however I fail to see any info at stdio. Anyone can
tell me where is qemu-kvm logfile, or, what I need do to record my fprintf info?
Thanks,
Jinsong--
To unsubscribe from this list: send the line
Avi Kivity wrote:
On 09/10/2012 01:44 PM, Liu, Jinsong wrote:
Hi,
I'm recently debugging a qemu-kvm issue. I add some print code like
'fprintf(stderr, ...)', however I fail to see any info at stdio.
Anyone can tell me where is qemu-kvm logfile, or, what I need do to
record my fprintf info
Avi Kivity wrote:
On 09/07/2012 03:07 PM, Liu, Jinsong wrote:
Avi Kivity wrote:
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 148ed66..0e64997 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -2210,7 +2210,11 @@ int kvm_dev_ioctl_check_extension(long ext
Avi Kivity wrote:
On 09/09/2012 05:54 PM, Liu, Jinsong wrote:
hrtimers is an intrusive feature, I don't think we should
force-enable it. Please change it to a depends on.
Hmm, if it changed as
config KVM
depends on HIGH_RES_TIMERS
The item 'Kernel-based Virtual Machine (KVM
64d0458ec50a7d6917adf1e9735ba6e6ae6024ad Mon Sep 17 00:00:00 2001
From: Liu, Jinsong jinsong@intel.com
Date: Sat, 8 Sep 2012 03:32:31 +0800
Subject: [PATCH] KVM: select HIGH_RES_TIMERS when KVM enabled
This is for 2 reasons:
1. it's pointless for kvm lapic timer and tsc deadline timer
when kernel hrtimer not configured
From 728a17e2de591b557c3c8ba31076b4bf2ca5ab42 Mon Sep 17 00:00:00 2001
From: Liu, Jinsong jinsong@intel.com
Date: Wed, 5 Sep 2012 03:18:15 +0800
Subject: [PATCH] KVM: tsc deadline timer works only when hrtimer high
resolution configured
This is for 2 reasons:
1. it's pointless to enable tsc
regarding to cpuid
exposing these days.
However, I think I may ignore something (so many discussion :-), so if you
think anything wrong, please point out to me.
Thanks,
Jinsong
From 8b5b003f6f8834d2d5d71e18bb47b7f089bc4928 Mon Sep 17 00:00:00 2001
From: Liu, Jinsong jinsong
Eduardo, Jan
I will update tsc deadline timer patch (at qemu-kvm side) recently.
Have you made a final agreement of the issue 'KVM_CAP_TSC_DEADLINE_TIMER' vs.
'GET_SUPPORTED_CPUID'?
Thanks,
Jinsong
Eduardo Habkost wrote:
(CCing Andre Przywara, in case he can help to clarify what's the
Eduardo Habkost wrote:
On Thu, Jun 14, 2012 at 07:02:03PM +, Liu, Jinsong wrote:
Eduardo, Jan
I will update tsc deadline timer patch (at qemu-kvm side) recently.
Have you made a final agreement of the issue
'KVM_CAP_TSC_DEADLINE_TIMER' vs. 'GET_SUPPORTED_CPUID'?
I don't think
Eduardo Habkost wrote:
On Fri, Mar 09, 2012 at 09:52:29PM +0100, Jan Kiszka wrote:
On 2012-03-09 20:09, Liu, Jinsong wrote:
Jan Kiszka wrote:
On 2012-03-09 19:27, Liu, Jinsong wrote:
Jan Kiszka wrote:
On 2012-03-06 08:49, Liu, Jinsong wrote:
Jan,
Any comments? I feel some confused about
Eduardo Habkost wrote:
On Fri, Mar 23, 2012 at 03:49:27AM +, Liu, Jinsong wrote:
Eduardo Habkost wrote:
[1] From Documentation/virtual/kvm/api.txt:
KVM_GET_SUPPORTED_CPUID
[...]
This ioctl returns x86 cpuid features which are supported by both
the hardware and kvm. Userspace can use
Eduardo Habkost wrote:
On Tue, Mar 20, 2012 at 12:53:57PM +, Liu, Jinsong wrote:
Rik van Riel wrote:
On 03/09/2012 01:27 PM, Liu, Jinsong wrote:
As for 'tsc deadline' feature exposing, my patch (as attached) just
obey qemu general cpuid exposing method, and also satisfied your
target I
Jan Kiszka wrote:
On 2012-03-09 20:09, Liu, Jinsong wrote:
Jan Kiszka wrote:
On 2012-03-09 19:27, Liu, Jinsong wrote:
Jan Kiszka wrote:
On 2012-03-06 08:49, Liu, Jinsong wrote:
Jan,
Any comments? I feel some confused about your point 'disable
cpuid feature for older machine types
Jan Kiszka wrote:
On 2012-03-06 08:49, Liu, Jinsong wrote:
Jan,
Any comments? I feel some confused about your point 'disable cpuid
feature for older machine types by default': are you planning a
common approach for this common issue, or, you just ask me a
specific solution for the tsc
Jan Kiszka wrote:
On 2012-03-09 19:27, Liu, Jinsong wrote:
Jan Kiszka wrote:
On 2012-03-06 08:49, Liu, Jinsong wrote:
Jan,
Any comments? I feel some confused about your point 'disable cpuid
feature for older machine types by default': are you planning a
common approach for this common
Liu, Jinsong wrote:
Jan Kiszka wrote:
On 2012-03-06 08:49, Liu, Jinsong wrote:
Jan,
Any comments? I feel some confused about your point 'disable cpuid
feature for older machine types by default': are you planning a
common approach for this common issue, or, you just ask me a
specific
Avi,
Any comments?
Thanks,
Jinsong
Liu, Jinsong wrote:
From ecd8be962f69393c183f941bfdbd7a7d3876d442 Mon Sep 17 00:00:00 2001
From: Liu, Jinsong jinsong@intel.com
Date: Mon, 27 Feb 2012 05:19:32 +0800
Subject: [PATCH] KVM: expose Intel cpu new features to guest
Intel recently release
Jan,
Any comments? I feel some confused about your point 'disable cpuid feature for
older machine types by default': are you planning a common approach for this
common issue, or, you just ask me a specific solution for the tsc deadline
timer case?
Thanks,
Jinsong
Liu, Jinsong wrote:
My
if in-kernel irqchip is used
and kvm has emulated tsc deadline timer;
2). It also authorizes user to control the feature exposing via a cpu feature
flag;
Thanks,
Jinsong
From 5b7d5f459b621686e78e437010ce34748bcb9e8e Mon Sep 17 00:00:00 2001
From: Liu, Jinsong jinsong
Jan Kiszka wrote:
On 2012-01-07 19:23, Liu, Jinsong wrote:
Jan Kiszka wrote:
On 2012-01-05 18:07, Liu, Jinsong wrote:
Sorry, it remains bogus to expose the tsc deadline timer feature
on machines pc-1.1. That's just like we introduced kvmclock
only to pc-0.14 onward. The reason is that guest
From ecd8be962f69393c183f941bfdbd7a7d3876d442 Mon Sep 17 00:00:00 2001
From: Liu, Jinsong jinsong@intel.com
Date: Mon, 27 Feb 2012 05:19:32 +0800
Subject: [PATCH] KVM: expose Intel cpu new features to guest
Intel recently release 2 new features, HLE and TRM.
Refer to http://software.intel.com
Jan Kiszka wrote:
On 2012-01-05 18:07, Liu, Jinsong wrote:
Sorry, it remains bogus to expose the tsc deadline timer feature on
machines pc-1.1. That's just like we introduced kvmclock only to
pc-0.14 onward. The reason is that guest OSes so far running on
qemu-1.0 or older without deadline
;
+}
+}
- disable it for older machine types (see below) by default
TSC deadline timer emulation in user space is a different story to be
told once we have a patch for it.
Signed-off-by: Liu, Jinsong jinsong@intel.com ---
target-i386/cpu.h |2 ++
target-i386/cpuid.c |7
Jan Kiszka wrote:
On 2011-12-28 18:35, Liu, Jinsong wrote:
diff --git a/qemu-kvm.h b/qemu-kvm.h
index 2bd5602..8c6c2ea 100644
--- a/qemu-kvm.h
+++ b/qemu-kvm.h
@@ -260,6 +260,7 @@ extern int kvm_irqchip;
extern int kvm_pit;
extern int kvm_pit_reinject;
extern unsigned int
diff --git a/qemu-kvm.h b/qemu-kvm.h
index 2bd5602..8c6c2ea 100644
--- a/qemu-kvm.h
+++ b/qemu-kvm.h
@@ -260,6 +260,7 @@ extern int kvm_irqchip;
extern int kvm_pit;
extern int kvm_pit_reinject;
extern unsigned int kvm_shadow_memory;
+extern int tsc_deadline_timer;
int
From 5afecc308bc25c7fd8d124e7557f08fb067d6caa Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Thu, 29 Dec 2011 01:45:45 +0800
Subject: [PATCH 1/2] Define KVM_CAP_TSC_DEADLINE_TIMER
Signed-off-by: Liu, Jinsong jinsong@intel.com
Signed-off-by: Jan Kiszka jan.kis
From 3a78adf8006ec6189bfe2f55f7ae213e75bf3815 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Thu, 29 Dec 2011 05:28:12 +0800
Subject: [PATCH 2/2] Expose tsc deadline timer cpuid to guest
Depend on several factors:
1. Considering live migration, user enable/disable tsc
Avi Kivity wrote:
On 12/22/2011 05:41 PM, Liu, Jinsong wrote:
Avi Kivity wrote:
On 12/21/2011 12:25 PM, Jan Kiszka wrote:
We must not report the TSC deadline timer feature on our own when
user space provides the APIC as we have no clue about its features.
We must not report the TSC
Avi Kivity wrote:
From: Jan Kiszka jan.kis...@siemens.com
Unlike all of the other cpuid bits, the TSC deadline timer bit is set
unconditionally, regardless of what userspace wants.
This is broken in several ways:
- if userspace doesn't use KVM_CREATE_IRQCHIP, and doesn't emulate
the
Sasha Levin wrote:
On Sun, 2011-12-25 at 21:00 +0200, Sasha Levin wrote:
On Sun, 2011-12-25 at 15:03 +0200, Avi Kivity wrote:
+ if (apic) {
+ if (best-ecx bit(X86_FEATURE_TSC_DEADLINE_TIMER))
+ apic-lapic_timer.timer_mode_mask = 3 17;
+ else
+
Avi Kivity wrote:
On 12/26/2011 10:11 AM, Liu, Jinsong wrote:
It breaks live migration: if you start a guest on a TSC-deadline
capable host kernel, and migrate it to a TSC-deadline incapable host
kernel, you end up with a broken guest.
More broadly, kvm never exposes features
From 19caf1db1f93e6f6b736e1dfd5e91a0c7669adec Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Tue, 27 Dec 2011 04:08:27 +0800
Subject: [PATCH] Expose tsc deadline timer cpuid to guest
Depend on several factors:
1. Considering live migration, user enable/disable tsc deadline
From 8bb5d052825149c211afa92458912bc49a50ee2f Mon Sep 17 00:00:00 2001
From: Liu, Jinsong jinsong@intel.com
Date: Mon, 28 Nov 2011 03:55:19 -0800
Subject: [PATCH] X86: expose latest Intel cpu new features to guest
Intel latest cpu add 6 new features, refer http://software.intel.com/file/36945
Avi Kivity wrote:
On 10/09/2011 05:32 PM, Liu, Jinsong wrote:
Updated test case for kvm tsc deadline timer
https://github.com/avikivity/kvm-unit-tests, as attached.
Applied, thanks.
Which tree? I didn't find it at git://github.com/avikivity/kvm-unit-tests.git
Thanks,
Jinsong
Marcelo Tosatti wrote:
On Wed, Oct 12, 2011 at 12:26:12PM +0800, Liu, Jinsong wrote:
Marcelo,
I just test guest migration from v13 to v12, it failed w/ info
savevm: unsupported version 13 for 'cpu' v12
load of migration failed
v13 is new qemu-kvm with tsc deadline timer co-work patch
Marcelo,
I just test guest migration from v13 to v12, it failed w/ info
savevm: unsupported version 13 for 'cpu' v12
load of migration failed
v13 is new qemu-kvm with tsc deadline timer co-work patch, v12 is old qemu-kvm.
Marcelo Tosatti wrote:
Jinsong, please test this qemu-kvm patch by
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