On Mon, Jan 20, 2014, Marcelo Tosatti wrote about Re: Monotonic clock with KVM
pv-clock:
On Mon, Jan 20, 2014 at 11:56:56AM +0200, Nadav Har'El wrote:
Hi,
I'm trying to figure out how a guest OS can get a monotonic clock using
KVM's paravirtual clock.
At first, I thought
changes and KVM_SYSTEM_TIME doesn't,
but am no longer sure this is actually the case.
If KVM_SYSTEM_TIME is not a correct way to get a monotonic paravirtual clock
from KVM, is there a correct way?
Thanks,
Nadav.
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Nadav Har'El| Monday, Jan 20 2014, 19 Shevat 5774
n
Center Embedded Linux
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;
vmcs12-vm_exit_intr_info = 0;
+ if (enable_shadow_vmcs)
+ copy_vmcs12_to_shadow(to_vmx(vcpu));
where you need to copy this exit-reason override as well...
I wonder if there isn't a less ugly and repetitive way to do this :(
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Nadav Har'El
easy to exercise this.
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Nadav Har'El| Monday, Mar 4 2013, 22 Adar 5773
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is supported, we *also* support 0 setting. I'm not
sure why this is a bad thing. Our VMX will be even better than the
real processors' ;-)
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Nadav Har'El| Monday, Mar 4 2013, 22 Adar 5773
n...@math.technion.ac.il
would not see a difference.
+ vmx_set_rflags(vcpu, 0x02);
There's a macro X86_EFLAGS_BIT1 which you can use for this 0x02.
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Nadav Har'El| Sunday, Mar 3 2013, 22 Adar 5773
n...@math.technion.ac.il |-
Phone
:( These patches
definitely need some lovin', but it's easier than starting from scratch.
Nadav.
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Nadav Har'El| Tuesday, Feb 26 2013, 16 Adar 5773
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |I
, it causes the L1 guest to lock up, and is not ignored?
Nadav.
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Nadav Har'El|Monday, Feb 25 2013, 15 Adar 5773
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |If con is the opposite of pro
kvm_set_cr0(), because it does some extra stuff and does some extra
checks. Hmm, see, see this:
http://markmail.org/message/hhidqyhbo2mrgxxc
where Avi asked for the reverse patch you're attempting now.
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Nadav Har'El| Saturday, Feb 23 2013, 14 Adar 5773
n
.
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Nadav Har'El| Thursday, Feb 21 2013, 11 Adar 5773
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |Cat rule #2: Bite the hand that won't
http://nadav.harel.org.il |feed you fast enough
was necessary, after all.
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http://nadav.harel.org.il
=
vmcs_read32(VM_EXIT_REASON)). Maybe I'm missing something?
Nadav.
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Nadav Har'El| Wednesday, Feb 20 2013, 10 Adar 5773
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |Change is inevitable, except from a
http
. I tend to believe now my first idea was better.
If you want to make the !PIN_BASED_EXT_INTR_MASK case work correctly,
please also see:
https://bugzilla.kernel.org/show_bug.cgi?id=53711
Nadav.
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Nadav Har'El| Saturday, Feb 16 2013, 6 Adar 5773
n
in both.
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Nadav Har'El| Thursday, Feb 14 2013, 4 Adar 5773
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |A fanatic is one who can't change his
http://nadav.harel.org.il |mind and won't
the port
number before using it as an offset into io_bitmap_b?
Nadav.
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Nadav Har'El| Monday, Feb 11 2013, 1 Adar 5773
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |Attention
to improve it. So unfortunately, you
should expect more of this bugzilla spam on the mailing list...
Nadav.
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Nadav Har'El| Monday, Feb 11 2013, 1 Adar 5773
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ
it). After each exit, the hypervisor resumes
running at might decide (using Linux's normal scheduling policies) to
schedule a different process or VM instead of the one that just exited.
--
Nadav Har'El|Wednesday, Sep 19 2012, 3 Tishri 5773
n...@math.technion.ac.il
and running its own guest. This is
known as nested virtualization.
In an ordinary (non-hypervisor) guest, you'll never see this exit
reason.
--
Nadav Har'El| Thursday, Sep 20 2012, 4 Tishri 5773
n...@math.technion.ac.il
.
--
Nadav Har'El| Thursday, Sep 13 2012, 26 Elul 5772
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |error compiling committee.c: too many
http://nadav.harel.org.il |arguments to function
that is never used, so I had to #if them out...
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Nadav Har'El| Thursday, Aug 2 2012, 15 Av 5772
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |It's fortunate I have bad luck - without
http
, we return 1 - meaning that
we exit to L1 so that it can handle this hypercall.
I believe that this is this is the more sensible behavior, but if you
want L0 to handle hypercalls, you can, in the EXIT_REASON_VMCALL case
in that function, return 0, which would cause L0 to handle this exit.
--
Nadav
| 11 -
7 files changed, 354 insertions(+), 41 deletions(-)
--
Nadav Har'El
IBM Haifa Research Lab
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of several vmcs02 fields), so we always
support this feature, regardless of whether the host supports it.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/vmx.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
--- .before/arch/x86/kvm/vmx.c 2012-08-01 17:22
.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/mmu.c | 14 +
arch/x86/kvm/paging_tmpl.h | 98 ---
2 files changed, 96 insertions(+), 16 deletions(-)
--- .before/arch/x86/kvm/mmu.c 2012-08-01 17:22:46.0 +0300
+++ .after/arch/x86
need to switch back and forth between this nested context and the
regular MMU context when switching between L1 and L2 (when L1 runs this L2
with EPT).
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/mmu.c | 38 +++
arch/x86/kvm/mmu.h |1
arch/x86
. This patch adds this copy.
If L0 isn't controlling cr3 when running L2 (i.e., L0 is using EPT), and
whoever does control cr3 (L1 or L2) is using PAE, the processor might have
saved PDPTEs and we should also save them in vmcs12 (and restore later).
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86
of the original nested VMX patches),
we can't avoid this problem and need to fix it.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/x86.c | 11 ---
1 file changed, 11 deletions(-)
--- .before/arch/x86/kvm/x86.c 2012-08-01 17:22:47.0 +0300
+++ .after/arch/x86/kvm
Some additional comments to preexisting code:
Explain who (L0 or L1) handles EPT violation and misconfiguration exits.
Don't mention shadow on either EPT or shadow as the only two options.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/vmx.c | 21 +++--
1 file
.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/vmx.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
--- .before/arch/x86/kvm/vmx.c 2012-08-01 17:22:47.0 +0300
+++ .after/arch/x86/kvm/vmx.c 2012-08-01 17:22:47.0 +0300
@@ -1946,6 +1946,7
.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/include/asm/vmx.h |2
arch/x86/kvm/vmx.c | 87 +++
2 files changed, 89 insertions(+)
--- .before/arch/x86/include/asm/vmx.h 2012-08-01 17:22:47.0 +0300
+++ .after/arch/x86/include/asm
Update the documentation to no longer say that nested EPT is not supported.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
Documentation/virtual/kvm/nested-vmx.txt |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- .before/Documentation/virtual/kvm/nested-vmx.txt2012-08-01
Some trivial code cleanups not really related to nested EPT.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/vmx.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
--- .before/arch/x86/kvm/vmx.c 2012-08-01 17:22:47.0 +0300
+++ .after/arch/x86/kvm/vmx.c 2012
.
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Nadav Har'El|Wednesday, Aug 1 2012, 13 Av 5772
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |May you live as long as you want - and
http://nadav.harel.org.il |never want as long as you
* virtualization (where the host,
guest, and guest's guest all want to delay loading the FPU registers) -
it took me about a month to get that working without bugs ;-)
--
Nadav Har'El| Thursday, Jun 21 2012,
n...@math.technion.ac.il
- You discuss interrupt delivery without stating that you have MSIs in
mind. Some aspects may be helpful for legacy interrupts as well, but
you obviously can't achieve exit-less operation there. Not an issue,
should just be made clear.
Can you eleborate on why exit-less operation
doesn't try to turn on more bits.
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Nadav Har'El| Tuesday, May 15 2012,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |A bird in the hand is safer than one
http://nadav.harel.org.il
for device assignment, without any changes (in performance or
security) in the host?
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Nadav Har'El|Sunday, Apr 22 2012,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |Sign in zoo: Do
. This noticably slows down I/O, unfortunately.
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Nadav Har'El|Friday, Apr 20 2012,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |A bird in the hand is safer than one
http://nadav.harel.org.il
, and then VMPTRLD on the new CPU.
So you don't need to VMXOFF, but do need to VMCLEAR. But there's still
the complication that you mention - you need to do the VMCLEAR on the right
processor...
--
Nadav Har'El| Wednesday, Apr 18 2012,
n...@math.technion.ac.il
correctly? Are you using an emulated serial console, emulated
VGA (on X? on VNC?), or what?
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Nadav Har'El|Monday, Apr 16 2012,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |If Barbie
of being unusable (I think you saw this with grub performance in L3).
So I wonder if you'd really want to use it, even if it worked... Just
curious, what were you thinking of doing with L3?
Nadav.
--
Nadav Har'El| Wednesday, Apr 11 2012,
n
-data = data;
+ if (msr - vmx-guest_msrs vmx-save_nmsrs)
+ kvm_set_shared_msr(msr-index, msr-data,
+ msr-mask);
break;
}
--
Nadav Har'El
version.
Nadav.
--
Nadav Har'El| Monday, Apr 9 2012,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |Diplomat: A man who always remembers a
http://nadav.harel.org.il |woman's
much more efficiently.
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Phone +972-523-790466, ICQ 13349191 |Lottery: You need a dollar and a dream.
http://nadav.harel.org.il
.
But I can't help but wonder if you can flip the locking bit from
the locked position to the unlocked position if you're still in
real mode.
What makes you think that being in real mode makes a difference?
As far as I know, it doesn't. Any reason why you think it does?
--
Nadav Har'El
PM, Nadav Har'El wrote:
+ u64 msr_ia32_feature_control;
};
Need to add to the list of exported MSRs so it can be live migrated
(msrs_to_save).
Did this.
The variable itself should live in vcpu-arch, even if
some bits are vendor specific.
But not this. I understand what you explained
.
This patch emulates this MSR better, allowing the guest to lock it, and
verifying its setting on VMXON. Also make sure that this MSR (and of course,
VMXON state) is reset on guest vcpu reset (via SIPI).
Signed-off-by: Nadav Har'El n...@il.ibm.com
Reported-by: Julian Stecklina j...@alien8.de
On Sun, Mar 04, 2012, Michael S. Tsirkin wrote about Re: [PATCH] vhost: don't
forget to schedule():
On Sun, Mar 04, 2012 at 11:10:01AM +0200, Nadav Har'El wrote:
On Tue, Feb 28, 2012, Avi Kivity wrote about Re: [PATCH] vhost: don't
forget to schedule
(vcpu)-nested.msr_ia32_feature_control;
break;
In a separate patch, please move this outside vmx_get_vmx_msr(). It's
not a vmx msr.
I agree, I'll move it. But if it's a VMX-only MSR, I want to leave it
in vmx.c, and not move it to x86.c.
--
Nadav Har'El
On Wed, Mar 07, 2012, Avi Kivity wrote about Re: [PATCH] KVM: Enable
VMX-related bits in MSR_IA32_FEATURE_CONTROL.:
On 03/06/2012 07:33 PM, Nadav Har'El wrote:
By the way, am I right in my understanding that KVM doesn't support
SMX in the guest?
Isn't nested vmx crazy enough?
:-)
btw
.
This patch emulates this MSR better, allowing the guest to lock it, and
verifying its setting on VMXON. Also make sure that this MSR (and of course,
VMXON state) is reset on guest vcpu reset (via SIPI).
Signed-off-by: Nadav Har'El n...@il.ibm.com
Reported-by: Julian Stecklina j...@alien8.de
that should have been more
properly done in another place, but I've yet to figure out exactly what.
I'll send a patch when I have this figured out. If anybody else has any
guess, I'd love to hear.
Nadav.
--
Nadav Har'El|Tuesday, Mar 6 2012,
n
this patch, and indeed it solves the bug with nested
VMX.
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Nadav Har'El|Tuesday, Mar 6 2012,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |I think therefore I am. My computer
http
The code which checks whether to inject a pagefault to L1 or L2 (in
nested VMX) was wrong, incorrect in how it checked the PF_VECTOR bit.
Thanks to Dan Carpenter for spotting this.
Signed-off-by: Nadav Har'El n...@il.ibm.com
Reported-by: Dan Carpenter dan.carpen...@oracle.com
---
arch/x86/kvm
to disable
nested VMX if it wishes (not that I think this is a very useful
usecase...).
3. vmx_set_vmx_msr to MSR_IA32_FEATURE_CONTROL should throw a #GP if
FEATURE_CONTROL_LOCKED is on.
I'll create a patch to do this shortly.
--
Nadav Har'El
On Tue, Mar 06, 2012, Nadav Har'El wrote about Re: [PATCH] KVM: Enable
VMX-related bits in MSR_IA32_FEATURE_CONTROL.:
2. handle_vmon() does not check the previous setting of this MSR.
If the guest (or its BIOS) doesn't set both FEATURE_CONTROL_LOCKED
), and they were removed, but the extra check remained.
Do you want a patch to remove this extra check? Or you can just remove
it yourself?
Thanks,
Nadav.
--
Nadav Har'El| Sunday, Mar 4 2012,
n...@math.technion.ac.il
anybody shed a light on what
is the right way to do it?
--
Nadav Har'El| Tuesday, Feb 28 2012,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |I am logged in, therefore I am.
http
Gordon for this patch.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
vhost.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index c14c42b..ae66278 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -222,6 +222,8 @@ static int
to know that in
nested_ept_inject_page_fault. Moreover, in the original EPT visolation's
exit qualification, there were various other bits which we lose (and don't
have a direct parallel in PFERR_* anyway), so when we reinject the fault,
L1 doesn't get them.
What a mess :(
--
Nadav Har'El
On Thu, Nov 10, 2011, Avi Kivity wrote about Re: [PATCH 08/10] nEPT: Nested
INVEPT:
On 11/10/2011 12:01 PM, Nadav Har'El wrote:
If we let L1 use EPT, we should probably also support the INVEPT
instruction.
..
+ if (vmcs12 nested_cpu_has_ept(vmcs12
(ACC_*_MASK)
4. EPT access bits (VMX_EPT_*_MASK).
I just have to try hard not to confuse them.
--
Nadav Har'El| Thursday, Dec 8 2011,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191
?
The last thing I want to do is to repeat the same definitions in two places.
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Nadav Har'El| Wednesday, Dec 7 2011,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |A witty saying proves
or
relevance to the SVM code. It's not a terrible disaster, but it's
unclean. I'll try to think if there's a cleaner way.
Nadav.
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Nadav Har'El|Tuesday, Dec 6 2011,
n...@math.technion.ac.il |-
Phone
qemu64 by whatever you want) to
advertise the exisance of VMX.
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Nadav Har'El| Wednesday, Nov 23 2011,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |When you lose, don't lose the lesson
pas.
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Nadav Har'El| Wednesday, Nov 23 2011,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |Why do doctors call what they do
http://nadav.harel.org.il |practice? Think about
be there - right?
It seems we need a fifth case in that function.
But at that point in mmu.c, how will I be able to check if this is the
nested EPT case? Do you have any suggestion?
Thanks,
Nadav.
--
Nadav Har'El| Wednesday, Nov 23 2011,
n...@math.technion.ac.il
On Wed, Nov 23, 2011, Nadav Har'El wrote about Re: [PATCH 02/10] nEPT: MMU
context for nested EPT:
+static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
+{
+ int r = kvm_init_shadow_mmu(vcpu, vcpu-arch.mmu);
+
+ vcpu-arch.nested_mmu.gva_to_gpa = EPT_gva_to_gpa_nested
has an exception bitmap which defines which exceptions cause
an exit, and you can turn on the #UD bit to ask for this exit.
--
Nadav Har'El|Monday, Nov 14 2011,
n...@math.technion.ac.il |-
Phone +972
an IOMMU for L1, how can that be done?
Thanks,
Nadav.
--
Nadav Har'El|Sunday, Nov 13 2011,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |An error? Impossible! My modem is error
http
gets notified ( i.e. TLB invalidated). some
kind of apic needs to be sent, right ?
I didn't quite follow your example, but there is indeed a remote tlb
flush IPI.
--
Nadav Har'El|Sunday, Nov 13 2011,
n...@math.technion.ac.il
-on-ept code.
And in simple (64 bit, 4k page) kvm-over-kvm configurations like I tried, it
works well.
Nadav.
--
Nadav Har'El| Saturday, Nov 12 2011,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ
| 16 -
arch/x86/kvm/paging_tmpl.h |6
arch/x86/kvm/vmx.c | 259 -
arch/x86/kvm/x86.c | 11
7 files changed, 269 insertions(+), 30 deletions(-)
--
Nadav Har'El
IBM Haifa Research Lab
--
To unsubscribe
, currently we do not support this mode,
and it is becoming less interesting as newer processors all support EPT.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/vmx.c | 12
1 file changed, 12 insertions(+)
--- .before/arch/x86/kvm/vmx.c 2011-11-10 11:33:58.0
and L2.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/vmx.c | 60 +++
1 file changed, 60 insertions(+)
--- .before/arch/x86/kvm/vmx.c 2011-11-10 11:33:58.0 +0200
+++ .after/arch/x86/kvm/vmx.c 2011-11-10 11:33:58.0 +0200
. This patch adds this copy.
If L0 isn't controlling cr3 when running L2 (i.e., L0 is using EPT), and
whoever does control cr3 (L1 or L2) is using PAE, the processor might have
saved PDPTEs and we should also save them in vmcs12 (and restore later).
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86
), which is a reserved bit in EPT and causes
an EPT Misconfiguration failure.
So we must move link_shadow_page's list of extra bits to a new mmu context
field, which is set differently for nested EPT.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/include/asm/kvm_host.h |1 +
arch/x86
Kivity's review of the original nested VMX patches),
we can't avoid this problem and need to fix it.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/x86.c | 11 ---
1 file changed, 11 deletions(-)
--- .before/arch/x86/kvm/x86.c 2011-11-10 11:33:59.0 +0200
+++ .after/arch
Some additional comments to preexisting code:
Explain who (L0 or L1) handles EPT violation and misconfiguration exits.
Don't mention shadow on either EPT or shadow as the only two options.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/vmx.c | 21 +++--
1 file
If we let L1 use EPT, we should probably also support the INVEPT instruction.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/include/asm/vmx.h |2
arch/x86/kvm/vmx.c | 112 +++
2 files changed, 114 insertions(+)
--- .before/arch/x86
.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/vmx.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
--- .before/arch/x86/kvm/vmx.c 2011-11-10 11:33:59.0 +0200
+++ .after/arch/x86/kvm/vmx.c 2011-11-10 11:33:59.0 +0200
@@ -1908,6 +1908,7
Some trivial code cleanups not really related to nested EPT.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/vmx.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
--- .before/arch/x86/kvm/vmx.c 2011-11-10 11:33:59.0 +0200
+++ .after/arch/x86/kvm/vmx.c 2011
Update the documentation to no longer say that nested EPT is not supported.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
Documentation/virtual/kvm/nested-vmx.txt |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- .before/Documentation/virtual/kvm/nested-vmx.txt2011-11-10
kvm_mmu to link_shadow_page, or I just
pass the only field which I need... I thought that passing the single
field I need was cleaner - but I can easily change it if you prefer to
pass the kvm_mmu.
Thanks,
Nadav.
--
Nadav Har'El| Thursday, Nov 10 2011
On Thu, Nov 10, 2011, Avi Kivity wrote about Re: [PATCH 01/10] nEPT: Module
option:
On 11/10/2011 11:58 AM, Nadav Har'El wrote:
Add a module option nested_ept determining whether to enable Nested EPT.
...
In the future, we can support emulation of EPT for L1 *always*, even when L0
itself
similarly.
And it does in fact work - in typical cases which I tried, at least.
If you still think I'm missing something, I won't be entirely surprised
( :-) ), so let me know.
Nadav.
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Nadav Har'El| Thursday, Nov 10 2011,
n...@math.technion.ac.il
can force back the old shadow-on-EPT method with just a single option
in L0 (instead of needing to give ept=0 option in L1s).
If you really don't like the existance of this option, I can easily
remove it of course.
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Nadav Har'El| Thursday, Nov 10 2011
this :(
Back to the drawing board, I guess. I need to figure out exactly what
needs to be fixed, and how to do this with the least obtrusive changes to
the existing use case (normal shadow page tables, and nested EPT).
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Nadav Har'El| Thursday, Nov 10 2011,
n
...
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Nadav Har'El|Sunday, Oct 16 2011,
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |Computers are like air conditioners. Both
http://nadav.harel.org.il |stop working
/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-3b-system-programming-manual.html
Volume 2 of the same manual gives additional details on each instructions
like the aforementioned VMLAUNCH and friends.
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Nadav Har'El|Sunday
On Fri, Sep 23, 2011, Marcelo Tosatti wrote about Re: [PATCH 1/2] nVMX: Add
KVM_REQ_IMMEDIATE_EXIT:
On Thu, Sep 22, 2011 at 01:52:56PM +0300, Nadav Har'El wrote:
This patch adds a new vcpu-requests bit, KVM_REQ_IMMEDIATE_EXIT.
This bit requests that when next entering the guest, we should
statistics:
-
arch/x86/kvm/vmx.c | 18 +++---
arch/x86/kvm/x86.c |6 ++
include/linux/kvm_host.h |1 +
3 files changed, 18 insertions(+), 7 deletions(-)
--
Nadav Har'El
IBM Haifa Research Lab
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To unsubscribe from this list: send the line unsubscribe
-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/vmx.c | 11 +++
arch/x86/kvm/x86.c |6 ++
include/linux/kvm_host.h |1 +
3 files changed, 14 insertions(+), 4 deletions(-)
--- .before/include/linux/kvm_host.h2011-09-22 13:51:31.0 +0300
+++ .after
the solution, and to Avi Kivity
for helping to improve it.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/vmx.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
--- .before/arch/x86/kvm/vmx.c 2011-09-22 13:51:31.0 +0300
+++ .after/arch/x86/kvm/vmx.c 2011-09
vectoring info) of the original nVMX patch series.
Thanks to Dave Allan and to Federico Simoncelli for reporting this bug,
to Abel Gordon for helping me figure out the solution, and to Avi Kivity
for helping to improve it.
Signed-off-by: Nadav Har'El n...@il.ibm.com
---
arch/x86/kvm/vmx.c | 20
).
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Nadav Har'El| Wednesday, Aug 10 2011, 10 Av 5771
n...@math.technion.ac.il |-
Phone +972-523-790466, ICQ 13349191 |Always keep your words soft and sweet,
http://nadav.harel.org.il |just in case you have to eat
) in situations where this value is wrongly returned to the
guest, but this will leave qemu to always read the TSC MSR from L1, even when
L2 is running. While I proposed this as a second option, I don't think I
can recommend it.
So what's the verdict? :-)
Thanks,
Nadav.
--
Nadav Har'El
virtual machine. Those failures are very
rare.
How is this different from a VM running on a single machine that fails?
Just that the small probability of failure (roughly) doubles for the
relatively-short duration of the transfer?
--
Nadav Har'El
running L2, the adjustment needs to apply to L1 */
to_vmx(vcpu)-nested.vmcs01_tsc_offset += adjustment;
}
}
Thanks,
Nadav.
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Nadav Har'El|Wednesday, Aug 3 2011, 3 Av 5771
n...@math.technion.ac.il
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