If posted interrupts are enabled, we can no longer track if an IRQ was
coalesced based on IRR. So drop this logic also from the classic
software path and simplify apic_test_and_set_irr to apic_set_irr.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/x86/kvm/lapic.c | 23
Both have no users anymore.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/x86/kvm/lapic.c | 10 --
1 files changed, 0 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 9dc3650..c98f054 100644
--- a/arch/x86/kvm/lapic.c
+++
Il 24/07/2013 23:37, H. Peter Anvin ha scritto:
What I'm suggesting is exactly that except that the native hypervisor is
later in CPUID space.
Me too actually.
I was just suggesting an implementation of the idea (that takes into
account hypervisors detected by other means than CPUID).
Paolo
On 2013-07-25 07:31, Arthur Chunqi Li wrote:
This is the first version of VMX nested environment. It contains the
basic VMX instructions test cases, including VMXON/VMXOFF/VMXPTRLD/
VMXPTRST/VMCLEAR/VMLAUNCH/VMRESUME/VMCALL. This patchalso tests the
basic execution routine in VMX nested
On 07/25/2013 03:59 PM, Paolo Bonzini wrote:
Il 24/07/2013 23:37, H. Peter Anvin ha scritto:
What I'm suggesting is exactly that except that the native hypervisor is
later in CPUID space.
Me too actually.
I was just suggesting an implementation of the idea (that takes into
account
On Wed, Jul 24, 2013 at 03:32:49PM -0500, Scott Wood wrote:
On 07/24/2013 04:39:59 AM, Alexander Graf wrote:
On 24.07.2013, at 11:35, Gleb Natapov wrote:
On Wed, Jul 24, 2013 at 11:21:11AM +0200, Alexander Graf wrote:
Are not we going to use page_is_ram() from
e500_shadow_mas2_attrib()
From: Konstantin Weitz konstantin.we...@gmail.com
This patch enables Collaborative Memory Management (CMM) for kvm
on s390. CMM allows the guest to inform the host about page usage
(see arch/s390/mm/cmm.c). The host uses this information to avoid
swapping in unused pages in the page fault
From: Konstantin Weitz konstantin.we...@gmail.com
In a virtualized environment and given an appropriate interface the guest
can mark pages as unused while they are free (for the s390 implementation
see git commit 45e576b1c3d00206 guest page hinting light). For the host
the unused state is a
v1-v2:
- found a way to simplify the common code patch
Linux on s390 as a guest under z/VM has been using the guest page
hinting interface (alias collaborative memory management) for a long
time. The full version with volatile states has been deemed to be too
complicated (see the old discussion
We try to handle the hypervisor compatibility mode by detecting hypervisor
through a specific order. This is not robust, since hypervisors may implement
each others features.
This patch tries to handle this situation by always choosing the last one in the
CPUID leaves. This is done by letting
This patch introduce hypervisor_cpuid_base() which loop test the hypervisor
existence function until the signature match and check the number of leaves if
required. This could be used by Xen/KVM guest to detect the existence of
hypervisor.
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar
Switch to use hypervisor_cpuid_base() to detect Xen.
Cc: Konrad Rzeszutek Wilk konrad.w...@oracle.com
Cc: Jeremy Fitzhardinge jer...@goop.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@redhat.com
Cc: H. Peter Anvin h...@zytor.com
Cc: x...@kernel.org
Cc: Paolo Bonzini
Switch to use hypervisor_cpuid_base() to detect KVM.
Cc: Gleb Natapov g...@redhat.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@redhat.com
Cc: H. Peter Anvin h...@zytor.com
Cc: x...@kernel.org
Cc: kvm@vger.kernel.org
Signed-off-by: Jason
On 07/24/2013 06:06 PM, Raghavendra K T wrote:
On 07/24/2013 05:36 PM, Gleb Natapov wrote:
On Wed, Jul 24, 2013 at 05:30:20PM +0530, Raghavendra K T wrote:
On 07/24/2013 04:09 PM, Gleb Natapov wrote:
On Wed, Jul 24, 2013 at 03:15:50PM +0530, Raghavendra K T wrote:
On 07/23/2013 08:37 PM,
On Thu, Jul 25, 2013 at 02:47:37PM +0530, Raghavendra K T wrote:
On 07/24/2013 06:06 PM, Raghavendra K T wrote:
On 07/24/2013 05:36 PM, Gleb Natapov wrote:
On Wed, Jul 24, 2013 at 05:30:20PM +0530, Raghavendra K T wrote:
On 07/24/2013 04:09 PM, Gleb Natapov wrote:
On Wed, Jul 24, 2013 at
On 07/25/2013 02:45 PM, Gleb Natapov wrote:
On Thu, Jul 25, 2013 at 02:47:37PM +0530, Raghavendra K T wrote:
On 07/24/2013 06:06 PM, Raghavendra K T wrote:
On 07/24/2013 05:36 PM, Gleb Natapov wrote:
On Wed, Jul 24, 2013 at 05:30:20PM +0530, Raghavendra K T wrote:
On 07/24/2013 04:09 PM,
On Sun, Jul 07, 2013 at 11:13:37PM +0800, Arthur Chunqi Li wrote:
The recent KVM patch adds IA32_FEATURE_CONTROL support. QEMU needs
to clear this MSR when reset vCPU and keep the value of it when
migration. This patch add this feature.
Signed-off-by: Arthur Chunqi Li yzt...@gmail.com
On 04.07.2013, at 08:57, Bharat Bhushan wrote:
KVM need this function when switching from vcpu to user-space
thread. My subsequent patch will use this function.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
Ben / Michael, please ack.
Alex
---
v5-v6
-
On Thu, Jul 25, 2013 at 09:58:45AM +0200, Jan Kiszka wrote:
If posted interrupts are enabled, we can no longer track if an IRQ was
coalesced based on IRR. So drop this logic also from the classic
software path and simplify apic_test_and_set_irr to apic_set_irr.
Signed-off-by: Jan Kiszka
On 25/07/13 10:54, Martin Schwidefsky wrote:
v1-v2:
- found a way to simplify the common code patch
Linux on s390 as a guest under z/VM has been using the guest page
hinting interface (alias collaborative memory management) for a long
time. The full version with volatile states has been
On 25/07/13 10:54, Martin Schwidefsky wrote:
From: Konstantin Weitz konstantin.we...@gmail.com
In a virtualized environment and given an appropriate interface the guest
can mark pages as unused while they are free (for the s390 implementation
see git commit 45e576b1c3d00206 guest page
-Original Message-
From: Jason Wang [mailto:jasow...@redhat.com]
Sent: Thursday, July 25, 2013 4:55 AM
To: t...@linutronix.de; mi...@redhat.com; h...@zytor.com; x...@kernel.org;
linux-ker...@vger.kernel.org; pbonz...@redhat.com
Cc: kvm@vger.kernel.org; Jason Wang; KY Srinivasan;
On 25/07/13 10:54, Martin Schwidefsky wrote:
From: Konstantin Weitz konstantin.we...@gmail.com
This patch enables Collaborative Memory Management (CMM) for kvm
on s390. CMM allows the guest to inform the host about page usage
(see arch/s390/mm/cmm.c). The host uses this information to avoid
EPT uses different shifts for A/D bits and first version of nEPT does
not support them at all.
Signed-off-by: Gleb Natapov g...@redhat.com
---
arch/x86/kvm/paging_tmpl.h | 30 ++
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git
After changing hands several times I proud to present a new version of
Nested EPT patches. Nothing groundbreaking here comparing to v3: all
review comment are addressed, some by Yang Zhang and some by Yours Truly.
Gleb Natapov (1):
nEPT: make guest's A/D bits depends on guest's paging mode
From: Nadav Har'El n...@il.ibm.com
Some additional comments to preexisting code:
Explain who (L0 or L1) handles EPT violation and misconfiguration exits.
Don't mention shadow on either EPT or shadow as the only two options.
Signed-off-by: Nadav Har'El n...@il.ibm.com
Signed-off-by: Jun Nakajima
From: Yang Zhang yang.z.zh...@intel.com
Inject nEPT fault to L1 guest. This patch is original from Xinhao.
Signed-off-by: Jun Nakajima jun.nakaj...@intel.com
Signed-off-by: Xinhao Xu xinhao...@intel.com
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
Signed-off-by: Gleb Natapov g...@redhat.com
From: Nadav Har'El n...@il.ibm.com
Advertise the support of EPT to the L1 guest, through the appropriate MSR.
This is the last patch of the basic Nested EPT feature, so as to allow
bisection through this patch series: The guest will not see EPT support until
this last patch, and will not attempt
From: Nadav Har'El n...@il.ibm.com
The existing code for handling cr3 and related VMCS fields during nested
exit and entry wasn't correct in all cases:
If L2 is allowed to control cr3 (and this is indeed the case in nested EPT),
during nested exit we must copy the modified cr3 from vmcs02 to
From: Nadav Har'El n...@il.ibm.com
Some trivial code cleanups not really related to nested EPT.
Signed-off-by: Nadav Har'El n...@il.ibm.com
Signed-off-by: Jun Nakajima jun.nakaj...@intel.com
Signed-off-by: Xinhao Xu xinhao...@intel.com
Reviewed-by: Paolo Bonzini pbonz...@redhat.com
From: Nadav Har'El n...@il.ibm.com
Recent KVM, since http://kerneltrap.org/mailarchive/linux-kvm/2010/5/2/6261577
switch the EFER MSR when EPT is used and the host and guest have different
NX bits. So if we add support for nested EPT (L1 guest using EPT to run L2)
and want to be able to run
From: Nadav Har'El n...@il.ibm.com
KVM's existing shadow MMU code already supports nested TDP. To use it, we
need to set up a new MMU context for nested EPT, and create a few callbacks
for it (nested_ept_*()). This context should also use the EPT versions of
the page table access functions
From: Nadav Har'El n...@il.ibm.com
If we let L1 use EPT, we should probably also support the INVEPT instruction.
In our current nested EPT implementation, when L1 changes its EPT table
for L2 (i.e., EPT12), L0 modifies the shadow EPT table (EPT02), and in
the course of this modification already
From: Nadav Har'El n...@il.ibm.com
For preparation, we just move gpte_access(), prefetch_invalid_gpte(),
s_rsvd_bits_set(), protect_clean_gpte() and is_dirty_gpte() from mmu.c
to paging_tmpl.h.
Signed-off-by: Nadav Har'El n...@il.ibm.com
Signed-off-by: Jun Nakajima jun.nakaj...@intel.com
From: Yang Zhang yang.z.zh...@intel.com
Since nEPT doesn't support A/D bit, so we should not set those bit
when build shadow page table.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
Signed-off-by: Gleb Natapov g...@redhat.com
---
arch/x86/kvm/mmu.c | 12 +---
From: Nadav Har'El n...@il.ibm.com
kvm_set_cr3() attempts to check if the new cr3 is a valid guest physical
address. The problem is that with nested EPT, cr3 is an *L2* physical
address, not an L1 physical address as this test expects.
As the comment above this test explains, it isn't necessary,
I've compiled the vfio-vga-reset kernel branch, but every time I try to run
mkinitcpio with the -k switch pointing either to the kernel or specifying the
kernel version it says there are no modules to add.
Running up to date Arch Linux. Mkinitcpio works fine with other kernels. Is
there a
On 11.07.2013, at 13:49, Paul Mackerras wrote:
Unlike the other general-purpose SPRs, SPRG3 can be read by usermode
code, and is used in recent kernels to store the CPU and NUMA node
numbers so that they can be read by VDSO functions. Thus we need to
load the guest's SPRG3 value into the
On 25.07.2013, at 15:38, Alexander Graf wrote:
On 11.07.2013, at 13:49, Paul Mackerras wrote:
Unlike the other general-purpose SPRs, SPRG3 can be read by usermode
code, and is used in recent kernels to store the CPU and NUMA node
numbers so that they can be read by VDSO functions. Thus
On 11.07.2013, at 13:50, Paul Mackerras wrote:
Currently PR-style KVM keeps the volatile guest register values
(R0 - R13, CR, LR, CTR, XER, PC) in a shadow_vcpu struct rather than
the main kvm_vcpu struct. For 64-bit, the shadow_vcpu exists in two
places, a kmalloc'd struct and in the PACA,
On 25.07.2013, at 10:50, Gleb Natapov wrote:
On Wed, Jul 24, 2013 at 03:32:49PM -0500, Scott Wood wrote:
On 07/24/2013 04:39:59 AM, Alexander Graf wrote:
On 24.07.2013, at 11:35, Gleb Natapov wrote:
On Wed, Jul 24, 2013 at 11:21:11AM +0200, Alexander Graf wrote:
Are not we going to use
On Thu, Jul 25, 2013 at 06:07:55PM +0200, Alexander Graf wrote:
On 25.07.2013, at 10:50, Gleb Natapov wrote:
On Wed, Jul 24, 2013 at 03:32:49PM -0500, Scott Wood wrote:
On 07/24/2013 04:39:59 AM, Alexander Graf wrote:
On 24.07.2013, at 11:35, Gleb Natapov wrote:
On Wed, Jul 24,
On Thu, Jul 25, 2013 at 4:11 PM, Jan Kiszka jan.kis...@web.de wrote:
On 2013-07-25 07:31, Arthur Chunqi Li wrote:
This is the first version of VMX nested environment. It contains the
basic VMX instructions test cases, including VMXON/VMXOFF/VMXPTRLD/
VMXPTRST/VMCLEAR/VMLAUNCH/VMRESUME/VMCALL.
From: Nadav Har'El n...@il.ibm.com
This is the first patch in a series which adds nested EPT support to KVM's
nested VMX. Nested EPT means emulating EPT for an L1 guest so that L1 can use
EPT when running a nested guest L2. When L1 uses EPT, it allows the L2 guest
to set its own cr3 and take its
This is the first version of VMX nested environment. It contains the
basic VMX instructions test cases, including VMXON/VMXOFF/VMXPTRLD/
VMXPTRST/VMCLEAR/VMLAUNCH/VMRESUME/VMCALL. This patchalso tests the
basic execution routine in VMX nested environment andlet the VM print
Hello World to inform
Arthur Chunqi Li yzt...@gmail.com writes:
This is the first version of VMX nested environment. It contains the
basic VMX instructions test cases, including VMXON/VMXOFF/VMXPTRLD/
VMXPTRST/VMCLEAR/VMLAUNCH/VMRESUME/VMCALL. This patchalso tests the
basic execution routine in VMX nested
On 2013-07-25 18:51, Bandan Das wrote:
Arthur Chunqi Li yzt...@gmail.com writes:
This is the first version of VMX nested environment. It contains the
basic VMX instructions test cases, including VMXON/VMXOFF/VMXPTRLD/
VMXPTRST/VMCLEAR/VMLAUNCH/VMRESUME/VMCALL. This patchalso tests the
basic
On 2013-07-25 18:51, Bandan Das wrote:
Arthur Chunqi Li yzt...@gmail.com writes:
This is the first version of VMX nested environment. It contains the
basic VMX instructions test cases, including VMXON/VMXOFF/VMXPTRLD/
VMXPTRST/VMCLEAR/VMLAUNCH/VMRESUME/VMCALL. This patchalso tests the
https://bugzilla.kernel.org/show_bug.cgi?id=60629
Bug ID: 60629
Summary: Starting a virtual machine ater suspend causes the
host system hangup
Product: Virtualization
Version: unspecified
Kernel Version: 2.6.35-32 - 3.9.9-1
For booke3e _PAGE_ENDIAN is not defined. Infact what is defined
is _PAGE_LENDIAN which is wrong and that should be _PAGE_ENDIAN.
There are no compilation errors as
arch/powerpc/include/asm/pte-common.h defines _PAGE_ENDIAN to 0
as it is not defined anywhere.
Signed-off-by: Bharat Bhushan
E bit in MAS2 bit indicates whether the page is accessed
in Little-Endian or Big-Endian byte order.
There is no reason to stop guest setting E, so allow him.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1 insertions(+), 1
G bit in MAS2 indicates whether the page is Guarded.
There is no reason to stop guest setting G, so allow him.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/e500.h
If the page is RAM then map this as cacheable and coherent (set M bit)
otherwise this page is treated as I/O and map this as cache inhibited
and guarded (set I + G)
This helps setting proper MMU mapping for direct assigned device.
NOTE: There can be devices that require cacheable mapping, which
On 04.07.2013, at 08:57, Bharat Bhushan wrote:
KVM need this function when switching from vcpu to user-space
thread. My subsequent patch will use this function.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
Ben / Michael, please ack.
Alex
---
v5-v6
-
On 11.07.2013, at 13:49, Paul Mackerras wrote:
Unlike the other general-purpose SPRs, SPRG3 can be read by usermode
code, and is used in recent kernels to store the CPU and NUMA node
numbers so that they can be read by VDSO functions. Thus we need to
load the guest's SPRG3 value into the
On 25.07.2013, at 15:38, Alexander Graf wrote:
On 11.07.2013, at 13:49, Paul Mackerras wrote:
Unlike the other general-purpose SPRs, SPRG3 can be read by usermode
code, and is used in recent kernels to store the CPU and NUMA node
numbers so that they can be read by VDSO functions. Thus
On 11.07.2013, at 13:50, Paul Mackerras wrote:
Currently PR-style KVM keeps the volatile guest register values
(R0 - R13, CR, LR, CTR, XER, PC) in a shadow_vcpu struct rather than
the main kvm_vcpu struct. For 64-bit, the shadow_vcpu exists in two
places, a kmalloc'd struct and in the PACA,
On 25.07.2013, at 10:50, Gleb Natapov wrote:
On Wed, Jul 24, 2013 at 03:32:49PM -0500, Scott Wood wrote:
On 07/24/2013 04:39:59 AM, Alexander Graf wrote:
On 24.07.2013, at 11:35, Gleb Natapov wrote:
On Wed, Jul 24, 2013 at 11:21:11AM +0200, Alexander Graf wrote:
Are not we going to use
On Thu, Jul 25, 2013 at 06:07:55PM +0200, Alexander Graf wrote:
On 25.07.2013, at 10:50, Gleb Natapov wrote:
On Wed, Jul 24, 2013 at 03:32:49PM -0500, Scott Wood wrote:
On 07/24/2013 04:39:59 AM, Alexander Graf wrote:
On 24.07.2013, at 11:35, Gleb Natapov wrote:
On Wed, Jul 24,
For booke3e _PAGE_ENDIAN is not defined. Infact what is defined
is _PAGE_LENDIAN which is wrong and that should be _PAGE_ENDIAN.
There are no compilation errors as
arch/powerpc/include/asm/pte-common.h defines _PAGE_ENDIAN to 0
as it is not defined anywhere.
Signed-off-by: Bharat Bhushan
G bit in MAS2 indicates whether the page is Guarded.
There is no reason to stop guest setting G, so allow him.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/e500.h
If the page is RAM then map this as cacheable and coherent (set M bit)
otherwise this page is treated as I/O and map this as cache inhibited
and guarded (set I + G)
This helps setting proper MMU mapping for direct assigned device.
NOTE: There can be devices that require cacheable mapping, which
62 matches
Mail list logo
