On Tue, Jun 17, 2014 at 06:21:23AM +0200, Paolo Bonzini wrote:
Il 16/06/2014 18:47, John Nielsen ha scritto:
On Jun 16, 2014, at 10:39 AM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 16/06/2014 18:09, John Nielsen ha scritto:
The only substantial difference on the hardware side is the CPU.
On 2014-06-16 18:54, Bandan Das wrote:
Jan Kiszka jan.kis...@siemens.com writes:
We already implemented them but failed to advertise them. Currently they
all return the identical values to the capability MSRs they are
augmenting. So there is no change in exposed features yet.
Drop related
On 2014-06-16 18:56, Bandan Das wrote:
Jan Kiszka jan.kis...@siemens.com writes:
SDM says bits 1, 4-6, 8, 13-16, and 26 have to be set.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/x86/include/asm/vmx.h | 3 +++
arch/x86/kvm/vmx.c | 5 +++--
2 files changed, 6
Check for required-0 or required-1 bits as well as known field value
restrictions. Also check the consistency between VMX_*_CTLS and
VMX_TRUE_*_CTLS and between CR0/4_FIXED0 and CR0/4_FIXED1.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
x86/vmx.c | 74
Extend the instruction interception test to also check for
interception-free execution.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
x86/vmx_tests.c | 121 +---
1 file changed, 72 insertions(+), 49 deletions(-)
diff --git
This particularly checks the case when debug controls are not to be
loaded/saved on host-guest transitions.
We have to fake results related to IA32_DEBUGCTL as support for this MSR
is missing KVM. The test already contains all bits required once KVM
adds support.
Signed-off-by: Jan Kiszka
Changes in v2 according to review remarks:
- refactored get/set_stage interface
- unified vmx_ctrl_* unions
- used vmx_ctrl_msr in capability test
- changed commented-out debugctl tests
Jan Kiszka (6):
VMX: Add tests for CR3 and CR8 interception
VMX: Rework test stage interface
VMX: Test
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
x86/vmx.c | 8
x86/vmx.h | 31 +--
2 files changed, 9 insertions(+), 30 deletions(-)
diff --git a/x86/vmx.c b/x86/vmx.c
index ba6a02b..f01e443 100644
--- a/x86/vmx.c
+++ b/x86/vmx.c
@@ -49,10 +49,10 @@
Consistently access the stage only via the helper functions. To enforce
this, move them from vmx_tests.c to vmx.c. At this chance, introduce a
stage incrementation helper.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
x86/vmx.c | 26 ++
x86/vmx.h | 4 +
x86/vmx_tests.c
Need to fix FIELD_* constants for this to make the exit qualification
check work.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
x86/vmx.h | 2 ++
x86/vmx_tests.c | 32 +---
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/x86/vmx.h
Il 17/06/2014 09:04, Jan Kiszka ha scritto:
-#define FIELD_EXIT_QUAL0
-#define FIELD_INSN_INFO1
+#define FIELD_EXIT_QUAL(1 1)
+#define FIELD_INSN_INFO(1 2)
Heh, you probably wanted 10 and 11. I'll fix it up. :)
Paolo
--
To
On 2014-06-17 09:41, Paolo Bonzini wrote:
Il 17/06/2014 09:04, Jan Kiszka ha scritto:
-#define FIELD_EXIT_QUAL0
-#define FIELD_INSN_INFO1
+#define FIELD_EXIT_QUAL(1 1)
+#define FIELD_INSN_INFO(1 2)
Heh, you probably wanted 10 and 11. I'll fix it up. :)
The current platform detection is a little bit messy. We look for lines
in /proc/cpuinfo starting with 'flags' OR 'vendor-id', and scan both
for values we know will only occur in one or the other. We also keep
scanning once we've found a value, which could be a feature, but isn't
in this case.
Unfortunately ioctl numbers are platform specific, so abstract them out
of the code so they can be overridden. As it happens x86 and s390 share
the same values, so nothing needs to change yet.
Signed-off-by: Michael Ellerman m...@ellerman.id.au
---
scripts/kvm/kvm_stat | 12 +---
1 file
Although we have the exit_reasons defined for s390, as far as I can tell
they never take effect. That is because there is no 'kvm_exit'
tracepoint defined for s390.
What is defined, for all platforms, is 'kvm_userspace_exit'. That
tracepoint uses the generic_exit_reason, but the filter parameter
In kvm_stat we grovel through /sys to find out how many cpus are in the
system. However if a cpu is offline it will still be present in /sys,
and the perf_event_open() will fail.
Modify the logic to only return online cpus. We need to be careful on
systems which don't support cpu hotplug, the
In kvm_stat we have a dictionary of exit reasons for s390. Firstly these
are not s390 specific, they are the generic exit reasons. So rename the
dictionary to reflect that.
Secondly, the values are defined using hex, but in the kernel header
they are decimal. That means values above 9 in kvm_stat
Add support for powerpc platforms. We use uname -m, which allows us to
detect ppc, ppc64 and ppc64le/el.
Signed-off-by: Michael Ellerman m...@ellerman.id.au
---
scripts/kvm/kvm_stat | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/scripts/kvm/kvm_stat
Il 17/06/2014 09:04, Jan Kiszka ha scritto:
+ default1 = vmx_ctl_msr[n].default1;
+ ok = (ctrl.set default1) == default1
+ ((ctrl.set ^ ctrl.clr) ~ctrl.clr) == 0;
Thanks, now I can understand what's going on. :) It can still be
simplified
On 17.06.14 09:54, Michael Ellerman wrote:
Add support for powerpc platforms. We use uname -m, which allows us to
detect ppc, ppc64 and ppc64le/el.
Signed-off-by: Michael Ellerman m...@ellerman.id.au
Could you please add support for PR KVM tracepoints along the way? There
we do know the
On 17.06.14 02:51, Paul Mackerras wrote:
On Wed, Jun 11, 2014 at 12:33:46PM +0200, Alexander Graf wrote:
From assembly code we might not only have to explicitly BE access 64bit values,
but sometimes also 32bit ones. Add helpers that allow for easy use of lwzx/stwx
in their respective
On 17.06.14 03:02, Paul Mackerras wrote:
On Wed, Jun 11, 2014 at 12:33:50PM +0200, Alexander Graf wrote:
On the exit path from the guest we check what type of interrupt we received
if we received one. This means we're doing hardware access to the XICS interrupt
controller.
However, when
On 14.06.14 23:08, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host or
On vcpu schedule, the condition checked for tlb pollution is too loose.
The tlb entries of a vcpu become polluted (vs stale) only when a different
vcpu within the same logical partition runs in-between. Optimize the tlb
invalidation condition taking into account the logical partition id.
With the
Hello all,
On 06/17/2014 04:54 AM, Stefan Hajnoczi wrote:
ivshmem has a performance disadvantage for guest-to-host
communication. Since the shared memory is exposed as PCI BARs, the
guest has to memcpy into the shared memory.
vhost-user can access guest memory directly and avoid the copy
On Thu, Jun 12, 2014 at 06:48:14PM +0200, urgrue wrote:
Does anyone have ANY idea where I could find out about market share and
adoption rates of linux hypervisors (kvm vs xen vs vmware, mainly)?
I've not found anything despite extensive searching, which is really kind of
problematic when
On 13.06.14 21:42, Scott Wood wrote:
On Fri, 2014-06-13 at 16:55 +0200, Alexander Graf wrote:
On 13.06.14 16:43, mihai.cara...@freescale.com wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Thursday, June 12, 2014 8:05 PM
To: Caraman Mihai Claudiu-B02008
Cc:
On 12.06.14 05:56, Paul Mackerras wrote:
On Tue, Jun 10, 2014 at 07:23:00PM +0200, Alexander Graf wrote:
When we're using PR KVM we must not allow the CPU to take interrupts
in virtual mode, as the SLB does not contain host kernel mappings
when running inside the guest context.
To make sure
On Tue, 2014-06-17 at 10:54 +0200, Alexander Graf wrote:
Also, why don't we use twi always or something else that actually is
defined as illegal instruction? I would like to see this shared with
book3s_32 PR.
twi will be directed to the guest on HV no ? We want a real illegal
because those
On 17.06.14 11:22, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 10:54 +0200, Alexander Graf wrote:
Also, why don't we use twi always or something else that actually is
defined as illegal instruction? I would like to see this shared with
book3s_32 PR.
twi will be directed to the guest
On Tue, 2014-06-17 at 11:25 +0200, Alexander Graf wrote:
On 17.06.14 11:22, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 10:54 +0200, Alexander Graf wrote:
Also, why don't we use twi always or something else that actually is
defined as illegal instruction? I would like to see this
On 17.06.14 11:32, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 11:25 +0200, Alexander Graf wrote:
On 17.06.14 11:22, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 10:54 +0200, Alexander Graf wrote:
Also, why don't we use twi always or something else that actually is
defined as
Il 17/06/2014 11:03, David Marchand ha scritto:
Unless someone steps up and maintains ivshmem, I think it should be
deprecated and dropped from QEMU.
Then I can maintain ivshmem for QEMU.
If this is ok, I will send a patch for MAINTAINERS file.
Typically, adding yourself to maintainers is
When we're using PR KVM we must not allow the CPU to take interrupts
in virtual mode, as the SLB does not contain host kernel mappings
when running inside the guest context.
To make sure we get good performance for non-KVM tasks but still
properly functioning PR KVM, let's just disable AIL
On Tue, Jun 17, 2014 at 12:03:58PM +0200, Alexander Graf wrote:
When we're using PR KVM we must not allow the CPU to take interrupts
in virtual mode, as the SLB does not contain host kernel mappings
when running inside the guest context.
To make sure we get good performance for non-KVM tasks
On 17.06.14 10:37, Alexander Graf wrote:
On 17.06.14 03:02, Paul Mackerras wrote:
On Wed, Jun 11, 2014 at 12:33:50PM +0200, Alexander Graf wrote:
On the exit path from the guest we check what type of interrupt we
received
if we received one. This means we're doing hardware access to the
I see kernel 3.15 is now out, so I retested with 3.15 guest and host. I'm
still getting exactly the same guest kernel panic: a divide error in
kvm_unlock_kick with -cpu host, but not with -cpu qemu64:
divide error: [#1] PREEMPT SMP
Modules linked in:
CPU: 1 PID: 781 Comm: mkdir Not tainted
On Tuesday 17 June 2014 02:24 PM, Alexander Graf wrote:
On 14.06.14 23:08, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the
On 17.06.14 13:07, Madhavan Srinivasan wrote:
On Tuesday 17 June 2014 02:24 PM, Alexander Graf wrote:
On 14.06.14 23:08, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation
On Tuesday 17 June 2014 03:02 PM, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 11:25 +0200, Alexander Graf wrote:
On 17.06.14 11:22, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 10:54 +0200, Alexander Graf wrote:
Also, why don't we use twi always or something else that actually
On Tuesday 17 June 2014 04:38 PM, Alexander Graf wrote:
On 17.06.14 13:07, Madhavan Srinivasan wrote:
On Tuesday 17 June 2014 02:24 PM, Alexander Graf wrote:
On 14.06.14 23:08, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using
On Tuesday 17 June 2014 03:13 PM, Alexander Graf wrote:
On 17.06.14 11:32, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 11:25 +0200, Alexander Graf wrote:
On 17.06.14 11:22, Benjamin Herrenschmidt wrote:
On Tue, 2014-06-17 at 10:54 +0200, Alexander Graf wrote:
Also, why don't we use
Hi
Please, send any topic that you are interested in covering.
* Machine as QOM (Marcel) (repeat)
- Solve the 'sensible' issues.
- Choose as first tasks the ones that will be more useful.
- Select solutions agreed by everyone.
Thanks, Juan.
Call details:
15:00 CEST
13:00 UTC
09:00 EDT
Hello,
I have a question related to KVM_IRQFD and KVM_SET_GSI_ROUTING ioctl
relationship.
When reading the KVM API documentation I do not understand there is any
dependency between KVM_IRQFD and KVM_SET_GSI_ROUTING. According to the
text it seems only the gsi field is used and interpreted as the
On 06/06/2014 02:16 PM, Christoffer Dall wrote:
On Mon, Jun 02, 2014 at 02:54:12PM +0100, Marc Zyngier wrote:
Hi Eric,
On Mon, Jun 02 2014 at 8:29:56 am BST, Eric Auger eric.au...@linaro.org
wrote:
This patch enables irqfd and irq routing on ARM.
It turns on CONFIG_HAVE_KVM_EVENTFD and
On Thu, Apr 17, 2014 at 04:17:42PM +0200, Andrew Jones wrote:
Signed-off-by: Andrew Jones drjo...@redhat.com
---
x86/unittests.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/x86/unittests.cfg b/x86/unittests.cfg
index 7930c026a38d6..d78fe0eafe2b6 100644
---
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Tuesday, June 17, 2014 12:09 PM
To: Wood Scott-B07421
Cc: Caraman Mihai Claudiu-B02008; kvm-...@vger.kernel.org;
kvm@vger.kernel.org; linuxppc-...@lists.ozlabs.org
Subject: Re: [PATCH] KVM: PPC: e500mc: Relax tlb
Juan Quintela quint...@redhat.com wrote:
Hi
I sent the first mail to the wrong address, please notice that
qemu-devel was missing). Fixed in this resent.
Sorry for the inconveniences.
Later, Juan.
Please, send any topic that you are interested in covering.
* Machine as QOM (Marcel)
On Tue, Jun 17, 2014 at 12:22:32PM +0200, Alexander Graf wrote:
Eh, no. What we do is we read (good on BE, byte reversed) into r0. Then we
swab32() from r0 to r3 on LE, mr from r0 to r3 on BE.
r3 gets truncated along the way.
The reason we maintain r0 as wrong-endian is that we write it
On 17.06.14 14:13, Paul Mackerras wrote:
On Tue, Jun 17, 2014 at 12:22:32PM +0200, Alexander Graf wrote:
Eh, no. What we do is we read (good on BE, byte reversed) into r0. Then we
swab32() from r0 to r3 on LE, mr from r0 to r3 on BE.
r3 gets truncated along the way.
The reason we maintain r0
Add report_skip(), which is report(), but with another condition
allowing it to output PASS/FAIL/SKIP, rather than only PASS/FAIL.
This allows report output to stay more consistent between
systems/configurations that may or may not support all tests.
Currently I only have a downstream use case for
Il 17/06/2014 14:21, Andrew Jones ha scritto:
would look better as
report(msg1, cond1) - FAIL
report_skip(msg2, !cond1, cond1 cond2) - SKIP
report_skip(msg3, !cond1, cond1 cond3) - SKIP
I think a lot of the time there is other code before the report that
On Tue, Jun 17, 2014 at 02:46:30PM +0200, Paolo Bonzini wrote:
Il 17/06/2014 14:21, Andrew Jones ha scritto:
would look better as
report(msg1, cond1) - FAIL
report_skip(msg2, !cond1, cond1 cond2) - SKIP
report_skip(msg3, !cond1, cond1 cond3) - SKIP
I
Add report_xfail(), which is report(), but with another condition
allowing it to output PASS/FAIL/XPASS/XFAIL, rather than only
PASS/FAIL. This allows report output to stay more consistent
between systems/configurations that may or may not support all
tests.
Signed-off-by: Andrew Jones
On 17.06.14 13:13, Madhavan Srinivasan wrote:
On Tuesday 17 June 2014 04:38 PM, Alexander Graf wrote:
On 17.06.14 13:07, Madhavan Srinivasan wrote:
On Tuesday 17 June 2014 02:24 PM, Alexander Graf wrote:
On 14.06.14 23:08, Madhavan Srinivasan wrote:
This patch adds kernel side support for
On Tue, 2014-06-17 at 12:02 +0300, Mihai Caraman wrote:
On vcpu schedule, the condition checked for tlb pollution is too loose.
The tlb entries of a vcpu become polluted (vs stale) only when a different
vcpu within the same logical partition runs in-between. Optimize the tlb
invalidation
On Thu, 2014-06-12 at 19:04 +0200, Alexander Graf wrote:
On 06/12/2014 04:00 PM, Mihai Caraman wrote:
@@ -140,12 +142,24 @@ static void kvmppc_core_vcpu_load_e500mc(struct
kvm_vcpu *vcpu, int cpu)
mtspr(SPRN_GDEAR, vcpu-arch.shared-dar);
mtspr(SPRN_GESR, vcpu-arch.shared-esr);
Paolo Bonzini pbonz...@redhat.com writes:
Il 16/06/2014 19:38, Bandan Das ha scritto:
Nadav Amit na...@cs.technion.ac.il writes:
The emulator does not emulate the xadd instruction correctly if the two
operands are the same. In this (unlikely) situation the result should be
the
sum of X
If we're running PR KVM in HV mode, we may get hypervisor doorbell interrupts.
Handle those the same way we treat normal doorbells.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/book3s_pr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kvm/book3s_pr.c
On 12.06.14 10:16, Anton Blanchard wrote:
To establish addressability quickly, ABIv2 requires the target
address of the function being called to be in r12.
Signed-off-by: Anton Blanchard an...@samba.org
Thanks, applied to kvm-ppc-queue.
Alex
---
Index:
On 12.06.14 10:16, Anton Blanchard wrote:
Both kvmppc_hv_entry_trampoline and kvmppc_entry_trampoline are
assembly functions that are exported to modules and also require
a valid r2.
As such we need to use _GLOBAL_TOC so we provide a global entry
point that establishes the TOC (r2).
We switched to ABIv2 on Little Endian systems now which gets rid of the
dotted function names. Branch to the actual functions when we see such
a system.
Signed-off-by: Alexander Graf ag...@suse.de
diff --git a/arch/powerpc/kvm/book3s_interrupts.S
b/arch/powerpc/kvm/book3s_interrupts.S
index
When running on an LE host all data structures are kept in little endian
byte order. However, the HTAB still needs to be maintained in big endian.
So every time we access any HTAB we need to make sure we do so in the right
byte order. Fix up all accesses to manually byte swap.
Signed-off-by:
There are a few shared data structures between the host and the guest. Most
of them get registered through the VPA interface.
These data structures are defined to always be in big endian byte order, so
let's make sure we always access them in big endian.
Signed-off-by: Alexander Graf
Now that we've fixed all the issues that HV KVM code had on little endian
hosts, we can enable it in the kernel configuration for users to play with.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git
Some data structures are always stored in big endian. Among those are the LPPACA
fields as well as the shadow slb. These structures might be shared with a
hypervisor.
So whenever we access those fields, make sure we do so in big endian byte order.
Signed-off-by: Alexander Graf ag...@suse.de
---
On the exit path from the guest we check what type of interrupt we received
if we received one. This means we're doing hardware access to the XICS interrupt
controller.
However, when running on a little endian system, this access is byte reversed.
So let's make sure to swizzle the bytes back
From assembly code we might not only have to explicitly BE access 64bit values,
but sometimes also 32bit ones. Add helpers that allow for easy use of lwzx/stwx
in their respective byte-reverse or native form.
Signed-off-by: Alexander Graf ag...@suse.de
CC: Benjamin Herrenschmidt
So far we've been able to successfully run HV KVM on big endian hosts, but
once you dive into little endian land things start to fall apart.
This patch set enables HV KVM for little endian hosts. This should be the
final piece left missing to get little endian systems fully en par with big
endian
We use ABIv2 on Little Endian systems which gets rid of the dotted function
names. Branch to the actual functions when we see such a system.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 22 ++
1 file changed, 14 insertions(+), 8
Il 17/06/2014 17:35, Bandan Das ha scritto:
Well, I meant it more as a review and suggested changes to this patchset
Nadav posted, but yeah, if you prefer, I can post a change myself. I will
make a pass through other uses of BUG() in the code too.
I'd prefer that, there's no need to make Nadav
On Jun 17, 2014, at 12:05 AM, Gleb Natapov g...@kernel.org wrote:
On Tue, Jun 17, 2014 at 06:21:23AM +0200, Paolo Bonzini wrote:
Il 16/06/2014 18:47, John Nielsen ha scritto:
On Jun 16, 2014, at 10:39 AM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 16/06/2014 18:09, John Nielsen ha scritto:
From: Nikolay Nikolaev n.nikol...@virtualopensystems.com
Add a function to check if the eventfd capability is present in KVM in
the host kernel.
Signed-off-by: Antonios Motakis a.mota...@virtualopensystems.com
Signed-off-by: Nikolay Nikolaev n.nikol...@virtualopensystems.com
Reviewed-by: Michael
Il 17/06/2014 16:36, Andrew Jones ha scritto:
Add report_xfail(), which is report(), but with another condition
allowing it to output PASS/FAIL/XPASS/XFAIL, rather than only
PASS/FAIL. This allows report output to stay more consistent
between systems/configurations that may or may not support
Il 17/04/2014 16:17, Andrew Jones ha scritto:
Signed-off-by: Andrew Jones drjo...@redhat.com
---
x86/unittests.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/x86/unittests.cfg b/x86/unittests.cfg
index 7930c026a38d6..d78fe0eafe2b6 100644
--- a/x86/unittests.cfg
+++
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, June 17, 2014 6:36 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH v2] KVM: PPC: e500mc: Enhance tlb invalidation
condition on vcpu
On Tue, 2014-06-17 at 14:04 -0500, Caraman Mihai Claudiu-B02008 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, June 17, 2014 6:36 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject:
On vcpu schedule, the condition checked for tlb pollution is too loose.
The tlb entries of a vcpu become polluted (vs stale) only when a different
vcpu within the same logical partition runs in-between. Optimize the tlb
invalidation condition keeping last_vcpu_on_cpu per logical partition id.
On Tue, 2014-06-17 at 22:09 +0300, Mihai Caraman wrote:
On vcpu schedule, the condition checked for tlb pollution is too loose.
The tlb entries of a vcpu become polluted (vs stale) only when a different
vcpu within the same logical partition runs in-between. Optimize the tlb
invalidation
-static DEFINE_PER_CPU(struct kvm_vcpu *, last_vcpu_on_cpu);
+static DEFINE_PER_CPU(struct kvm_vcpu * [KVMPPC_NR_LPIDS],
last_vcpu_on_cpu);
Hmm, I didn't know you could express types like that. Is this special
syntax that only works for typeof?
Yes, AFAIK.
No space after *
Checkpatch
On Tue, 2014-06-17 at 14:42 -0500, Caraman Mihai Claudiu-B02008 wrote:
-static DEFINE_PER_CPU(struct kvm_vcpu *, last_vcpu_on_cpu);
+static DEFINE_PER_CPU(struct kvm_vcpu * [KVMPPC_NR_LPIDS],
last_vcpu_on_cpu);
Hmm, I didn't know you could express types like that. Is this special
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, June 17, 2014 10:48 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH v3] KVM: PPC: e500mc: Enhance tlb invalidation
condition on vcpu
+ new = tail | (val _Q_LOCKED_MASK);
+
+ old = atomic_cmpxchg(lock-val, val, new);
+ if (old == val)
+ break;
+
+ val = old;
+ }
+
+ /*
+* we won the trylock; forget about queueing.
+*/
+ if
On Tue, 2014-06-17 at 15:02 -0500, Caraman Mihai Claudiu-B02008 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, June 17, 2014 10:48 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject:
+ * The basic principle of a queue-based spinlock can best be understood
+ * by studying a classic queue-based spinlock implementation called the
+ * MCS lock. The paper below provides a good description for this kind
+ * of lock.
+ *
+ * http://www.cise.ufl.edu/tr/DOC/REP-1992-71.pdf
+ *
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, June 17, 2014 11:05 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH v3] KVM: PPC: e500mc: Enhance tlb invalidation
condition on vcpu
On Sun, Jun 15, 2014 at 02:47:00PM +0200, Peter Zijlstra wrote:
Because the qspinlock needs to touch a second cacheline; add a pending
bit and allow a single in-word spinner before we punt to the second
cacheline.
Could you add this in the description please:
And by second cacheline we mean
On 17.06.14 22:36, mihai.cara...@freescale.com wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, June 17, 2014 11:05 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH v3] KVM: PPC:
On 06/17/2014 04:36 PM, Konrad Rzeszutek Wilk wrote:
On Sun, Jun 15, 2014 at 02:47:00PM +0200, Peter Zijlstra wrote:
Because the qspinlock needs to touch a second cacheline; add a pending
bit and allow a single in-word spinner before we punt to the second
cacheline.
Could you add this in the
On Sun, Jun 15, 2014 at 02:47:01PM +0200, Peter Zijlstra wrote:
From: Waiman Long waiman.l...@hp.com
This patch extracts the logic for the exchange of new and previous tail
code words into a new xchg_tail() function which can be optimized in a
later patch.
And also adds a third try on
On Tue, Jun 17, 2014 at 04:51:57PM -0400, Waiman Long wrote:
On 06/17/2014 04:36 PM, Konrad Rzeszutek Wilk wrote:
On Sun, Jun 15, 2014 at 02:47:00PM +0200, Peter Zijlstra wrote:
Because the qspinlock needs to touch a second cacheline; add a pending
bit and allow a single in-word spinner before
On Sun, Jun 15, 2014 at 03:16:54PM +0200, Peter Zijlstra wrote:
On Thu, Jun 12, 2014 at 04:48:41PM -0400, Waiman Long wrote:
I don't have a good understanding of the kernel alternatives mechanism.
I didn't either; I do now, cost me a whole day reading up on
alternative/paravirt code
On Tue, Jun 17, 2014 at 05:07:29PM -0400, Konrad Rzeszutek Wilk wrote:
On Tue, Jun 17, 2014 at 04:51:57PM -0400, Waiman Long wrote:
On 06/17/2014 04:36 PM, Konrad Rzeszutek Wilk wrote:
On Sun, Jun 15, 2014 at 02:47:00PM +0200, Peter Zijlstra wrote:
Because the qspinlock needs to touch a
When KVM is enabled call kvm_mips_reset_vcpu() from mips_cpu_reset() as
done for other targets since commit 50a2c6e55fa2 (kvm: reset state from
the CPU's reset method).
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Aurelien Jarno aurel...@aurel32.net
Cc: Paolo Bonzini pbonz...@redhat.com
From: Sanjay Lal sanj...@kymasys.com
COP0 emulation is in-kernel for KVM, so inject IRQ2 (I/O) interrupts via
ioctls.
Signed-off-by: Sanjay Lal sanj...@kymasys.com
Signed-off-by: James Hogan james.ho...@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
Reviewed-by: Andreas Färber
MIPS/Linux is unusual in having 128 signals rather than just 64 like
most other architectures. This means its sigmask is 16 bytes instead of
8, so allow arches to override the sigmask-len value passed to the
KVM_SET_SIGNAL_MASK ioctl in kvm_set_signal_mask() by calling
kvm_set_sigmask_len() from
Add MAINTAINERS entry for MIPS KVM.
Signed-off-by: James Hogan james.ho...@imgtec.com
---
Changes in v4:
- Add MAINTAINERS entry for MIPS KVM.
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 51a6f51842be..0a637c90c679 100644
---
From: Sanjay Lal sanj...@kymasys.com
Add API for converting physical addresses to KVM guest KSEG0 addresses,
and fix the existing API for converting KSEG0 addresses to physical
addresses to work in the KVM case. Both have the same sized KSEG0, so
it's just a case of fixing the mask.
In KVM trap
From: Sanjay Lal sanj...@kymasys.com
Compare/Count timer interrupts are handled in-kernel for KVM. Therefore
don't bother creating the timer at init time if KVM is enabled. This
will conveniently avoid attempts to set the timeout when
cpu_mips_store_count() is called at reset with KVM enabled,
The MIPS CPU timer (CP0 Count/Compare registers QEMU timer) is
reset at machine initialisation, including starting the timeout. Both
registers however are placed before mvp in CPUMIPSState so they will
both be zeroed on reset by the memset in mips_cpu_reset() including soon
after init. This
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