[PATCH v2 0/6] x86, apicv: Add APIC virtualizatin support

. Changes v1 to v2: * Add Posted Interrupt support in this series patch. * Since there is a notifer hook in vAPIC EOI for PIT interrupt. So always Set PIT interrupt in eoi exit bitmap to force vmexit when EOI to interrupt. * Rebased on top of KVM upstream Yang Zhang (6): x86: PIT connects

[PATCH v2 1/6] x86: PIT connects to pin 2 of IOAPIC

When PIT connects to IOAPIC, it route to pin 2 not pin 0. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- virt/kvm/ioapic.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/virt/kvm/ioapic.c b/virt/kvm/ioapic.c index cfb7e4d..166c450 100644 --- a/virt/kvm/ioapic.c

[PATCH v2 6/6] x86, apicv: Add Posted Interrupt supporting

automatically, without any software involvemnt. - If target vcpu is not running or there already a notification event pending in the vcpu, do nothing. The interrupt will be handled by old way. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/kvm_host.h |3 + arch/x86

[PATCH v2 2/6] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Yang Zhang yang.z.zh...@intel.com Signed-off-by: Kevin Tian kevin.t...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 16 arch/x86/kvm/lapic.h |2

[PATCH v2 5/6] x86: Enable ack interrupt on vmexit

self ipi. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/kvm/vmx.c | 11 ++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 7949d21..f6ef090 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -2525,7

[PATCH v2 3/6] x86, apicv: add virtual interrupt delivery support

-by: Yang Zhang yang.z.zh...@intel.com Signed-off-by: Kevin Tian kevin.t...@intel.com --- arch/x86/include/asm/kvm_host.h |4 + arch/x86/include/asm/vmx.h | 11 arch/x86/kvm/irq.c | 44 ++ arch/x86/kvm/lapic.c| 44 +- arch/x86/kvm

[PATCH v2 4/6] x86, apicv: add virtual x2apic support

basically to benefit from apicv, we need clear MSR bitmap for corresponding x2apic MSRs: 0x800 - 0x8ff: no read intercept for apicv register virtualization TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86

[PATCH v3 0/4] x86, apicv: Add APIC virtualization support

bitmap to force vmexit when EOI to interrupt. * Rebased on top of KVM upstream Yang Zhang (4): x86: PIT connects to pin 2 of IOAPIC x86, apicv: add APICv register virtualization support x86, apicv: add virtual interrupt delivery support x86, apicv: add virtual x2apic support arch/x86/include

[PATCH v3 2/4] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Yang Zhang yang.z.zh...@intel.com Signed-off-by: Kevin Tian kevin.t...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 16 arch/x86/kvm/lapic.h |2

[PATCH v3 1/4] x86: PIT connects to pin 2 of IOAPIC

When PIT connects to IOAPIC, it route to pin 2 not pin 0. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- virt/kvm/ioapic.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/virt/kvm/ioapic.c b/virt/kvm/ioapic.c index cfb7e4d..166c450 100644 --- a/virt/kvm/ioapic.c

[PATCH v3 4/4] x86, apicv: add virtual x2apic support

basically to benefit from apicv, we need clear MSR bitmap for corresponding x2apic MSRs: 0x800 - 0x8ff: no read intercept for apicv register virtualization TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery Signed-off-by: Yang Zhang yang.z.zh...@intel.com Signed-off

[PATCH v3 3/4] x86, apicv: add virtual interrupt delivery support

-by: Yang Zhang yang.z.zh...@intel.com Signed-off-by: Kevin Tian kevin.t...@intel.com --- arch/x86/include/asm/kvm_host.h |4 + arch/x86/include/asm/vmx.h | 11 +++ arch/x86/kvm/irq.c | 53 ++- arch/x86/kvm/lapic.c| 56 +--- arch/x86/kvm

[PATCH v4 1/2] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 15 +++ arch/x86/kvm/lapic.h |2 ++ arch

[PATCH v4 2/2] x86, apicv: add virtual interrupt delivery support

-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/kvm_host.h |4 + arch/x86/include/asm/vmx.h | 11 arch/x86/kvm/irq.c | 79 +++- arch/x86/kvm/lapic.c| 101

[PATCH v4 0/2] x86, apicv: Add APIC virtualization support

upstream Yang Zhang (2): x86, apicv: add APICv register virtualization support x86, apicv: add virtual interrupt delivery support arch/x86/include/asm/kvm_host.h |4 + arch/x86/include/asm/vmx.h | 13 arch/x86/kvm/irq.c | 79 - arch/x86/kvm/lapic.c

[RESEND PATCH v4 0/3] x86, apicv: Add APIC virtualization support

From: Yang Zhang yang.z.zh...@intel.com APIC virtualization is a new feature which can eliminate most of VM exit when vcpu handle a interrupt: APIC register virtualization: APIC read access doesn't cause APIC-access VM exits. APIC write becomes trap-like. Virtual interrupt

[RESEND PATCH v4 1/3] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 15 +++ arch/x86/kvm/lapic.h |2 ++ arch/x86/kvm/vmx.c | 33

[RESEND PATCH v4 2/3] x86, apicv: add virtual interrupt delivery support

-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/kvm_host.h |4 + arch/x86/include/asm/vmx.h | 11 arch/x86/kvm/irq.c | 79 +-- arch/x86/kvm/lapic.c| 101

[RESEND PATCH v4 3/3] x86, apicv: add virtual x2apic support

basically to benefit from apicv, we need clear MSR bitmap for corresponding x2apic MSRs: 0x800 - 0x8ff: no read intercept for apicv register virtualization TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery Signed-off-by: Yang Zhang yang.z.zh...@intel.com Signed-off

[PATCH v5 0/3] x86, apicv: Add APIC virtualization support

From: Yang Zhang yang.z.zh...@intel.com APIC virtualization is a new feature which can eliminate most of VM exit when vcpu handle a interrupt: APIC register virtualization: APIC read access doesn't cause APIC-access VM exits. APIC write becomes trap-like. Virtual interrupt

[PATCH v5 1/3] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 15 +++ arch/x86/kvm/lapic.h |2 ++ arch

[PATCH v5 2/3] x86, apicv: add virtual interrupt delivery support

-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/ia64/kvm/lapic.h |6 ++ arch/x86/include/asm/kvm_host.h |5 ++ arch/x86/include/asm/vmx.h | 11 arch/x86/kvm/irq.c | 76 ++-- arch/x86/kvm

[PATCH v5 3/3] x86, apicv: add virtual x2apic support

basically to benefit from apicv, we need clear MSR bitmap for corresponding x2apic MSRs: 0x800 - 0x8ff: no read intercept for apicv register virtualization TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery Signed-off-by: Yang Zhang yang.z.zh...@intel.com Signed-off

[PATCH v6 0/3] x86, apicv: Add APIC virtualization support

From: Yang Zhang yang.z.zh...@intel.com APIC virtualization is a new feature which can eliminate most of VM exit when vcpu handle a interrupt: APIC register virtualization: APIC read access doesn't cause APIC-access VM exits. APIC write becomes trap-like. Virtual interrupt

[PATCH v6 1/3] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 15 +++ arch/x86/kvm/lapic.h |2 ++ arch

[PATCH] KVM: remove a wrong hack of delivery PIT intr to vcpu0

From: Yang Zhang yang.z.zh...@intel.com This hack is wrong. The pin number of PIT is connected to 2 not 0. This means this hack never takes effect. So it is ok to remove it. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- virt/kvm/ioapic.c |9 - 1 files changed, 0 insertions

[PATCH 0/2] KVM: Add posted interrupt supporting

From: Yang Zhang yang.z.zh...@intel.com Posted Interrupt allows APIC interrupts to inject directly to guest VMM's involvement. When deliverying an virtual interrupt, VMM needn't to send an IPI to kick down target vcpu. Instead, send a notification event to the PCPU and hardware will inject

[PATCH 1/2] x86: Enable ack interrupt on vmexit

From: Yang Zhang yang.z.zh...@intel.com Ack interrupt on vmexit is required by Posted Interrupt. With it, when external interrupt caused vmexit, the cpu will acknowledge the interrupt controller and save the interrupt's vector in vmcs. Only enable it when posted interrupt is enabled

[PATCH 2/2] x86, apicv: Add Posted Interrupt supporting

From: Yang Zhang yang.z.zh...@intel.com Posted Interrupt allows APIC interrupts to inject into guest directly without any vmexit. - When delivering a interrupt to guest, if target vcpu is running, update Posted-interrupt requests bitmap and send a notification event to the vcpu

[PATCH v7 0/3] x86, apicv: Add APIC virtualization support

From: Yang Zhang yang.z.zh...@intel.com APIC virtualization is a new feature which can eliminate most of VM exit when vcpu handle a interrupt: APIC register virtualization: APIC read access doesn't cause APIC-access VM exits. APIC write becomes trap-like. Virtual interrupt

[PATCH v7 1/3] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 15 +++ arch/x86/kvm/lapic.h |2 ++ arch

[PATCH v7 3/3] x86, apicv: add virtual x2apic support

basically to benefit from apicv, we need clear MSR bitmap for corresponding x2apic MSRs: 0x800 - 0x8ff: no read intercept for apicv register virtualization TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery Signed-off-by: Yang Zhang yang.z.zh...@intel.com Signed-off

[PATCH v7 2/3] x86, apicv: add virtual interrupt delivery support

From: Yang Zhang yang.z.zh...@intel.com Virtual interrupt delivery avoids KVM to inject vAPIC interrupts manually, which is fully taken care of by the hardware. This needs some special awareness into existing interrupr injection path: - for pending interrupt, instead of direct injection, we may

[PATCH v8 1/3] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 15 +++ arch/x86/kvm/lapic.h |2 ++ arch

[PATCH v8 3/3] x86, apicv: add virtual x2apic support

From: Yang Zhang yang.z.zh...@intel.com basically to benefit from apicv, we need clear MSR bitmap for corresponding x2apic MSRs when guest enabled x2apic: 0x800 - 0x8ff: no read intercept for apicv register virtualization TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery

[PATCH v8 0/3] x86, apicv: Add APIC virtualization support

From: Yang Zhang yang.z.zh...@intel.com APIC virtualization is a new feature which can eliminate most of VM exit when vcpu handle a interrupt: APIC register virtualization: APIC read access doesn't cause APIC-access VM exits. APIC write becomes trap-like. Virtual interrupt

[PATCH v8 2/3] x86, apicv: add virtual interrupt delivery support

From: Yang Zhang yang.z.zh...@intel.com Virtual interrupt delivery avoids KVM to inject vAPIC interrupts manually, which is fully taken care of by the hardware. This needs some special awareness into existing interrupr injection path: - for pending interrupt, instead of direct injection, we may

[PATCH v9 0/3] x86, apicv: Add APIC virtualization support

From: Yang Zhang yang.z.zh...@intel.com APIC virtualization is a new feature which can eliminate most of VM exit when vcpu handle a interrupt: APIC register virtualization: APIC read access doesn't cause APIC-access VM exits. APIC write becomes trap-like. Virtual interrupt

[PATCH v9 1/3] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 15 +++ arch/x86/kvm/lapic.h |2 ++ arch

[PATCH v9 3/3] x86, apicv: add virtual interrupt delivery support

From: Yang Zhang yang.z.zh...@intel.com Virtual interrupt delivery avoids KVM to inject vAPIC interrupts manually, which is fully taken care of by the hardware. This needs some special awareness into existing interrupr injection path: - for pending interrupt, instead of direct injection, we may

[PATCH v9 2/3] x86, apicv: add virtual x2apic support

From: Yang Zhang yang.z.zh...@intel.com basically to benefit from apicv, we need to enable virtualized x2apic mode. Currently, we only enable it when guest is really using x2apic. Also, clear MSR bitmap for corresponding x2apic MSRs when guest enabled x2apic: 0x800 - 0x8ff: no read intercept

[PATCH v10 0/3] x86, apicv: Add APIC virtualization support

From: Yang Zhang yang.z.zh...@intel.com APIC virtualization is a new feature which can eliminate most of VM exit when vcpu handle a interrupt: APIC register virtualization: APIC read access doesn't cause APIC-access VM exits. APIC write becomes trap-like. Virtual interrupt

[PATCH v10 1/3] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 15 +++ arch/x86/kvm/lapic.h |2 ++ arch

[PATCH v10 2/3] x86, apicv: add virtual x2apic support

From: Yang Zhang yang.z.zh...@intel.com basically to benefit from apicv, we need to enable virtualized x2apic mode. Currently, we only enable it when guest is really using x2apic. Also, clear MSR bitmap for corresponding x2apic MSRs when guest enabled x2apic: 0x800 - 0x8ff: no read intercept

[PATCH v10 3/3] x86, apicv: add virtual interrupt delivery support

From: Yang Zhang yang.z.zh...@intel.com Virtual interrupt delivery avoids KVM to inject vAPIC interrupts manually, which is fully taken care of by the hardware. This needs some special awareness into existing interrupr injection path: - for pending interrupt, instead of direct injection, we may

[PATCH] KVM: VMX: enable acknowledge interupt on vmexit

From: Yang Zhang yang.z.zh...@intel.com The acknowledge interrupt on exit feature controls processor behavior for external interrupt acknowledgement. When this control is set, the processor acknowledges the interrupt controller to acquire the interrupt vector on VM exit. This feature is required

[PATCH v11 0/3] x86, apicv: Add APIC virtualization support

From: Yang Zhang yang.z.zh...@intel.com APIC virtualization is a new feature which can eliminate most of VM exit when vcpu handle a interrupt: APIC register virtualization: APIC read access doesn't cause APIC-access VM exits. APIC write becomes trap-like. Virtual interrupt

[PATCH v11 1/3] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 15 +++ arch/x86/kvm/lapic.h |2 ++ arch

[PATCH v11 2/3] x86, apicv: add virtual x2apic support

From: Yang Zhang yang.z.zh...@intel.com basically to benefit from apicv, we need to enable virtualized x2apic mode. Currently, we only enable it when guest is really using x2apic. Also, clear MSR bitmap for corresponding x2apic MSRs when guest enabled x2apic: 0x800 - 0x8ff: no read intercept

[PATCH v11 3/3] x86, apicv: add virtual interrupt delivery support

From: Yang Zhang yang.z.zh...@intel.com Virtual interrupt delivery avoids KVM to inject vAPIC interrupts manually, which is fully taken care of by the hardware. This needs some special awareness into existing interrupr injection path: - for pending interrupt, instead of direct injection, we may

[PATCH v2] KVM: VMX: enable acknowledge interupt on vmexit

From: Yang Zhang yang.z.zh...@intel.com The acknowledge interrupt on exit feature controls processor behavior for external interrupt acknowledgement. When this control is set, the processor acknowledges the interrupt controller to acquire the interrupt vector on VM exit. After enabling

[PATCH v12 0/3] x86, apicv: Add APIC virtualization support

From: Yang Zhang yang.z.zh...@intel.com APIC virtualization is a new feature which can eliminate most of VM exit when vcpu handle a interrupt: APIC register virtualization: APIC read access doesn't cause APIC-access VM exits. APIC write becomes trap-like. Virtual interrupt

[PATCH v12 1/3] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 15 +++ arch/x86/kvm/lapic.h |2 ++ arch

[PATCH v12 2/3] x86, apicv: add virtual x2apic support

From: Yang Zhang yang.z.zh...@intel.com basically to benefit from apicv, we need to enable virtualized x2apic mode. Currently, we only enable it when guest is really using x2apic. Also, clear MSR bitmap for corresponding x2apic MSRs when guest enabled x2apic: 0x800 - 0x8ff: no read intercept

[PATCH v12 3/3] x86, apicv: add virtual interrupt delivery support

From: Yang Zhang yang.z.zh...@intel.com Virtual interrupt delivery avoids KVM to inject vAPIC interrupts manually, which is fully taken care of by the hardware. This needs some special awareness into existing interrupr injection path: - for pending interrupt, instead of direct injection, we may

[PATCH v13 2/3] x86, apicv: add virtual x2apic support

From: Yang Zhang yang.z.zh...@intel.com basically to benefit from apicv, we need to enable virtualized x2apic mode. Currently, we only enable it when guest is really using x2apic. Also, clear MSR bitmap for corresponding x2apic MSRs when guest enabled x2apic: 0x800 - 0x8ff: no read intercept

[PATCH v13 1/3] x86, apicv: add APICv register virtualization support

- APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Kevin Tian kevin.t...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |2 ++ arch/x86/kvm/lapic.c | 15 +++ arch/x86/kvm/lapic.h |2 ++ arch

[PATCH v13 0/3] x86, apicv: Add APIC virtualization support

From: Yang Zhang yang.z.zh...@intel.com APIC virtualization is a new feature which can eliminate most of VM exit when vcpu handle a interrupt: APIC register virtualization: APIC read access doesn't cause APIC-access VM exits. APIC write becomes trap-like. Virtual interrupt

[PATCH v13 3/3] x86, apicv: add virtual interrupt delivery support

From: Yang Zhang yang.z.zh...@intel.com Virtual interrupt delivery avoids KVM to inject vAPIC interrupts manually, which is fully taken care of by the hardware. This needs some special awareness into existing interrupr injection path: - for pending interrupt, instead of direct injection, we may

[PATCH v3] KVM: VMX: enable acknowledge interupt on vmexit

From: Yang Zhang yang.z.zh...@intel.com The acknowledge interrupt on exit feature controls processor behavior for external interrupt acknowledgement. When this control is set, the processor acknowledges the interrupt controller to acquire the interrupt vector on VM exit. After enabling

[PATCH v4] KVM: VMX: enable acknowledge interupt on vmexit

From: Yang Zhang yang.z.zh...@intel.com The acknowledge interrupt on exit feature controls processor behavior for external interrupt acknowledgement. When this control is set, the processor acknowledges the interrupt controller to acquire the interrupt vector on VM exit. After enabling

[PATCH v2 0/2] KVM: VMX: Add Posted Interrupt supporting

From: Yang Zhang yang.z.zh...@intel.com The two patches is adding the Posted Interrupt supporting to KVM: The first patch enabls the feature 'acknowledge interrupt on vmexit'.Since it is required by Posted interrupt, we need to enable it firstly. And the second patch is adding the posted

[PATCH v2 1/2] KVM: VMX: enable acknowledge interupt on vmexit

From: Yang Zhang yang.z.zh...@intel.com The acknowledge interrupt on exit feature controls processor behavior for external interrupt acknowledgement. When this control is set, the processor acknowledges the interrupt controller to acquire the interrupt vector on VM exit. After enabling

[PATCH v2 2/2] KVM: VMX: Add Posted Interrupt supporting

From: Yang Zhang yang.z.zh...@intel.com Posted Interrupt allows APIC interrupts to inject into guest directly without any vmexit. - When delivering a interrupt to guest, if target vcpu is running, update Posted-interrupt requests bitmap and send a notification event to the vcpu

[PATCH] KVM : VMX: disable apicv by default

From: Yang Zhang yang.z.zh...@intel.com Without Posted Interrupt, current code is broken. Just disable by default until Posted Interrupt is ready. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/kvm/vmx.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git

[PATCH v2] KVM: VMX: disable apicv by default

From: Yang Zhang yang.z.zh...@intel.com Without Posted Interrupt, current code is broken. Just disable by default until Posted Interrupt is ready. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/kvm/vmx.c |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git

[PATCH v3 1/2] KVM: VMX: enable acknowledge interupt on vmexit

From: Yang Zhang yang.z.zh...@intel.com The acknowledge interrupt on exit feature controls processor behavior for external interrupt acknowledgement. When this control is set, the processor acknowledges the interrupt controller to acquire the interrupt vector on VM exit. After enabling

[PATCH v3 2/2] KVM: VMX: Add Posted Interrupt supporting

From: Yang Zhang yang.z.zh...@intel.com Posted Interrupt allows APIC interrupts to inject into guest directly without any vmexit. - When delivering a interrupt to guest, if target vcpu is running, update Posted-interrupt requests bitmap and send a notification event to the vcpu

[PATCH v3 0/2] KVM: VMX: Add Posted Interrupt supporting

From: Yang Zhang yang.z.zh...@intel.com The two patches are adding the Posted Interrupt supporting to KVM: The first patch enables the feature 'acknowledge interrupt on vmexit'.Since it is required by Posted interrupt, we need to enable it firstly. And the second patch is adding the posted

[PATCH v4 0/2] KVM: VMX: Add Posted Interrupt supporting

From: Yang Zhang yang.z.zh...@intel.com The two patches are adding the Posted Interrupt supporting to KVM: The first patch enables the feature 'acknowledge interrupt on vmexit'.Since it is required by Posted interrupt, we need to enable it firstly. And the second patch is adding the posted

[PATCH v4 1/2] KVM: VMX: enable acknowledge interupt on vmexit

From: Yang Zhang yang.z.zh...@intel.com The acknowledge interrupt on exit feature controls processor behavior for external interrupt acknowledgement. When this control is set, the processor acknowledges the interrupt controller to acquire the interrupt vector on VM exit. After enabling

[PATCH v4 2/2] KVM: VMX: Add Posted Interrupt supporting

From: Yang Zhang yang.z.zh...@intel.com Posted Interrupt allows APIC interrupts to inject into guest directly without any vmexit. - When delivering a interrupt to guest, if target vcpu is running, update Posted-interrupt requests bitmap and send a notification event to the vcpu

[PATCH] KVM: VMX: fix interrupt lost when enable virtual interrupt delivery

From: Yang Zhang yang.z.zh...@intel.com In the platform which supporing virtual interrupt delivery feature, hardware will clear vIRR atomatically when target vcpu is running. So software should not modify vIRR when target vcpu is running. This patch will record the virtual interrupt

[PATCH v5 0/5] KVM: VMX: Add Posted Interrupt supporting

From: Yang Zhang yang.z.zh...@intel.com Hi Ingo and Peter, The second patch (2/5 KVM: VMX: Register a new IPI for posted interrupt) tries to register an new IPI for posted interrupt which is used by KVM. Please help to review it. The follwoing patches are adding the Posted Interrupt supporting

[PATCH v5 1/5] KVM: VMX: Enable acknowledge interupt on vmexit

From: Yang Zhang yang.z.zh...@intel.com The acknowledge interrupt on exit feature controls processor behavior for external interrupt acknowledgement. When this control is set, the processor acknowledges the interrupt controller to acquire the interrupt vector on VM exit. After enabling

[PATCH v5 2/5] KVM: VMX: Register a new IPI for posted interrupt

From: Yang Zhang yang.z.zh...@intel.com Posted Interrupt feature requires a special IPI to deliver posted interrupt to guest. And it should has a high priority so the interrupt will not be blocked by others. Normally, the posted interrupt will be consumed by vcpu if target vcpu is running

[PATCH v5 5/5] KVM : VMX: Use posted interrupt to deliver virtual interrupt

From: Yang Zhang yang.z.zh...@intel.com If posted interrupt is avaliable, then uses it to inject virtual interrupt to guest. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/kvm/irq.c |2 +- arch/x86/kvm/lapic.c | 16 +--- arch/x86/kvm/lapic.h |1 + arch/x86

[PATCH v5 4/5] KVM: VMX: Add the algorithm of deliver posted interrupt

From: Yang Zhang yang.z.zh...@intel.com Only deliver the posted interrupt when target vcpu is running and there is no previous interrupt pending in pir. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/kvm_host.h |3 ++ arch/x86/kvm/lapic.c| 13

[PATCH v5 3/5] KVM: VMX: Check the posted interrupt capability

From: Yang Zhang yang.z.zh...@intel.com Detect the posted interrupt feature. If it exists, then set it in vmcs_config. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |4 ++ arch/x86/kvm/vmx.c | 87 ++-- 2

[PATCH 0/5] use eoi to track RTC interrupt delivery status

From: Yang Zhang yang.z.zh...@intel.com Current interrupt coalescing logci which only used by RTC has conflict with Posted Interrupt. This patch introduces a new mechinism to use eoi to track interrupt: When delivering an interrupt to vcpu, the need_eoi set to number of vcpu that received

[PATCH 5/5] KVM: use eoi to track RTC interrupt delivery status

From: Yang Zhang yang.z.zh...@intel.com Current interrupt coalescing logci which only used by RTC has conflict with Posted Interrupt. This patch introduces a new mechinism to use eoi to track interrupt: When delivering an interrupt to vcpu, the need_eoi set to number of vcpu that received

[PATCH 3/5] KVM: introduce struct rtc_status

From: Yang Zhang yang.z.zh...@intel.com New rtc_status structure to record rtc irq info. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- virt/kvm/ioapic.h |9 + 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/virt/kvm/ioapic.h b/virt/kvm/ioapic.h index 2fc61a5

[PATCH 1/5] KVM: parse ioapic entry to get destination vcpu

From: Yang Zhang yang.z.zh...@intel.com Introduce new function kvm_get_dest_vcpu() to parse ioapic entry to get destionation vcpu bitmap. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/kvm/lapic.c | 40 arch/x86/kvm/lapic.h |3 +++ 2

[PATCH 2/5] KVM: add vcpu info to ioapic_update_eoi()

From: Yang Zhang yang.z.zh...@intel.com Add vcpu info for ioapic when handling eoi. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/kvm/lapic.c |2 +- virt/kvm/ioapic.c| 12 ++-- virt/kvm/ioapic.h|3 ++- 3 files changed, 9 insertions(+), 8 deletions

[PATCH 4/5] KVM: register rtc eoi notifier

From: Yang Zhang yang.z.zh...@intel.com when virtual interrupt delivery avaliable, register a rtc eoi notifier to force vmexit when writing eoi for rtc interupt Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- virt/kvm/ioapic.c | 26 ++ 1 files changed, 26

[PATCH v6 0/5] KVM: VMX: Add Posted Interrupt supporting

From: Yang Zhang yang.z.zh...@intel.com The follwoing patches are adding the Posted Interrupt supporting to KVM: The first patch enables the feature 'acknowledge interrupt on vmexit'.Since it is required by Posted interrupt, we need to enable it firstly. And the subsequent patches are adding

[PATCH v6 1/5] KVM: VMX: Enable acknowledge interupt on vmexit

From: Yang Zhang yang.z.zh...@intel.com The acknowledge interrupt on exit feature controls processor behavior for external interrupt acknowledgement. When this control is set, the processor acknowledges the interrupt controller to acquire the interrupt vector on VM exit. After enabling

[PATCH v6 2/5] KVM: VMX: Register a new IPI for posted interrupt

From: Yang Zhang yang.z.zh...@intel.com Posted Interrupt feature requires a special IPI to deliver posted interrupt to guest. And it should has a high priority so the interrupt will not be blocked by others. Normally, the posted interrupt will be consumed by vcpu if target vcpu is running

[PATCH v6 3/5] KVM: VMX: Check the posted interrupt capability

From: Yang Zhang yang.z.zh...@intel.com Detect the posted interrupt feature. If it exists, then set it in vmcs_config. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/vmx.h |4 ++ arch/x86/kvm/vmx.c | 87 ++-- 2

[PATCH v6 5/5] KVM : VMX: Use posted interrupt to deliver virtual interrupt

From: Yang Zhang yang.z.zh...@intel.com If posted interrupt is avaliable, then uses it to inject virtual interrupt to guest. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/kvm/irq.c |3 ++- arch/x86/kvm/lapic.c | 16 +--- arch/x86/kvm/lapic.h |1 + arch

[PATCH v6 4/5] KVM: VMX: Add the algorithm of deliver posted interrupt

From: Yang Zhang yang.z.zh...@intel.com Only deliver the posted interrupt when target vcpu is running and there is no previous interrupt pending in pir. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/include/asm/kvm_host.h |4 ++ arch/x86/kvm/lapic.c| 13

[PATCH v2 1/8] KVM: Parse ioapic entry to get destination vcpu

From: Yang Zhang yang.z.zh...@intel.com Get destination vcpu map from one ioapic entry. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/kvm/lapic.c | 40 arch/x86/kvm/lapic.h |3 +++ 2 files changed, 27 insertions(+), 16 deletions

[PATCH v2 0/8] Use eoi to track RTC interrupt delivery status

From: Yang Zhang yang.z.zh...@intel.com Current interrupt coalescing logci which only used by RTC has conflict with Posted Interrupt. This patch introduces a new mechinism to use eoi to track interrupt: When delivering an interrupt to vcpu, the need_eoi set to number of vcpu that received

[PATCH v2 4/8] KVM: Introduce struct rtc_status

From: Yang Zhang yang.z.zh...@intel.com Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- virt/kvm/ioapic.h |9 + 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/virt/kvm/ioapic.h b/virt/kvm/ioapic.h index 2001b61..4904ca3 100644 --- a/virt/kvm/ioapic.h +++ b/virt

[PATCH v2 7/8] KVM: Add rtc irq to eoi exit bitmap

From: Yang Zhang yang.z.zh...@intel.com Add rtc irq to eoi exit bitmap to force vmexit when virtual interrupt delivery is enabled. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- virt/kvm/ioapic.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/virt/kvm/ioapic.c b

[PATCH v2 5/8] KVM: Recalculate destination vcpu map

From: Yang Zhang yang.z.zh...@intel.com Update destination vcpu map when ioapic entry or apic(id, ldr, dfr) is changed Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- virt/kvm/ioapic.c | 38 -- 1 files changed, 36 insertions(+), 2 deletions(-) diff

[PATCH v2 3/8] KVM: Add vcpu info to ioapic_update_eoi()

From: Yang Zhang yang.z.zh...@intel.com Need to know which vcpu writes EOI. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/kvm/lapic.c |2 +- virt/kvm/ioapic.c| 12 ++-- virt/kvm/ioapic.h|3 ++- 3 files changed, 9 insertions(+), 8 deletions(-) diff

[PATCH v2 8/8] KVM: Use eoi to track RTC interrupt delivery status

From: Yang Zhang yang.z.zh...@intel.com Current interrupt coalescing logci which only used by RTC has conflict with Posted Interrupt. This patch introduces a new mechinism to use eoi to track interrupt: When delivering an interrupt to vcpu, the need_eoi set to number of vcpu that received

[PATCH v2 6/8] KVM: Add reset/restore rtc_status support

From: Yang Zhang yang.z.zh...@intel.com reset/restore rtc_status when ioapic reset/restore. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/kvm/lapic.c |8 arch/x86/kvm/lapic.h |1 + virt/kvm/ioapic.c| 33 + 3 files changed

[PATCH v2 2/8] KVM: Rename kvm_ioapic_make_eoibitmap_request to kvm_scan_ioapic_entry

From: Yang Zhang yang.z.zh...@intel.com RTC interrupt coalesced need to parse ioapic entry to get destionation vcpu too. Rename it to more common name. Signed-off-by: Yang Zhang yang.z.zh...@intel.com --- arch/x86/kvm/lapic.c |2 +- virt/kvm/ioapic.c|6 +++--- virt/kvm/ioapic.h

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