On 05/19/2011 08:04 AM, Kumar Gala wrote:
On May 17, 2011, at 6:35 PM, Scott Wood wrote:
From: yu liuyu@freescale.com
giveup_spe() saves the SPE state which is protected by MSR[SPE].
However, modifying SPEFSCR does not trap when MSR[SPE]=0.
And since SPEFSCR is already saved/restored in
On 05/18/2011 01:40 AM, Scott Wood wrote:
BKeep the guest MSR and the guest-mode true MSR separate, rather than
Bkeep?
modifying the guest MSR on each guest entry to produce a true MSR.
Any bits which should be modified based on guest MSR must be explicitly
propagated from
On 05/18/2011 01:42 AM, Scott Wood wrote:
This is a shared page used for paravirtualization. It is always present
in the guest kernel's effective address space at the address indicated
by the hypercall that enables it.
The physical address specified by the hypercall is not used, as
e500 does
On 05/18/2011 01:42 AM, Scott Wood wrote:
From: Liu Yuyu@freescale.com
This patch utilize PID1 to map guest ID to shadow ID,
so that we can combine all needs to invalidate host TLB together,
and therefor reduce the frequency of calling _tlbia().
Signed-off-by: Liu Yuyu@freescale.com
On 05/18/2011 01:42 AM, Scott Wood wrote:
This implements a shared-memory API for giving Qemu access to the guest's
TLB.
Signed-off-by: Scott Woodscottw...@freescale.com
---
Documentation/kvm/api.txt | 79 +++-
arch/powerpc/include/asm/kvm.h | 35 +++
On 19.05.2011, at 18:28, Scott Wood wrote:
On Thu, 19 May 2011 16:10:48 +0200
Alexander Graf ag...@suse.de wrote:
On 05/18/2011 01:42 AM, Scott Wood wrote:
+For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV:
Can we rename those KVM_MMU_BOOKE_206_NOHV and KVM_MMU_BOOKE_206_HV
On 19.05.2011, at 18:37, Scott Wood wrote:
On Thu, 19 May 2011 12:43:21 +0200
Alexander Graf ag...@suse.de wrote:
On 05/18/2011 01:42 AM, Scott Wood wrote:
+void kvmppc_map_magic(struct kvm_vcpu *vcpu)
+{
+ struct tlbe magic;
+ ulong shared_page = ((ulong)vcpu-arch.shared
On 27.05.2011, at 12:33, Paul Mackerras wrote:
On Tue, May 17, 2011 at 12:17:50PM +0200, Alexander Graf wrote:
On 16.05.2011, at 07:58, Paul Mackerras wrote:
I do the check there because I was having problems where, if the HDEC
goes negative before we do the partition switch, we would
On 27.05.2011, at 22:59, Segher Boessenkool wrote:
I do the check there because I was having problems where, if the HDEC
goes negative before we do the partition switch, we would occasionally
not get the HDEC interrupt at all until the next time HDEC went
negative, ~ 8.4 seconds later.
On 31.05.2011, at 08:40, Paul Mackerras wrote:
The following series of patches enable KVM to exploit the hardware
hypervisor mode on 64-bit Power ISA Book3S machines. At present only
POWER7 is supported, but it would be easy to add other processors.
Running the KVM host in hypervisor mode
On 31.05.2011, at 14:35, Paul Mackerras wrote:
On Tue, May 31, 2011 at 12:40:31PM +0200, Alexander Graf wrote:
Thinking about the testability of this a bit more ... how much
effort would it be to get this code running on a 970MP with SLOF?
There should only be a few POWER7 specific pieces
On 03.06.2011, at 01:15, Scott Wood wrote:
This patchset contains SPE state management for e500 KVM guests, as well
as MMU enhancements (performance, userspace visibility, and support for
mapping things that aren't standard kernel-managed pages).
They are combined into one patchset because
On 06.06.2011, at 20:38, Scott Wood wrote:
On Sat, 4 Jun 2011 01:59:34 +0200
Alexander Graf ag...@suse.de wrote:
On 03.06.2011, at 01:15, Scott Wood wrote:
This patchset contains SPE state management for e500 KVM guests, as well
as MMU enhancements (performance, userspace visibility
-bit kvm user space to set signal masks.
This patch fixes qemu with --enable-io-thread on ppc64 hosts when running
32-bit user land.
Signed-off-by: Alexander Graf ag...@suse.de
---
kernel/compat.c |1 +
virt/kvm/kvm_main.c | 50 +-
2 files
-bit kvm user space to set signal masks.
This patch fixes qemu with --enable-io-thread on ppc64 hosts when running
32-bit user land.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- use compat_ptr
- only declare compat call with CONFIG_COMPAT
---
kernel/compat.c |1 +
virt
On 03.06.2011, at 01:17, Scott Wood wrote:
This is a shared page used for paravirtualization. It is always present
in the guest kernel's effective address space at the address indicated
by the hypercall that enables it.
The physical address specified by the hypercall is not used, as
e500
On 03.06.2011, at 01:17, Scott Wood wrote:
From: Liu Yu yu@freescale.com
Instead of a fully separate set of TLB entries, keep just the
pfn and dirty status.
Signed-off-by: Liu Yu yu@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
---
On 03.06.2011, at 01:17, Scott Wood wrote:
From: Liu Yu yu@freescale.com
Dynamically assign host PIDs to guest PIDs, splitting each guest PID into
multiple host (shadow) PIDs based on kernel/user and MSR[IS/DS]. Use
both PID0 and PID1 so that the shadow PIDs for the right mode can be
On 14.06.2011, at 21:28, Scott Wood wrote:
On Tue, 14 Jun 2011 12:40:22 +0200
Alexander Graf ag...@suse.de wrote:
On 03.06.2011, at 01:17, Scott Wood wrote:
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
index c09e642..9d1e28d 100644
--- a/arch/powerpc/kvm
On 14.06.2011, at 21:37, Scott Wood wrote:
On Tue, 14 Jun 2011 12:41:03 +0200
Alexander Graf ag...@suse.de wrote:
On 03.06.2011, at 01:17, Scott Wood wrote:
+static void kvmppc_e500_stlbe_invalidate(struct kvmppc_vcpu_e500
*vcpu_e500,
+int tlbsel
On 15.06.2011, at 01:34, Scott Wood wrote:
This is a shared page used for paravirtualization. It is always present
in the guest kernel's effective address space at the address indicated
by the hypercall that enables it.
The physical address specified by the hypercall is not used, as
e500
On 15.06.2011, at 22:58, Scott Wood wrote:
On Wed, 15 Jun 2011 13:34:06 +0200
Alexander Graf ag...@suse.de wrote:
On 15.06.2011, at 12:50, Alexander Graf wrote:
What are your results when using the magic page? I have the following
numbers with your patches applied:
== bare metal
On 17.06.2011, at 00:29, Scott Wood wrote:
This implements a shared-memory API for giving host userspace access to
the guest's TLB.
Would you mind if we wait with applying this upstream until there's a user
available we can verify the interface against?
Alex
--
To unsubscribe from this
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/timing.c |9 -
1 files changed, 0 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kvm/timing.c b/arch/powerpc/kvm/timing.c
index 319177d..07b6110 100644
--- a/arch
/agraf/linux-2.6.git kvm-ppc-next
Alexander Graf (2):
KVM: PPC: Resolve real-mode handlers through function exports
KVM: Add compat ioctl for KVM_SET_SIGNAL_MASK
Liu Yu (2):
KVM: PPC: e500: Stop keeping shadow TLB
KVM: PPC: e500: Add shadow PID support
Scott Wood (9
-bit kvm user space to set signal masks.
This patch fixes qemu with --enable-io-thread on ppc64 hosts when running
32-bit user land.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- use compat_ptr
- only declare compat call with CONFIG_COMPAT
---
kernel/compat.c |1 +
virt
-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kernel/head_fsl_booke.S |2 --
arch/powerpc/kernel/process.c|1 +
arch/powerpc/kernel/traps.c |5 +
3 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_fsl_booke.S
b/arch/powerpc
From: Liu Yu yu@freescale.com
Instead of a fully separate set of TLB entries, keep just the
pfn and dirty status.
Signed-off-by: Liu Yu yu@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/kvm_e500.h
.
Signed-off-by: Liu Yu yu@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/kvm_e500.h |8 +-
arch/powerpc/include/asm/kvm_host.h |1 +
arch/powerpc/kernel/asm-offsets.c |1 +
arch/powerpc/kvm
-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/e500_tlb.c | 103 +++
1 files changed, 94 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
index 0291c3c
-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/ppc_asm.h | 28
arch/powerpc/kernel/head_fsl_booke.S |6 +++---
2 files changed, 19 insertions(+), 15
not have real mode.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
Documentation/virtual/kvm/ppc-pv.txt |8 +---
arch/powerpc/include/asm/kvm_ppc.h |1 +
arch/powerpc/kvm/booke.c | 11 +++
arch/powerpc/kvm
On 18.06.2011, at 10:27, Paul Mackerras wrote:
The following series of patches enable KVM to exploit the hardware
hypervisor mode on 64-bit Power ISA Book3S machines. At present,
POWER7 and PPC970 processors are supported. (Note that the PPC970
processors in Apple G5 machines don't have a
On 19.06.2011, at 11:04, Avi Kivity wrote:
On 06/17/2011 05:49 PM, Alexander Graf wrote:
KVM has an ioctl to define which signal mask should be used while running
inside VCPU_RUN. At least for big endian systems, this mask is different
on 32-bit and 64-bit systems (though the size
On 18.06.2011, at 10:35, Paul Mackerras wrote:
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged
On 18.06.2011, at 10:27, Paul Mackerras wrote:
The following series of patches enable KVM to exploit the hardware
hypervisor mode on 64-bit Power ISA Book3S machines. At present,
POWER7 and PPC970 processors are supported. (Note that the PPC970
processors in Apple G5 machines don't have a
On 29.06.2011, at 13:53, Josh Boyer wrote:
On Wed, Jun 29, 2011 at 08:41:03PM +1000, Paul Mackerras wrote:
Documentation/virtual/kvm/api.txt | 35
+++
arch/powerpc/include/asm/kvm.h | 15 +++
arch/powerpc/include/asm/kvm_host.h |1 +
On 06/29/2011 12:41 PM, Paul Mackerras wrote:
This new ioctl allows userspace to specify what paravirtualization
interface (if any) KVM should implement, what architecture version
the guest virtual processors should conform to, and whether the guest
can be permitted to use a real supervisor
On 29.06.2011, at 12:18, Paul Mackerras wrote:
Doing so means that we don't have to save the flags anywhere and gets
rid of the last reference to to_book3s(vcpu) in arch/powerpc/kvm/book3s.c.
Doing so is OK because a program interrupt won't be generated at the
same time as any other
On 29.06.2011, at 12:15, Paul Mackerras wrote:
The first patch of the following series is a pure bug-fix for 32-bit
kernels.
The remainder of the following series of patches enable KVM to exploit
the hardware hypervisor mode on 64-bit Power ISA Book3S machines. At
present, POWER7 and
On 03.07.2011, at 10:15, Avi Kivity wrote:
On 06/30/2011 07:33 PM, Alexander Graf wrote:
On 30.06.2011, at 18:00, Avi Kivitya...@redhat.com wrote:
On 06/30/2011 06:22 PM, Alexander Graf wrote:
Regarding that. There's another option - the ioctl code embeds the
structure size. So
On 03.07.2011, at 10:56, Avi Kivity wrote:
On 07/03/2011 11:34 AM, Alexander Graf wrote:
Yup, which requires knowledge in the code on what actually fits :).
Logic we don't have today.
I don't follow. What knowledge is required? Please give an example.
Sure. Let's take an easy
On 03.07.2011, at 11:12, Avi Kivity wrote:
On 07/03/2011 12:09 PM, Alexander Graf wrote:
Right. The idea is that if KVM_FLAG_BLAH implies a field
kvm_struct::blah, then either both are present in the headers, or none of
them.
Yup, makes sense. I like the idea :). Gets rid of all
On 04.07.2011, at 13:22, Avi Kivity wrote:
On 07/04/2011 01:59 PM, Alexander Graf wrote:
On 03.07.2011, at 11:12, Avi Kivity wrote:
On 07/03/2011 12:09 PM, Alexander Graf wrote:
Right. The idea is that if KVM_FLAG_BLAH implies a field
kvm_struct::blah, then either both
On 04.07.2011, at 13:37, Avi Kivity wrote:
On 07/04/2011 02:36 PM, Alexander Graf wrote:
What intermediate steps? We can't add fields to the structure before we
get the extensibility infrastructure, but that's all.
If we add it now without extensibility code, we will have a kernel
-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/exception-64s.h | 121 --
arch/powerpc/kernel/exceptions-64s.S | 189 +---
arch/powerpc/kvm/book3s_rmhandlers.S | 78 ++--
arch
runnable, so we will always use the lower-numbered
hardware threads in preference to higher-numbered threads if not all
the vcpus in the vcore are runnable, regardless of which vcpus are
runnable.
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
where we could block
or get preempted.
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/exception-64s.h | 10 ++--
arch/powerpc/include/asm/kvm_book3s_asm.h | 27 ++---
arch/powerpc/include/asm/paca.h |1
do SMT4 guest
support in the book3s hypervisor mode code.
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/kvm_ppc.h |1 +
arch/powerpc/kvm/book3s_interrupts.S |2 +-
arch/powerpc/kvm/book3s_pr.c | 12
a virtual real
memory area (VRMA) composed of 16MB large pages, and hypervisor
decrementer interrupts are disabled.
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/reg.h |4
arch/powerpc/kernel
() to convert these addresses
to physical addresses.
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/book3s.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm
interrupts.
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/exception-64s.h |4 +
arch/powerpc/include/asm/kvm_book3s_asm.h |2 +-
arch/powerpc/include/asm/kvm_host.h |2 +-
arch/powerpc/kernel/asm-offsets.c
into the
kvm-arch struct and arranges for the MER (mediated external request)
bit, which is the only bit that varies between vcpus, to be set in
assembly code when going into the guest if there is a pending external
interrupt request.
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander
this.
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/kvm_ppc.h |7 +++
arch/powerpc/kvm/book3s_pr.c | 20
arch/powerpc/kvm/booke.c | 20
arch/powerpc/kvm
Commit c8f729d408 (KVM: PPC: Deliver program interrupts right away instead
of queueing them) made away with all users of prog_flags, so we can just
remove it from the headers.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/kvm_book3s.h |1 -
1 files changed, 0
...@gibson.dropbear.id.au
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
Documentation/virtual/kvm/api.txt| 35 +
arch/powerpc/include/asm/kvm.h |9 +++
arch/powerpc/include/asm/kvm_book3s_64.h |2 +
arch/powerpc/include/asm
__tlbie() can only get called
if we are running bare-metal, i.e. in hypervisor mode.
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/cputable.h| 14 --
arch/powerpc/include/asm/reg.h | 16
-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/book3s.c |8 +++-
1 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index 163e3e1..f68a34d 100644
--- a/arch/powerpc/kvm
On 08.07.2011, at 23:36, Aashish Mittal wrote:
Scott Wood scottwood at freescale.com writes:
On Fri, 8 Jul 2011 20:33:18 +
Aashish Mittal aashish.mittal4u at gmail.com wrote:
Were they saved in the first place? What trap type did you enter on --
is it listed in
On 08.07.2011, at 01:41, Scott Wood wrote:
It should contain the way, not the absolute TLB0 index.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/kvm/e500_tlb.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/e500_tlb.c
On 08.07.2011, at 01:41, Scott Wood wrote:
Split out the portions of tlbe_priv that should be associated with host
entries into tlbe_ref. Base victim selection on the number of hardware
entries, not guest entries.
For TLB1, where one guest entry can be mapped by multiple host entries,
we
On 18.07.2011, at 20:06, Scott Wood wrote:
On Mon, 18 Jul 2011 18:30:51 +0200
Alexander Graf ag...@suse.de wrote:
On 18.07.2011, at 18:12, Scott Wood wrote:
On Mon, 18 Jul 2011 11:16:10 +0200
Alexander Graf ag...@suse.de wrote:
On 08.07.2011, at 01:41, Scott Wood wrote
On 18.07.2011, at 20:45, Scott Wood wrote:
On Mon, 18 Jul 2011 11:49:10 +0200
Alexander Graf ag...@suse.de wrote:
On 08.07.2011, at 01:41, Scott Wood wrote:
@@ -63,7 +64,9 @@ static DEFINE_PER_CPU(struct pcpu_id_table, pcpu_sids);
* The valid range of shadow ID is [1..255] */
static
On 18.07.2011, at 23:43, Scott Wood wrote:
On Mon, 18 Jul 2011 23:37:50 +0200
Alexander Graf ag...@suse.de wrote:
I guess I'm merely not understanding why we have the non-way bits set in
TLB0 entries, but not in TLB1 ones :). Do we pass in the real array index?
KVM internally uses
On 19.07.2011, at 13:20, Johannes Weiner wrote:
On Tue, Jul 19, 2011 at 10:51:40AM +0200, Alexander Graf wrote:
On 19.07.2011, at 10:36, Johannes Weiner wrote:
On Mon, Jul 18, 2011 at 11:44:02PM +0200, Alexander Graf wrote:
On 18.07.2011, at 20:08, Scott Wood wrote:
On Mon, 18 Jul
On 25.07.2011, at 21:25, Scott Wood wrote:
On Sun, 24 Jul 2011 11:16:32 +0200
Alexander Graf ag...@suse.de wrote:
On 19.07.2011, at 13:20, Johannes Weiner wrote:
You don't have to work around the mm subsystem trying to reclaim your
memory,
The pages are pinned by get_free_pages_fast
On 07/23/2011 09:42 AM, Paul Mackerras wrote:
With a KVM guest operating in SMT4 mode (i.e. 4 hardware threads per
core), whenever a CPU goes idle, we have to pull all the other
hardware threads in the core out of the guest, because the H_CEDE
hcall is handled in the kernel. This is
the system call.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/book3s_segment.S |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_segment.S
b/arch/powerpc/kvm/book3s_segment.S
index aed32e5..678b6be 100644
--- a/arch/powerpc/kvm
When running a PAPR guest, some things change. The privilege level drops
from hypervisor to supervisor, SDR1 gets treated differently and we interpret
hypercalls. For bisectability sake, add the flag now, but only enable it when
all the support code is there.
Signed-off-by: Alexander Graf ag
Recent Linux versions use the CFAR and PURR SPRs, but don't really care about
their contents (yet). So for now, we can simply return 0 when the guest wants
to read them.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/book3s_emulate.c |4
1 files changed, 4 insertions
this way
around, as the two differ too much in those details.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/kvm_book3s.h |1 +
arch/powerpc/kvm/Makefile |1 +
arch/powerpc/kvm/book3s_pr_papr.c | 158 +
3 files changed
We have 3 privilege levels: problem state, supervisor state and hypervisor
state. Each of them can access different SPRs, so we need to check on every
SPR if it's accessible in the respective mode.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/book3s_emulate.c | 25
the SREGS based method, we drop the PVR logic.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/kvm.h|8
arch/powerpc/include/asm/kvm_book3s.h |2 ++
arch/powerpc/kvm/book3s_pr.c | 14 --
arch/powerpc/kvm/powerpc.c
interface that we already use for HV style
KVM.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/book3s_pr.c | 22 +-
1 files changed, 21 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 78dcf65..48558f6
We need the compute_tlbie_rb in _pr and _hv implementations for papr
soon, so let's move it over to a common header file that both
implementations can leverage.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/kvm_book3s.h | 33 +
arch
On 08/09/2011 06:42 PM, Avi Kivity wrote:
On 08/09/2011 07:31 PM, Alexander Graf wrote:
In KVM for Book3S PPC we currently have 2 implementations. There
is the PR based implementation which works on any POWER system
you pass in and the super fast HV implementation which requires
libre firmware
Am 10.08.2011 um 06:42 schrieb Paul Mackerras pau...@samba.org:
On Tue, Aug 09, 2011 at 06:31:48PM +0200, Alexander Graf wrote:
Now that Book3S PV mode can also run PAPR guests, we can add a PAPR cap and
enable it for all Book3S targets. Enabling that CAP switches KVM into PAPR
mode
checks if PVR is set (should always be true given the current code
flow), if PAPR is only used with book3s_64 where it works and that
HV KVM is only used in PAPR mode.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/kvm.h |5 +
arch/powerpc/include/asm
On 08/03/2011 08:55 PM, Nishanth Aravamudan wrote:
On a box with gcc 4.3.2, I see errors like:
arch/powerpc/kvm/book3s_hv_rmhandlers.S:1254: Error: Unrecognized opcode:
stxvd2x
arch/powerpc/kvm/book3s_hv_rmhandlers.S:1316: Error: Unrecognized opcode: lxvd2x
Paul, mind to ack?
Alex
On 10.08.2011, at 20:56, Benjamin Herrenschmidt wrote:
On Wed, 2011-08-10 at 16:58 +0200, Alexander Graf wrote:
On 08/03/2011 08:55 PM, Nishanth Aravamudan wrote:
On a box with gcc 4.3.2, I see errors like:
arch/powerpc/kvm/book3s_hv_rmhandlers.S:1254: Error: Unrecognized opcode:
stxvd2x
Am 12.08.2011 um 05:33 schrieb David Gibson da...@gibson.dropbear.id.au:
On Tue, Aug 09, 2011 at 06:31:47PM +0200, Alexander Graf wrote:
PAPR defines hypercalls as SC1 instructions. Using these, the guest modifies
page tables and does other privileged operations that it wouldn't be allowed
Am 12.08.2011 um 05:35 schrieb David Gibson da...@gibson.dropbear.id.au:
On Tue, Aug 09, 2011 at 06:31:45PM +0200, Alexander Graf wrote:
When running a PAPR guest, we need to handle a few hypercalls in kernel
space,
most prominently the page table invalidation (to sync the shadows).
So
Am 12.08.2011 um 09:43 schrieb David Gibson da...@gibson.dropbear.id.au:
On Fri, Aug 12, 2011 at 07:35:42AM +0200, Alexander Graf wrote:
Am 12.08.2011 um 05:33 schrieb David Gibson da...@gibson.dropbear.id.au:
On Tue, Aug 09, 2011 at 06:31:47PM +0200, Alexander Graf wrote:
PAPR defines
Am 12.08.2011 um 09:43 schrieb David Gibson da...@gibson.dropbear.id.au:
On Fri, Aug 12, 2011 at 07:38:54AM +0200, Alexander Graf wrote:
Am 12.08.2011 um 05:35 schrieb David Gibson da...@gibson.dropbear.id.au:
On Tue, Aug 09, 2011 at 06:31:45PM +0200, Alexander Graf wrote:
When running
On 19.08.2011, at 06:45, Aashish Mittal wrote:
Hi
I'm trying to emulate the lwzu instruction in e500 powerpc kvm for my project
.
I've removed the read and write privileges from the tlb entries of guest's
certain pages . So when i'm trying to emulate lwzu instruction i'm getting a
When running a PAPR guest, some things change. The privilege level drops
from hypervisor to supervisor, SDR1 gets treated differently and we interpret
hypercalls. For bisectability sake, add the flag now, but only enable it when
all the support code is there.
Signed-off-by: Alexander Graf ag
checks if PVR is set (should always be true given the current code
flow), if PAPR is only used with book3s_64 where it works and that
HV KVM is only used in PAPR mode.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/kvm.h |5 +
arch/powerpc/include/asm
via exceptions-64s.S.
Signed-off-by: Paul Mackerras pau...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kernel/exceptions-64s.S| 10 --
arch/powerpc/kvm/Makefile |3 +++
arch/powerpc/kvm/book3s_hv_rmhandlers.S |3 +++
arch/powerpc/kvm
kvm-ppc-next
Alexander Graf (11):
KVM: PPC: move compute_tlbie_rb to book3s common header
KVM: PPC: Add papr_enabled flag
KVM: PPC: Check privilege level on SPRs
KVM: PPC: Interpret SDR1 as HVA in PAPR mode
KVM: PPC: Read out syscall instruction on trap
KVM: PPC
We need the compute_tlbie_rb in _pr and _hv implementations for papr
soon, so let's move it over to a common header file that both
implementations can leverage.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/include/asm/kvm_book3s.h | 33 +
arch
the system call.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/book3s_segment.S |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_segment.S
b/arch/powerpc/kvm/book3s_segment.S
index aed32e5..678b6be 100644
--- a/arch/powerpc/kvm
On 25.08.2011, at 04:30, Aashish Mittal wrote:
On Thu, Aug 25, 2011 at 4:04 AM, Alexander Graf ag...@suse.de wrote:
On 19.08.2011, at 06:45, Aashish Mittal wrote:
Hi
I'm trying to emulate the lwzu instruction in e500 powerpc kvm for my
project .
I've removed the read and write
Hi Kun,
On 08/29/2011 11:31 AM, Kun Wang wrote:
Hi, everyone,
This is Kun Wang from IBM Research China. I and my team have been working
on IBM PowerEN processor in recent years, including its simulation,
lib/runtime optimization and etc. Now we start the work to enable KVM on
PowerEN
We have an ioctl that enables capabilities individually, but no description
on what exactly happens when we enable a capability using this ioctl.
This patch adds documentation for capability enabling in a new section
of the API documentation.
Signed-off-by: Alexander Graf ag...@suse.de
On 31.08.2011, at 15:07, Avi Kivity wrote:
On 08/31/2011 04:02 PM, Alexander Graf wrote:
On 31.08.2011, at 14:52, Sasha Levin wrote:
On Wed, 2011-08-31 at 10:58 +0200, Alexander Graf wrote:
+This capaobility enables interception of OSI hypercalls that otherwise
would
capability
On 08/18/2011 10:24 PM, Scott Wood wrote:
Scott Wood (5):
KVM: PPC: e500: don't translate gfn to pfn with preemption disabled
KVM: PPC: e500: Eliminate preempt_disable in local_sid_destroy_all
KVM: PPC: e500: clear up confusion between host and guest entries
KVM: PPC: e500: MMU API
Am 02.09.2011 um 01:08 schrieb Scott Wood scottw...@freescale.com:
Signed-off-by: Scott Wood scottw...@freescale.com
Patch description missing.
Also, since pir == vcpu_id now, can't we just remove pir?
Alex
---
arch/powerpc/kvm/booke.c |4 ++--
arch/powerpc/kvm/e500.c |3 ---
2
On 02.09.2011, at 20:14, Scott Wood wrote:
On 09/02/2011 10:12 AM, Alexander Graf wrote:
Am 02.09.2011 um 01:08 schrieb Scott Wood scottw...@freescale.com:
Signed-off-by: Scott Wood scottw...@freescale.com
Patch description missing.
It's not missing, it's just brief. :-)
I
On 02.09.2011, at 20:17, Scott Wood wrote:
On 09/02/2011 08:53 AM, Alexander Graf wrote:
On 08/27/2011 01:31 AM, Scott Wood wrote:
int_pending was only being lowered if a bit in pending_exceptions
was cleared during exception delivery -- but for interrupts, we clear
it during IACK/TSR
On 02.09.2011, at 21:35, Scott Wood wrote:
On 09/02/2011 02:23 PM, Alexander Graf wrote:
On 02.09.2011, at 20:14, Scott Wood wrote:
On 09/02/2011 10:12 AM, Alexander Graf wrote:
Am 02.09.2011 um 01:08 schrieb Scott Wood scottw...@freescale.com:
Signed-off-by: Scott Wood scottw
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