[PATCH 93/95] arm64: KVM: vgic-v3: Do not save an LR known to be empty

On exit, any empty LR will be signaled in ICH_ELRSR_EL2. Which means that we do not have to save it, and we can just clear its state in the in-memory copy. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier ---

[PATCH 95/95] arm64: KVM: vgic-v3: Only wipe LRs on vcpu exit

So far, we're always writing all possible LRs, setting the empty ones with a zero value. This is obvious doing a low of work for nothing, and we're better off clearing those we've actually dirtied on the exit path (it is very rare to inject more than one interrupt at a time anyway). Reviewed-by:

[PATCH 88/95] KVM: arm/arm64: vgic-v2: Reset LRs at boot time

In order to let make the GICv2 code more lazy in the way it accesses the LRs, it is necessary to start with a clean slate. Let's reset the LRs on each CPU when the vgic is probed. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier ---

[PATCH 92/95] arm64: KVM: vgic-v3: Save maintenance interrupt state only if required

Next on our list of useless accesses is the maintenance interrupt status registers (ICH_MISR_EL2, ICH_EISR_EL2). It is pointless to save them if we haven't asked for a maintenance interrupt the first place, which can only happen for two reasons: - Underflow: ICH_HCR_UIE will be set, - EOI:

[PATCH 94/95] arm64: KVM: vgic-v3: Reset LRs at boot time

In order to let the GICv3 code be more lazy in the way it accesses the LRs, it is necessary to start with a clean slate. Let's reset the LRs on each CPU when the vgic is probed (which includes a round trip to EL2...). Reviewed-by: Christoffer Dall Signed-off-by:

[PATCH 91/95] arm64: KVM: vgic-v3: Avoid accessing ICH registers

Just like on GICv2, we're a bit hammer-happy with GICv3, and access them more often than we should. Adopt a policy similar to what we do for GICv2, only save/restoring the minimal set of registers. As we don't access the registers linearly anymore (we may skip some), the convoluted accessors

[PATCH 90/95] KVM: arm/arm64: vgic-v2: Make GICD_SGIR quicker to hit

The GICD_SGIR register lives a long way from the beginning of the handler array, which is searched linearly. As this is hit pretty often, let's move it up. This saves us some precious cycles when the guest is generating IPIs. Acked-by: Christoffer Dall Signed-off-by:

[PATCH 89/95] KVM: arm/arm64: vgic-v2: Only wipe LRs on vcpu exit

So far, we're always writing all possible LRs, setting the empty ones with a zero value. This is obvious doing a lot of work for nothing, and we're better off clearing those we've actually dirtied on the exit path (it is very rare to inject more than one interrupt at a time anyway). Reviewed-by:

[PATCH 71/95] arm64: KVM: Add access handler for PMUSERENR register

From: Shannon Zhao This register resets as unknown in 64bit mode while it resets as zero in 32bit mode. Here we choose to reset it as zero for consistency. PMUSERENR_EL0 holds some bits which decide whether PMU registers can be accessed from EL0. Add some check helpers

[PATCH 70/95] arm64: KVM: Add helper to handle PMCR register bits

From: Shannon Zhao According to ARMv8 spec, when writing 1 to PMCR.E, all counters are enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are disabled. When writing 1 to PMCR.P, reset all event counters, not including PMCCNTR, to zero. When writing 1 to

[PATCH 77/95] arm64: KVM: Add a new vcpu device control group for PMUv3

From: Shannon Zhao To configure the virtual PMUv3 overflow interrupt number, we use the vcpu kvm_device ioctl, encapsulating the KVM_ARM_VCPU_PMU_V3_IRQ attribute within the KVM_ARM_VCPU_PMU_V3_CTRL group. After configuring the PMUv3, call the vcpu ioctl with attribute

[PATCH 78/95] arm64: KVM: Switch the sys_reg search to be a binary search

Our 64bit sys_reg table is about 90 entries long (so far, and the PMU support is likely to increase this). This means that on average, it takes 45 comparaisons to find the right entry (and actually the full 90 if we have to search the invariant table). Not the most efficient thing. Specially when

[PATCH 82/95] ARM: KVM: Switch the CP reg search to be a binary search

Doing a linear search is a bit silly when we can do a binary search. Not that we trap that so many things that it has become a burden yet, but it makes sense to align it with the arm64 code. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier

[PATCH 79/95] ARM: KVM: Properly sort the invariant table

Not having the invariant table properly sorted is an oddity, and may get in the way of future optimisations. Let's fix it. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/kvm/coproc.c | 6 +++--- 1 file changed, 3

[PATCH 72/95] arm64: KVM: Add PMU overflow interrupt routing

From: Shannon Zhao When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when the perf event overflows, set the corresponding bit of guest PMOVSSET register. If this counter is enabled and its interrupt is enabled as well,

[PATCH 69/95] arm64: KVM: Add access handler for PMSWINC register

From: Shannon Zhao Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao Reviewed-by: Andrew Jones Signed-off-by: Marc

[PATCH 85/95] KVM: arm/arm64: vgic-v2: Save maintenance interrupt state only if required

Next on our list of useless accesses is the maintenance interrupt status registers (GICH_MISR, GICH_EISR{0,1}). It is pointless to save them if we haven't asked for a maintenance interrupt the first place, which can only happen for two reasons: - Underflow: GICH_HCR_UIE will be set, - EOI:

[PATCH 67/95] arm64: KVM: Add access handler for PMINTENSET and PMINTENCLR register

From: Shannon Zhao Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a handler to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao Reviewed-by: Andrew Jones

[PATCH 61/95] arm64: KVM: Add access handler for PMSELR register

From: Shannon Zhao Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. When reading PMSELR, return the PMSELR.SEL field to guest. Signed-off-by: Shannon Zhao Reviewed-by: Andrew Jones

[PATCH 68/95] arm64: KVM: Add access handler for PMOVSSET and PMOVSCLR register

From: Shannon Zhao Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a handler to emulate writing PMOVSSET or PMOVSCLR register. When writing non-zero value to PMOVSSET, the counter and its interrupt is enabled, kick

[PATCH 59/95] arm64: KVM: Define PMU data structure for each vcpu

From: Shannon Zhao Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monitor unit for

[PATCH 73/95] arm64: KVM: Reset PMU state when resetting vcpu

From: Shannon Zhao When resetting vcpu, it needs to reset the PMU state to initial status. Signed-off-by: Shannon Zhao Reviewed-by: Marc Zyngier Reviewed-by: Andrew Jones Signed-off-by: Marc Zyngier

[PATCH 66/95] arm64: KVM: Add access handler for event type register

From: Shannon Zhao These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER which is mapped to PMEVTYPERn or PMCCFILTR. The access handler translates all aarch32 register offsets to aarch64 ones and uses vcpu_sys_reg() to access their values to avoid taking

[PATCH 62/95] arm64: KVM: Add access handler for PMCEID0 and PMCEID1 register

From: Shannon Zhao Add access handler which gets host value of PMCEID0 or PMCEID1 when guest access these registers. Writing action to PMCEID0 or PMCEID1 is UNDEFINED. Signed-off-by: Shannon Zhao Signed-off-by: Marc Zyngier

[PATCH 60/95] arm64: KVM: Add access handler for PMCR register

From: Shannon Zhao Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN except PMCR.E which is zero. Add an access handler for PMCR. Signed-off-by: Shannon Zhao Reviewed-by: Andrew Jones

[PATCH 63/95] arm64: KVM: Add access handler for event counter register

From: Shannon Zhao These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which is mapped to PMEVCNTRn. The access handler translates all aarch32 register offsets to aarch64 ones and uses vcpu_sys_reg() to access their values to avoid taking care of big

[PATCH 64/95] arm64: KVM: Add access handler for PMCNTENSET and PMCNTENCLR register

From: Shannon Zhao Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a handler to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf event.

[PATCH 65/95] arm64: KVM: PMU: Add perf event map and introduce perf event creating function

From: Shannon Zhao When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event number and write this number to PMU PMEVTYPER_EL0 register. When getting the event number in

[PATCH 45/95] arm64: KVM: VHE: Use unified sysreg accessors for timer

Switch the timer code to the unified sysreg accessors. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/timer-sr.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[PATCH 51/95] arm64: VHE: Add support for running Linux in EL2 mode

With ARMv8.1 VHE, the architecture is able to (almost) transparently run the kernel at EL2, despite being written for EL1. This patch takes care of the "almost" part, mostly preventing the kernel from dropping from EL2 to EL1, and setting up the HYP configuration. Reviewed-by: Christoffer Dall

[PATCH 41/95] arm64: KVM: VHE: Use unified system register accessors

Use the recently introduced unified system register accessors for those sysregs that behave differently depending on VHE being in use or not. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/sysreg-sr.c | 84

[PATCH 58/95] arm64: KVM: Add temporary kvm_perf_event.h

In order to merge the KVM/ARM PMU patches without creating a conflict mess, let's have a temporary include file that won't conflict with anything. Subsequent patches will clean that up. Acked-by: Will Deacon Signed-off-by: Marc Zyngier ---

[PATCH 57/95] arm64: KVM: Move __cpu_init_stage2 after kvm_call_hyp

In order to ease the merge with the rest of the arm64 tree, move the definition of __cpu_init_stage2() after what will be the new kvm_call_hyp. Hopefully the resolution of the merge conflict will be obvious. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_host.h

[PATCH 52/95] arm64: KVM: Move kvm/hyp/hyp.h to include/asm/kvm_hyp.h

In order to be able to move code outside of kvm/hyp, we need to make the global hyp.h file accessible from a standard location. include/asm/kvm_hyp.h seems good enough. Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier ---

[PATCH 55/95] ARM: KVM: Use common version of vgic-v2-sr.c

No need to keep our own private version, the common one is strictly identical. Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/kvm/hyp/Makefile | 5 ++- arch/arm/kvm/hyp/vgic-v2-sr.c | 82

[PATCH 46/95] arm64: KVM: VHE: Add fpsimd enabling on guest access

Despite the fact that a VHE enabled kernel runs at EL2, it uses CPACR_EL1 to trap FPSIMD access. Add the required alternative code to re-enable guest FPSIMD access when it has trapped to EL2. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier

[PATCH 50/95] arm64: hw_breakpoint: Allow EL2 breakpoints if running in HYP

With VHE, we place kernel {watch,break}-points at EL2 to get things like kgdb and "perf -e mem:..." working. This requires a bit of repainting in the low-level encore/decode, but is otherwise pretty simple. Acked-by: Will Deacon Signed-off-by: Marc Zyngier

[PATCH 53/95] arm64: KVM: Move vgic-v2 and timer save/restore to virt/kvm/arm/hyp

We already have virt/kvm/arm/ containing timer and vgic stuff. Add yet another subdirectory to contain the hyp-specific files (timer and vgic again). Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/Makefile |

[PATCH 56/95] ARM: KVM: Use common version of timer-sr.c

Using the common HYP timer code is a bit more tricky, since we use system register names. Nothing a set of macros cannot work around... Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/include/asm/kvm_hyp.h | 9 ++

[PATCH 42/95] arm64: KVM: VHE: Enable minimal sysreg save/restore

We're now in a position where we can introduce VHE's minimal save/restore, which is limited to the handful of shared sysregs. Add the required alternative function calls that result in a "do nothing" call on VHE, and the normal save/restore for non-VHE. Reviewed-by: Christoffer Dall

[PATCH 49/95] arm64: perf: Count EL2 events if the kernel is running in HYP

When the kernel is running in HYP (with VHE), it is necessary to include EL2 events if the user requests counting kernel or hypervisor events. Reviewed-by: Christoffer Dall Acked-by: Catalin Marinas Acked-by: Will Deacon

[PATCH 47/95] arm64: KVM: VHE: Add alternative panic handling

As the kernel fully runs in HYP when VHE is enabled, we can directly branch to the kernel's panic() implementation, and not perform an exception return. Add the alternative code to deal with this. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier

[PATCH 39/95] arm64: KVM: VHE: Differenciate host/guest sysreg save/restore

With ARMv8, host and guest share the same system register file, making the save/restore procedure completely symetrical. With VHE, host and guest now have different requirements, as they use different sysregs. In order to prepare for this, add split sysreg save/restore functions for both host and

[PATCH 44/95] arm64: KVM: VHE: Implement VHE activate/deactivate_traps

Running the kernel in HYP mode requires the HCR_E2H bit to be set at all times, and the HCR_TGE bit to be set when running as a host (and cleared when running as a guest). At the same time, the vector must be set to the current role of the kernel (either host or hypervisor), and a couple of

[PATCH 32/95] arm/arm64: Add new is_kernel_in_hyp_mode predicate

With ARMv8.1 VHE extension, it will be possible to run the kernel at EL2 (aka HYP mode). In order for the kernel to easily find out where it is running, add a new predicate that returns whether or not the kernel is in HYP mode. For completeness, the 32bit code also get such a predicate (always

[PATCH 35/95] arm64: KVM: Skip HYP setup when already running in HYP

With the kernel running at EL2, there is no point trying to configure page tables for HYP, as the kernel is already mapped. Take this opportunity to refactor the whole init a bit, allowing the various parts of the hypervisor bringup to be split across multiple functions. Reviewed-by: Christoffer

[PATCH 40/95] arm64: KVM: VHE: Split save/restore of registers shared between guest and host

A handful of system registers are still shared between host and guest, even while using VHE (tpidr*_el[01] and actlr_el1). Also, some of the vcpu state (sp_el0, PC and PSTATE) must be save/restored on entry/exit, as they are used on the host as well. In order to facilitate the introduction of a

[PATCH 31/95] arm64: KVM: Switch to C-based stage2 init

There is no real need to leave the stage2 initialization as part of the early HYP bootstrap, and we can easily postpone it to the point where we can safely run C code. This will help VHE, which doesn't need any of this bootstrap. Reviewed-by: Christoffer Dall

[PATCH 36/95] arm64: KVM: VHE: Patch out use of HVC

With VHE, the host never issues an HVC instruction to get into the KVM code, as we can simply branch there. Use runtime code patching to simplify things a bit. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp.S

[PATCH 43/95] arm64: KVM: VHE: Make __fpsimd_enabled VHE aware

As non-VHE and VHE have different ways to express the trapping of FPSIMD registers to EL2, make __fpsimd_enabled a patchable predicate and provide a VHE implementation. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier ---

[PATCH 28/95] ARM: KVM: Remove handling of ARM_EXCEPTION_DATA/PREF_ABORT

These are now handled as a panic, so there is little point in keeping them around. Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/kvm/handle_exit.c | 2 -- 1 file changed, 2 deletions(-) diff --git

[PATCH 33/95] arm64: Allow the arch timer to use the HYP timer

With the ARMv8.1 VHE, the kernel can run in HYP mode, and thus use the HYP timer instead of the normal guest timer in a mostly transparent way, except for the interrupt line. This patch reworks the arch timer code to allow the selection of the HYP PPI, possibly falling back to the guest timer if

[PATCH 37/95] arm64: KVM: VHE: Patch out kern_hyp_va

The kern_hyp_va macro is pretty meaninless with VHE, as there is only one mapping - the kernel one. In order to keep the code readable and efficient, use runtime patching to replace the 'and' instruction used to compute the VA with a 'nop'. Reviewed-by: Christoffer Dall

[PATCH 26/95] ARM: KVM: Cleanup asm-offsets.c

Since we don't have much assembler left, most of the KVM stuff in asm-offsets.c is now superfluous. Let's get rid of it. Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/kernel/asm-offsets.c | 30

[PATCH 30/95] arm/arm64: KVM: Handle out-of-RAM cache maintenance as a NOP

So far, our handling of cache maintenance by VA has been pretty simple: Either the access is in the guest RAM and generates a S2 fault, which results in the page being mapped RW, or we go down the io_mem_abort() path, and nuke the guest. The first one is fine, but the second one is extremely

[PATCH 25/95] ARM: KVM: Turn CP15 defines to an enum

Just like on arm64, having the CP15 registers expressed as a set of #defines has been very conflict-prone. Let's turn it into an enum, which should make it more manageable. Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier ---

[PATCH 34/95] arm64: Add ARM64_HAS_VIRT_HOST_EXTN feature

Add a new ARM64_HAS_VIRT_HOST_EXTN features to indicate that the CPU has the ARMv8.1 VHE capability. This will be used to trigger kernel patching in KVM. Acked-by: Christoffer Dall Acked-by: Catalin Marinas Signed-off-by: Marc Zyngier

[PATCH 29/95] ARM: KVM: Remove __kvm_hyp_exit/__kvm_hyp_exit_end

I have no idea what these were for - probably a leftover from an early implementation. Good bye! Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/include/asm/kvm_asm.h | 3 --- 1 file changed, 3 deletions(-) diff --git

[PATCH 21/95] ARM: KVM: Change kvm_call_hyp return type to unsigned long

Having u64 as the kvm_call_hyp return type is problematic, as it forces all kind of tricks for the return values from HYP to be promoted to 64bit (LE has the LSB in r0, and BE has them in r1). Since the only user of the return value is perfectly happy with a 32bit value, let's make kvm_call_hyp

[PATCH 02/95] ARM: KVM: Move the HYP code to its own section

In order to be able to spread the HYP code into multiple compilation units, adopt a layout similar to that of arm64: - the HYP text is emited in its own section (.hyp.text) - two linker generated symbols are use to identify the boundaries of that section No functionnal change. Acked-by:

[PATCH 19/95] ARM: KVM: Add HYP mode entry code

This part is almost entierely borrowed from the existing code, just slightly simplifying the HYP function call (as we now save SPSR_hyp in the world switch). Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier ---

[PATCH 15/95] ARM: KVM: Add guest entry code

Add the very minimal piece of code that is now required to jump into the guest (and return from it). This code is only concerned with save/restoring the USR registers (r0-r12+lr for the guest, r4-r12+lr for the host), as everything else is dealt with in C (VFP is another matter though).

[PATCH 24/95] ARM: KVM: Remove __weak attributes

Now that the old code is long gone, we can remove all the weak attributes, as there is only one version of the code. Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/kvm/hyp/hyp-entry.S | 4 +--- arch/arm/kvm/hyp/switch.c

[PATCH 20/95] ARM: KVM: Add panic handling code

Instead of spinning forever, let's "properly" handle any unexpected exception ("properly" meaning "print a spat on the console and die"). This has proved useful quite a few times... Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier ---

[PATCH 11/95] ARM: KVM: Add timer save/restore

This patch shouldn't exist, as we should be able to reuse the arm64 version for free. I'll get there eventually, but in the meantime I need a timer ticking. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier ---

[PATCH 14/95] ARM: KVM: Add banked registers save/restore

Banked registers are one of the many perks of the 32bit architecture, and the world switch needs to cope with it. This requires some "special" accessors, as these are not accessed using a standard coprocessor instruction. Reviewed-by: Christoffer Dall Signed-off-by:

[PATCH 16/95] ARM: KVM: Add VFP lazy save/restore handler

Similar to the arm64 version, add the code that deals with VFP traps, re-enabling VFP, save/restoring the registers and resuming the guest. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/kvm/hyp/entry.S | 31

[PATCH 12/95] ARM: KVM: Add vgic v2 save/restore

This patch shouldn't exist, as we should be able to reuse the arm64 version for free. I'll get there eventually, but in the meantime I need an interrupt controller. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier ---

[PATCH 05/95] ARM: KVM: Move CP15 array into the CPU context structure

Continuing our rework of the CPU context, we now move the CP15 array into the CPU context structure. As this causes quite a bit of churn, we introduce the vcpu_cp15() macro that abstract the location of the actual array. This will probably help next time we have to revisit that code. Reviewed-by:

[PATCH 08/95] ARM: KVM: Add system register accessor macros

In order to move system register (CP15, mostly) access to C code, add a few macros to facilitate this, and minimize the difference between 32 and 64bit CP15 registers. This will get heavily used in the following patches. Acked-by: Christoffer Dall Signed-off-by:

[PATCH 13/95] ARM: KVM: Add VFP save/restore

This is almost a copy/paste of the existing version, with a couple of subtle differences: - Only write to FPEXC once on the save path - Add an isb when enabling VFP access The patch also defines a few sysreg accessors and a __vfp_enabled predicate that test the VFP trapping state. Reviewed-by:

[PATCH 07/95] ARM: KVM: Add a HYP-specific header file

In order to expose the various HYP services that are private to the hypervisor, add a new hyp.h file. So far, it only contains mundane things such as section annotation and VA manipulation. Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier

[PATCH 04/95] ARM: KVM: Move VFP registers to a CPU context structure

In order to turn the WS code into something that looks a bit more like the arm64 version, move the VFP registers into a CPU context container for both the host and the guest. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier ---

[PATCH 01/95] arm/arm64: KVM: Add hook for C-based stage2 init

As we're about to move the stage2 init to C code, introduce some C hooks that will later be populated with arch-specific implementations. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/include/asm/kvm_host.h | 4

[PATCH 06/95] ARM: KVM: Move GP registers into the CPU context structure

Continuing our rework of the CPU context, we now move the GP registers into the CPU context structure. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/include/asm/kvm_emulate.h | 8

[PATCH 03/95] ARM: KVM: Remove __kvm_hyp_code_start/__kvm_hyp_code_end

Now that we've unified the way we refer to the HYP text between arm and arm64, drop __kvm_hyp_code_start/end, and just use the __hyp_text_start/end symbols. Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier ---

[PULL] KVM/ARM updates for 4.6

Hi Paolo, Please find below the KVM/ARM updates for 4.6. As you can tell by the explosion of your mailbox, we've been fairly busy lately. Most notable things are PMU support for guests, as well as the v8.1 VHE support. Other than that, the 32bit port went under the knife just like we did for the

Re: [PATCH v3 3/9] irqchip/gic-v2: Gather ACPI specific data in a single structure

Hi Christoffer, On 09/03/2016 12:47, Christoffer Dall wrote: On Tue, Mar 08, 2016 at 11:29:27AM +, Julien Grall wrote: For now, there is only one member. More member will be added later. questionable commit message What about: "The ACPI code requires to use global variables in order

Re: [PATCH v3 9/9] clocksource: arm_arch_timer: Remove arch_timer_get_timecounter

On Tue, Mar 08, 2016 at 11:29:33AM +, Julien Grall wrote: > The only call of arch_timer_get_timecounter (in KVM) has been removed. > > Signed-off-by: Julien Grall > Acked-by: Christoffer Dall > --- > Cc: Daniel Lezcano

Re: [PATCH v3 8/9] KVM: arm/arm64: vgic: Rely on the GIC driver to parse the firmware tables

On Tue, Mar 08, 2016 at 11:29:32AM +, Julien Grall wrote: > Currenlty, the firmware tables are parsed 2 times: once in the GIC Currently, > drivers, the other time when initializing the vGIC. It means code > duplication and make more tedious to add the support for another > firmware table

Re: [PATCH v3 7/9] KVM: arm/arm64: arch_timer: Rely on the arch timer to parse the firmware tables

On Tue, Mar 08, 2016 at 11:29:31AM +, Julien Grall wrote: > The firmware table is currently parsed by the virtual timer code in > order to retrieve the virtual timer interrupt. However, this is already > done by the arch timer driver. > > To avoid code duplication, use the newly function

Re: [PATCH v3 6/9] irqchip/gic-v3: Parse and export virtual GIC information

On Tue, Mar 08, 2016 at 11:29:30AM +, Julien Grall wrote: > Fill up the recently introduced gic_kvm_info with the virtual GIC > information. this is not really virtual GIC information, it's information about the hardware used for virtualization. > > Signed-off-by: Julien Grall

Re: [PATCH v3 2/9] clocksource: arm_arch_timer: Extend arch_timer_kvm_info to get the virtual IRQ

Hi Christoffer, On 09/03/2016 10:27, Christoffer Dall wrote: On Tue, Mar 08, 2016 at 11:29:26AM +, Julien Grall wrote: diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index b7ab588..d8887f3 100644 --- a/drivers/clocksource/arm_arch_timer.c +++

Re: [PATCH v3 3/9] irqchip/gic-v2: Gather ACPI specific data in a single structure

On Tue, Mar 08, 2016 at 11:29:27AM +, Julien Grall wrote: > For now, there is only one member. More member will be added later. questionable commit message > > Signed-off-by: Julien Grall > > --- > Cc: Thomas Gleixner > Cc: Jason Cooper

Re: [PATCH v3 5/9] irqchip/gic-v3: Gather all ACPI specific data in a single structure

On Tue, Mar 08, 2016 at 11:29:29AM +, Julien Grall wrote: > Even though all the variables aren't marked with __initdata, they are > only used during initialization. So the structure is marked with > __initdata. Not sure I understand this commit message. As I see it, this commit includes two

Re: [PATCH v3 1/9] clocksource: arm_arch_timer: Gather KVM specific information in a structure

Hi Christoffer, On 09/03/2016 10:23, Christoffer Dall wrote: On Tue, Mar 08, 2016 at 11:29:25AM +, Julien Grall wrote: -static struct timecounter timecounter; +static struct arch_timer_kvm_info arch_timer_kvm_info; + +struct arch_timer_kvm_info *arch_timer_get_kvm_info(void) borderline

Re: [PATCH v3 4/9] irqchip/gic-v2: Parse and export virtual GIC information

On Tue, Mar 08, 2016 at 11:29:28AM +, Julien Grall wrote: > For now, the firmware tables are parsed 2 times: once in the GIC > drivers, the other timer when initializing the vGIC. It means code > duplication and make more tedious to add the support for another > firmware table (like ACPI). >

Re: [PATCH v3 2/9] clocksource: arm_arch_timer: Extend arch_timer_kvm_info to get the virtual IRQ

On Tue, Mar 08, 2016 at 11:29:26AM +, Julien Grall wrote: > Currently, the firmware table is parsed by the virtual timer code in > order to retrieve the virtual timer interrupt. However, this is already > done by the arch timer driver. > > To avoid code duplication, extend arch_timer_kvm_info

Re: [PATCH v3 1/9] clocksource: arm_arch_timer: Gather KVM specific information in a structure

On Tue, Mar 08, 2016 at 11:29:25AM +, Julien Grall wrote: > Introduce a structure which are filled up by the arch timer driver and > used by the virtual timer in KVM. > > The first member of this structure will be the timecounter. More members > will be added later. > > A stub for the new

Re: [PATCH v3 11/12] arm64: KVM: vgic-v3: Reset LRs at boot time

On Mon, Mar 07, 2016 at 09:33:33AM +, Marc Zyngier wrote: > In order to let the GICv3 code be more lazy in the way it > accesses the LRs, it is necessary to start with a clean slate. > > Let's reset the LRs on each CPU when the vgic is probed (which > includes a round trip to EL2...). > >

Re: [PATCH v3 06/12] KVM: arm/arm64: vgic-v2: Only wipe LRs on vcpu exit

On Mon, Mar 07, 2016 at 09:33:28AM +, Marc Zyngier wrote: > So far, we're always writing all possible LRs, setting the empty > ones with a zero value. This is obvious doing a lot of work for > nothing, and we're better off clearing those we've actually > dirtied on the exit path (it is very

Re: [PATCH v3 05/12] KVM: arm/arm64: vgic-v2: Reset LRs at boot time

On Mon, Mar 07, 2016 at 09:33:27AM +, Marc Zyngier wrote: > In order to let make the GICv2 code more lazy in the way it > accesses the LRs, it is necessary to start with a clean slate. > > Let's reset the LRs on each CPU when the vgic is probed. > > Signed-off-by: Marc Zyngier

[PATCH v3 7/9] KVM: arm/arm64: arch_timer: Rely on the arch timer to parse the firmware tables

The firmware table is currently parsed by the virtual timer code in order to retrieve the virtual timer interrupt. However, this is already done by the arch timer driver. To avoid code duplication, use the newly function arch_timer_get_kvm_info() which return all the information required by the

[PATCH v3 8/9] KVM: arm/arm64: vgic: Rely on the GIC driver to parse the firmware tables

Currenlty, the firmware tables are parsed 2 times: once in the GIC drivers, the other time when initializing the vGIC. It means code duplication and make more tedious to add the support for another firmware table (like ACPI). Use the recently introduced helper gic_get_kvm_info() to get

[PATCH v3 0/9] arm64: Add support of KVM with ACPI

Hello, This patch series allows an ARM64 ACPI based platform to use KVM. Currently the KVM code has to parse the firmware table to get the necessary information to setup the virtual timer and virtual GIC. However the parsing of those tables are already done in the GIC and arch timer drivers.

[PATCH v3 9/9] clocksource: arm_arch_timer: Remove arch_timer_get_timecounter

The only call of arch_timer_get_timecounter (in KVM) has been removed. Signed-off-by: Julien Grall --- Cc: Daniel Lezcano Cc: Thomas Gleixner Changes in v3: - Patch added ---

[PATCH v3 4/9] irqchip/gic-v2: Parse and export virtual GIC information

For now, the firmware tables are parsed 2 times: once in the GIC drivers, the other timer when initializing the vGIC. It means code duplication and make more tedious to add the support for another firmware table (like ACPI). Introduce a new structure and set of helpers to get/set the virtual GIC

[PATCH v3 6/9] irqchip/gic-v3: Parse and export virtual GIC information

Fill up the recently introduced gic_kvm_info with the virtual GIC information. Signed-off-by: Julien Grall Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier --- Changes in v3: - Add ACPI

[PATCH v3 5/9] irqchip/gic-v3: Gather all ACPI specific data in a single structure

Even though all the variables aren't marked with __initdata, they are only used during initialization. So the structure is marked with __initdata. Signed-off-by: Julien Grall --- Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc

[PATCH v3 2/9] clocksource: arm_arch_timer: Extend arch_timer_kvm_info to get the virtual IRQ

Currently, the firmware table is parsed by the virtual timer code in order to retrieve the virtual timer interrupt. However, this is already done by the arch timer driver. To avoid code duplication, extend arch_timer_kvm_info to get the virtual IRQ. Note that the KVM code will be modified in a

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