+ linaro-toolchain as I don't understand the CI issues on patchwork.
On Wed, Sep 27, 2023 at 8:40 PM Wilco Dijkstra wrote:
>
> Hi Ramana,
>
> > Hope this helps.
>
> Yes definitely!
>
> >> Passes regress/bootstrap, OK for commit?
> >
> > Target ? armhf ? --with-arch , -with-fpu , -with-float
On 04/06/2018 19:12, Richard Henderson wrote:
On 06/04/2018 11:00 AM, Adhemerval Zanella wrote:
Do you plan to adapt them to glibc?
Ramana suggested starting "upstream" in cortex-strings and copying to glibc
from there, as a general work-flow preference. I believe this has been the
case for
On 04/06/2018 19:30, Richard Henderson wrote:
On 06/04/2018 11:19 AM, Adhemerval Zanella wrote:
Yes, using cortex-strings as the bridge is indeed the preferred way. I am
asking which strategy do you see:
- Adding ifunc variants and add them as default if system advertise SVE
support.
On 31/03/16 18:26, Jim Wilson wrote:
> On Thu, Mar 31, 2016 at 5:12 AM, fengwei.yin wrote:
>> Because gcc 4.9 could build this file without any issue, I apply
>> --save-temps
>> with gcc 4.9. The ii file is attached. Can't see significant differences.
>
> There is a patch
On 31/03/16 18:26, Jim Wilson wrote:
> On Thu, Mar 31, 2016 at 5:12 AM, fengwei.yin wrote:
>> Because gcc 4.9 could build this file without any issue, I apply
>> --save-temps
>> with gcc 4.9. The ii file is attached. Can't see significant differences.
>
> There is a patch
On 24/03/16 13:14, Vitali Sokhin wrote:
> Hi all,
>
>
> Is there a roadmap for adding support for ARMv8.2 ? Specifically for
> assembler to support new instructions and SPRs?
FSF binutils-2.26 has aarch64 support for v8.2.
FSF binutils trunk (or what will be FSF binutils-2.27) will have aarch32
On 21/03/16 04:30, Prathamesh Kulkarni wrote:
> == This Week ==
>
> * LTO (3/10)
> a) section anchors:
> - prototype patch to bind functions to global vars
> - looked at balanced partitioning
> b) chromium LTO build fails with ICE on trunk for arm-linux-gnueabihf:
> http://pastebin.com/sX6yKLBP
-Original Message-
From: linaro-toolchain-boun...@lists.linaro.org [mailto:linaro-
toolchain-boun...@lists.linaro.org] On Behalf Of Wookey
Sent: 23 February 2014 20:43
To: Rob Savoye
Cc: Linaro ToolChain
Subject: Re: [Weekly] 17-21 FEB 2013
+++ Rob Savoye [2014-02-23 08:05
This one didn't do as well as expected as it ended up causing more
zero extends than necessary if my memory serves me right. This could be
a course for a low priority future blueprint.
Dropped. This plus flag_ree in the future?
I'm not so sure that flag_ree will help AArch32 in the future
-Original Message-
From: Michael Hope [mailto:michael.h...@linaro.org]
Sent: 12 December 2012 22:54
To: Ramana Radhakrishnan
Cc: linaro-toolchain@lists.linaro.org
Subject: Clearing out past branches
Hi Ramana. You have the following branches remaining on Launchpad:
* lp
Yvan,
LDAR is intended for an atomic load acquire. See
http://gcc.gnu.org/ml/gcc-patches/2012-11/msg01397.html
for compiler support upstream.
regards,
Ramana
-Original Message-
From: linaro-toolchain-boun...@lists.linaro.org [mailto:linaro-
toolchain-boun...@lists.linaro.org] On
From: Yvan Roux [yvan.r...@linaro.org]
Sent: 25 November 2012 19:51
To: Ramana Radhakrishnan
Cc: linaro-toolchain@lists.linaro.org
Subject: Re: Atomic builtins questions
That is correct. The addresses need to be aligned as per the restrictions in
the architecture. Yes we could have
I don't recall talking about hot cold partitioning and EEMBC .
I'm assuming this is regarding the SPEC2k failure that I've been debugging.
Thanks,
Ramana
From: linaro-toolchain-boun...@lists.linaro.org
[linaro-toolchain-boun...@lists.linaro.org] On
,
Ramana
From: Yvan Roux [mailto:yvan.r...@linaro.org]
Sent: 23 November 2012 10:29
To: Ramana Radhakrishnan
Cc: linaro-toolchain@lists.linaro.org
Subject: Re: Atomic builtins questions
Hi Ramana and Peter,
There is no issue in the first case. You are correct that the dmb's there are
to ensure
Hi Yvan,
There is no issue in the first case. You are correct that the dmb's there are
to ensure the sequential consistency as you'd want to see with __ATOMIC_SEQ_CST
in the call to the builtin. However what you must remember is that STRs are
guaranteed to be single-copy atomic by the
From: Zhenqiang Chen [zhenqiang.c...@linaro.org]
Sent: 16 October 2012 04:44
To: Ramana Radhakrishnan
Cc: linaro-toolchain
Subject: Re: Add dwarf/unwind info in epilogue
On 16 October 2012 10:22, Ramana Radhakrishnan
ramana.radhakrish...@arm.com wrote:
Zhenqiang,
I've been
Ramana Radhakrishnan
ARM Ltd.
On 15 Oct 2012, at 10:57, Zhenqiang Chen zhenqiang.c...@linaro.org wrote:
Hi Ramana,
The attached file is a reference patch to add more dwarf/unwind info
in epilogue. Please help to review.
Without the patch, dwarf check fail for the following cases when
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-08-07
Any updates please let me know or add to the wiki page as appropriate ?
Ramana
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== Progress ==
* Fixed PR54051
* Improved neon intrinsics testsuite. While still not an execution
based testsuite atleast we get compile time tests that are sensible C.
Exposed issues - wrote patches.
that improve vabal , vaba intrinsics. Fix an issue with costs,
fixed an issue with
Hi Steven,
Nice to hear from you.
On 23 July 2012 19:25, Steven Bosscher stevenb@gmail.com wrote:
Hello Ramana,
For your PGO list:
* please note that I've been working on PGO for switch code, and also
for chains of if-statements with a common condition variable (with Tom
de Vries)
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-07-24
is now online. If folks have anything they'd like to add can they do so ?
Ramana
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The Linaro Toolchain Working Group is pleased to announce the 2012.07
release of both Linaro GCC 4.7 and Linaro GCC 4.6.
Linaro GCC 4.7 2012.07 is the fourth release in the 4.7 series. Based
off the latest GCC 4.7.0+svn189098 release, it includes performance
improvements around choice of
On 6 July 2012 16:52, Mans Rullgard mans.rullg...@linaro.org wrote:
I ran my usual set of benchmarks of libav compiled with the current gcc
releases (hand-written assembly disabled). The results are in this
spreadsheet:
On 6 July 2012 00:10, Michael Hope michael.h...@linaro.org wrote:
Hi Ramana. These are covered by the release process documentation but
I thought I'd fill them out.
The builds are completing. You can see the finished grid at:
http://ex.seabright.co.nz/helpers/buildlog/gcc-linaro-4.7-2012
Thanks for doing this yet again.
On 6 July 2012 16:52, Mans Rullgard mans.rullg...@linaro.org wrote:
I ran my usual set of benchmarks of libav compiled with the current gcc
releases (hand-written assembly disabled). The results are in this
spreadsheet:
RAG
Amber: 4.7 2012.07 source release for reasons described below.
Green : 4.6 2012.07 source release done.
== Progress ==
* Worked on auto-inc-dec scheduler changes.First cut patch looking reasonable.
* Committed the neon permute intrinsics upstream.
* Release week : release tarballs
== Progress ==
* Testing costs changes for Neon intrinsics.
* Fixed the regression I added to the Linaro 4.6 tree - committed
there. Looked at a few vagaries around testresults.
* Started looking at auto-inc-dec scheduler changes.
* 1/2 a day lost to visa application process
* Usual 1:1s .
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-07-03
Ramana
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On 29 June 2012 07:52, Zhenqiang Chen zhenqiang.c...@linaro.org wrote:
Another two cases fail in precise test:
-PASS: c-c++-common/simulate-thread/bitfields-3.c -O0 -g thread simulation
test
+UNSUPPORTED: c-c++-common/simulate-thread/bitfields-3.c -O0 -g thread
simulation test
-PASS:
== Progress ==
* Tried a number of testcases for the shuffles . Needed to add
support to the C++ frontend for the __builtin_shuffle support.
Fortunately there existed a patch - I tested it and it looked good.
Committed upstream. However the original author had some concerns
whether it would work
I noticed this bug upstream about C++11 and C++98 ABI
incompatibilities , in case someone is using the C++11 features,
please be aware that there is an ABI bug lurking.
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53646
Ramana
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== Progress ==
* Connect last week.
* Worked through the open issues and open work items related to
performance and we've got a clear list of things that are currently in
flight. Now to keep track of this better.
https://wiki.linaro.org/RamanaRadhakrishnan/Sandbox//RRQ212ConnectNotes
and move
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-06-12
Rather late but it's just been effectively a week since Connect. The
only additional thing I've added is the vectorizer cost model and the
libav regression that Mans discovered .
regards,
Ramana
Thanks to the change in the schedule the agenda is here.
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-05-28
If there are any topics folks would like to add to this for today
please feel free to do so now given we have a session in under 2
hours.
regards,
Ramana
Progress
* Proposed backport for vfp addressing modes patch.
* Investigated the build issue with EEMBC and have a candidate patch
for upstream trunk. (PR53334)
* Investigated auto-inc-dec sched changes.
* Some upstream patch review.
Plans
* Work on auto-inc-dec sched changes.
* Finish PR53334
On 16 May 2012 10:04, Michael Hope michael.h...@linaro.org wrote:
Hi Ramana. FYI, gcc trunk fails to bootstrap with:
../../../../gcc-4.8~/libgcc/libgcc2.c: In function '__mulvdi3':
../../../../gcc-4.8~/libgcc/libgcc2.c:397:1: internal compiler error:
in df_uses_record, at df-scan.c:3179
A
On 16 May 2012 13:41, Mans Rullgard mans.rullg...@linaro.org wrote:
On 16 May 2012 10:29, Ramana Radhakrishnan
ramana.radhakrish...@linaro.org wrote:
On 16 May 2012 10:04, Michael Hope michael.h...@linaro.org wrote:
Hi Ramana. FYI, gcc trunk fails to bootstrap with:
../../../../gcc-4.8
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-05-15
I've put together an initial version of the blueprints we could consider .
Are there any other topics that folks are interested in adding ? If
so, could you add it to the wiki page.
Thanks,
Ramana
Short week given bank holiday
Progress
* Committed the VFP addressing modes patch.
* Investigated PR48941 patch a bit more - looks like an issue with the
register allocator around vzip and vuzp patterns and not sure what the
easiest way of sorting this really is. I wonder if we should be
looking
.
Ramana
Regards
RKS
-Original Message-
From: linaro-toolchain-boun...@lists.linaro.org
[mailto:linaro-toolchain-boun...@lists.linaro.org] On Behalf Of Ramana
Radhakrishnan
Sent: Monday, April 30, 2012 3:44 AM
To: Ulrich Weigand
Cc: linaro-toolchain
Subject: Vectorization paper
causing such a regression.
For the record this was just a pointer to a paper that might be of
interest . I haven't really investigated the kernels to see how useful
they really are :) .
regards,
Ramana
Regards
RKS
-Original Message-
From: Ramana Radhakrishnan [mailto:ramana.radhakrish
=== Progress ===
* Worked on the VFP addressing modes patch upstream. Handled most
comments. Final version has finished testing and looks almost ready to
commit.
* Investigated an issue with min type transformations for loop
terminating conditions. Wrote up a small patch which appears to do the
On 11 April 2012 17:21, Mans Rullgard mans.rullg...@linaro.org wrote:
On 11 April 2012 16:16, Ulrich Weigand ulrich.weig...@de.ibm.com wrote:
Singh, Ravi Kumar (Ravi) ravi.si...@lsi.com wrote:
Are there any pragmas for selectively disabling (in one chunk of
code) the vectorization, when its
=== Progress ===
* Worked on VFP addressing patch and corrected the failures.
* Got SPEC2k up and running with hot cold partitioning. Some SEGVs
that need investigation. In
general results appear to be better in quite a few cases.
* Investigated an issue with a merge request for upstream 4.7
On 5 April 2012 09:58, Ramana Radhakrishnan
ramana.radhakrish...@linaro.org wrote:
Hi there,
At the last call Michael asked if we could push this call back by 30
minutes given the changes due to daylight savings. Does anyone have
any objections to a new time of 10 a.m. BST - 11 a.m. Central
Anyway, I doubt there's anybody else needs to know this: I've just posted it
in case I get hit by a bus before next month.
It's probably something that should be documented and linked from
BzrTips or a how to do an upstream merge in the toolchain wiki (if
we had something like that ) ?
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-04-03
If there's anything people would like to add please do so on the wiki page.
Ramana
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I've written up a blueprint for Shrink-wrapping here.
https://blueprints.launchpad.net/gcc-linaro/+spec/shrink-wrapping
Comments are welcome.
Ramana
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=== Progress ===
* Caught up on email backlog.
* Reworked the ARM backend specific bits of the VFP addressing modes
patch and submitted again for some benchmarking and testing. Finished
the PRE_MODIFY and POST_MODIFY bits of that as well.
* Wrote up a small blueprint on the shrink-wrapping work.
== Progress ===
* Off sick for 4 days last week.
* Looked at the results for the vfp writeback modes and caught up with
some analysis on the one day I did work.
=== Plans ===
* Catch up on email after absences.
* Catch up on patches backlog
Absences.
* Apr 12-13 : Euro-LLVM London.
* 1 week
==Progress===
* Did some work to improve code generation for addressing modes in VFP
registers.
* Looked at some more cases and detected that there are 2 areas of
improvement for
the future
* shrink-wrapping
* Too many unnecessary ldm / stm stacking for cases with small
structures being
== Issues ==
It would be nice to have perf installed on the porter boxes in the
canonical data center as well if we are allowed to run benchmarks
there. Filed RT request.
==Progress===
* Understood STB_GNU_UNIQUE_NOTE - Helped fix a problem with compiz
crashing but then it was a very nice
Matthias,
https://bugs.launchpad.net/gcc-linaro/+bug/949805
This affects ubuntu-gcc as well and the work around is to try the
--enable-gnu-unique-object compiler configure time flag. Could you try
to rebuild a toolchain with the configure option
--enable-gnu-unique-object and check if tests
On 8 March 2012 21:24, Michael Hope michael.h...@linaro.org wrote:
On 9 March 2012 07:08, Ken Werner ken.wer...@linaro.org wrote:
On 03/08/2012 09:03 AM, Marcin Juszkiewicz wrote:
Ah, thanks - I forgot about that. It saves about 16GB of space and running
on tmpfs saves about 30 minutes on my
(Hit send too soon on my last mail and appear to have removed linaro-toolchain
Apologies to those who get duplicates)
On Tue, Mar 06, 2012 at 04:00:36PM +, Andrew Stubbs wrote:
Hi Alexandros,
Could you use the linaro-toolchain list for stuff like this please?
You're more likely to find
On holiday last week and at connect week before that.
==Progress===
* Recovered from jet-lag and started to catch up on email.
* Patch review week.
* Cleared out a bit of my patch backlog.
* Helped Asa with some bug triaging.
* Read up a bit about ssat and usat and what we should be doing with
Hi ,
This is now at :
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-02-07
Please add any topics that need to be added in the wiki page.
Thanks,
Ramana
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The Linaro Toolchain Working Group is pleased to announce the 2012.02
release of Linaro GCC 4.6 and Linaro GCC 4.5.
Linaro GCC 4.6 2012.02 is the twelfth release in the 4.6 series. Based
off the latest GCC 4.6.2+svn183786, it contains a few bug
fixes and backports Cortex-A7 and Cortex-A15 support
On 1 February 2012 19:33, Ulrich Weigand ulrich.weig...@de.ibm.com wrote:
Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote on 01.02.2012
16:28:04:
This patch should be queued for 4.8 .Sounds sensible to me.
OK, thanks for the review!
(As an aside, it might likewise be helpful
Hi Michael,
On 2 February 2012 02:44, Michael Hope michael.h...@linaro.org wrote:
I've set up a new user on my laptop that we can use for experimenting
with benchmarks during Connect. Here's what we've got:
* A user called 'connect'
* Ramana, Ulrich, Åsa, and myself can log in via SSH
Hi Uli,
Thanks for the detailed analysis.
The reason for this particular code sequence turns out to be as follows:
The middle end tries to store the LSB vector lane to memory, and uses the
vec_extract named pattern to do so. This pattern currently only supports
an s_register_operand
On 1 February 2012 19:33, Ulrich Weigand ulrich.weig...@de.ibm.com wrote:
Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote on 01.02.2012
16:28:04:
This patch should be queued for 4.8 .Sounds sensible to me.
OK, thanks for the review!
(As an aside, it might likewise be helpful
On 1 February 2012 23:08, Ramana Radhakrishnan
ramana.radhakrish...@linaro.org wrote:
On 1 February 2012 19:33, Ulrich Weigand ulrich.weig...@de.ibm.com wrote:
Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote on 01.02.2012
16:28:04:
This patch should be queued for 4.8 .Sounds
Attempted to create a Linaro GCC 4.7 branch, but my test build failed, so
that'll have to wait until it's stabilized a little.
There was a problem last week with libstdc++ builds last week but
AFAIK it's all now been fixed. FSF 4.7 bootstrapped fine last on
Sunday as per what I've seen on
==Progress===
* Fixed PR48308 on FSF trunk. Needs backporting to FSF GCC 4.6 branch
* Fixed a number of failing testcases on trunk.
* Read up on Partial-partial PRE . Slow progress but getting a handle
on the theory now. A couple of approaches being benchmarked . Still
slow progress.
*
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-01-24
do folks have anything to add to this ?
Ramana
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==Progress===
* Backported one part of the partial-partial PRE patch . Still looking into it.
* Investigate PR48308 - a bug where combine was generating incorrect
transformations.
* Reopened PR50313 - a bug which I originally thought was a dup of PR48308.
* Looked at upstream bugzilla for
Hi,
Does anyone have anything they'd like to bring up in tomorrow's
performance call. ? I don't have any topics other than following on
action items from last time's call - which was comparing movw/ movt
with constant pools .
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-01-10
On 29 December 2011 10:21, Richard Sandiford
richard.sandif...@linaro.org wrote:
The remaining change for neon-strided-load-extract is to allow fwprop.c
to propagate:
(set (reg X) (subreg (reg Y) N))
even if no further simplifications are possible. I posted the original
patch for
On 3 January 2012 15:29, Andy Doan andy.d...@linaro.org wrote:
anyone have a suggestion for this person?
Done on the forum
Ramana
Original Message
Subject: New question: problem in installing Linaro tools on Ask Linaro
Date: Mon, 26 Dec 2011 21:31:57 -0800 (PST)
Hi,
If folks want to put anything on the agenda can you please add it to
the wiki page here ?
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2011-12-13
Ramana
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TaskPlanned Estimated Actual
Historical
~~~
Connect 2011.q4
preparation 28/10/2011 28/10/2011
28/10/2011
Linaro Tasks
Fully Investigate the O3
performance
regressions
On 30 November 2011 20:28, Michael Hope michael.h...@linaro.org wrote:
On Thu, Dec 1, 2011 at 12:20 AM, Ira Rosen ira.ro...@linaro.org wrote:
On 30 November 2011 02:33, Michael Hope michael.h...@linaro.org wrote:
Peeling and using the vld1.i64 {d16-d17}, [r1:64]! form should be
faster for
==Progress===
* Off sick on Monday
* Systematic testing duty - few Aarch64 issues.
* Linaro patch review duty.
* Tested my vcvt fixed point patch and close to committing.
* Worked on sometime on movw / movt for symbol references rather than
constant pools . While this gives nice benefits it's a
Hi,
Now that upstream trunk is in stage3 and we have a few patches that
won't really make it upstream until stage1 is reopened is it
worthwhile having a new status in the merge requests that moves it
into a to_upstream status . The other option is to have a common
spreadsheet that we keep
On 29 November 2011 12:04, Richard Sandiford
richard.sandif...@linaro.org wrote:
Ramana Radhakrishnan ramana.radhakrish...@linaro.org writes:
Now that upstream trunk is in stage3 and we have a few patches that
won't really make it upstream until stage1 is reopened is it
worthwhile having a new
BTW, is hard float mode, are 64-bit integers passed in core-regs still? I
expect so, since hard-float doesn't imply neon, but it would probably be a
bonus if they were passed in neon registers.
They are still passed in the core registers . It would be worth noting
in any case that the VFP and
RAG :
RED : None
AMBER: Worried about trunk failures with test runs. Number of
testsuite failures after the atomics merge has increased - more below.
.
TaskPlanned Estimated Actual
Historical
~~~
Connect 2011.q4
preparation
On 15 November 2011 09:19, Richard Sandiford
richard.sandif...@linaro.org wrote:
Revital Eres revital.e...@linaro.org writes:
chain, so what makes the SMS version of it worse than the non-SMS version?
I attached the SMS dump file. The problematic loop is the one with
SMS succeeded 36 2 (there
PR51068 appears to be a dup of
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51051 . I've kicked off a
build on habitat.canonical.com with this patch applied to be sure that
the build and test continues
http://gcc.gnu.org/ml/gcc-patches/2011-11/txt00199.txt
Ramana
Hi,
I've now put this at :
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2011-11-15
Are there any other topics that folks want to bring up ?
The one thing worth thinking about ahead of time is if we want to
bring ahead the call by an hour to allow Michael to join at a not so
crazy
We are trying to organise a phone and merge this with the pgo session.
Sorry about the short notice.
Ramana
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==Progress===
* Off for one day during the week for Diwali.
* Connect preparation - Wrote down areas to look at during connect and
tried to plan what we
want to look at during connect.
* Looked at some of the cases with vcondfloat with Ira and helped
frame blueprint.
* Investigated one of the
Hi Folks,
I've been trying to capture what we want to do in terms of hacking
time and some of the performance related backlog that we have in the
system. I have done so here.
https://wiki.linaro.org/RamanaRadhakrishnan/Sandbox/Q411ConnectGCCPerfPlan
I'm on vacation tomorrow but should be
Hi Folks,
Draft agenda for the performance meeting next week at Connect -
https://blueprints.launchpad.net/gcc-linaro/+spec/linaro-toolchain-performance-meeting
Are there any topics that people would like to bring up during this
meeting other than the ones listed here ? I suspect that we'll
==Progress===
* Some upstream patch review.
* Spent time looking at LP 836588 which is a case where CSE removes a
particular label access in one case but doesn't remove it from the
list of things in the constant pool which is quite bizarre. Will
probably need some help with looking into this one.
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2011-10-18
I don't have much for this week personally given I've had 2 very short weeks.
Ramana
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Short week with 2 days gone on an internal training course
==Progress===
* Some patch review.
* Spent time looking at LP 836588.
* Tried some different approaches for the vcvt.f64.s32 case and it
looks like the simple solution is the best one unfortunately :(
* 2 days off at internal training
==Progress===
* Out of office for a day.
* Wrote a quick patch to do vcvt.f32.s32 with fractional bits where we
can. Tested no regressions, need to commit this after review upstream.
* Desk move and packing for that.
* Looked at a bug report LP 836588 appears to go away with fno-gcse.
Needs more
patterns
need to be written up at some point for completeness )
cheers
Ramana
2011-10-04 Ramana Radhakrishnan ramana.radhakrish...@linaro.org
* config/arm/arm.c (vfp3_const_double_for_fract_bits): Define.
* config/arm/arm-protos.h (vfp3_const_double_for_fract_bits): Declare
==GCC==
Combined report for last 2 weeks -
===Progress===
* Committed conditional compares patch to Linaro GCC 4.6
* Looking at modelling auto-inc-decs better .
* Tried patch for PR19599 and that broke bootstrap with a segfault.
Needs some re-engineering.
* Looked at the latest bootstrap
==GCC==
===Progress===
* Fixed https://bugs.launchpad.net/ubuntu/+source/gcc-4.6/+bug/838994
. Investigated Bernd's alternate patch . Will commit mine.
* Looked at PR48308 for sometime whihc might be a dup of PR50313 .
* Some blueprint foo.
* Committed a few of the outstanding approved patches
==GCC==
===Progress===
* Looked at the vectorize_with_neon_quad failure again and decided
that I had to handle another case but not convinced that the extra
stall we'd get in this case was worth it. In any case it would have
been a workaround but Richard Sandiford fixed this by getting df to do
On 23 August 2011 12:20, Revital Eres revital.e...@linaro.org wrote:
SMS flags to use for testing:
-O3 -fmodulo-sched-allow-regmoves -fmodulo-sched
-funsafe-loop-optimizations -fno-auto-inc-dec
Would we expect -funsafe-loop-optimizations to be turned on as well by
default ? I would expect
On 22 August 2011 13:35, Christian Robottom Reis k...@linaro.org wrote:
On Fri, Aug 19, 2011 at 04:38:51PM +0100, Ramana Radhakrishnan wrote:
* Having some problems getting my panda board working reliably. I'm
not sure if its the temperature or what but when it gets hot in the
office
Hi,
I've put up the agenda for tomorrow's call here.
https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2011-08-23
Please feel free to add to the agenda if there's something we want to
bring up for discussion.
cheers
Ramana
___
. Would you be interested in adding a Firefox-based benchmark? As a large
application it is a good testbed for LTO, FDO and other aggressive
optimizations.
Sorry about the delayed response. I did notice your mail last week but
I was busy with our conference and then the first couple of days
Given I'm away at some internal training and we had one last week . I
decided to cancel this.
Ramana
___
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linaro-toolchain@lists.linaro.org
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== GCC ==
=== Progress ===
* ivopts patch to minimise the amount of VFP moves to integer
registers because of auto-inc - sent out for review. It appears to
test fine and reduces the number of FP to integer moves in certain
SPEC2k6 benchmarks by about 20%
* More cases with vfp moves identified
== Progress ==
* Backported A5 / A15 tuning to Linaro GCC. Waiting for test results.
* T2 perf. meeting.
* Backported the neon length patch back.
* Patch for PR49385 being tested.
* Bootstraps broken yet again / upstream maintenance / test regressions.
* Waiting on Branch_cost results .
* Minor
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