AF_ALG data chunk size

Hello, i'm playing a bit with AF_ALG and found a strange problem: it looks like big data chunks (64K) can lead to error. what i do: 1. take a file, read some data (8 or 64K), encrypt, write to crypted-file, repeat until EOF. 2. read crypted-file, with the same chunk size, decrypt, write to

[PATCH v3 0/6] crypto: SHA1 multibuffer implementation

Herbert, Thanks for your suggestion to flush the jobs when cpu goes to idle. I've updated the code to flush the unfinished jobs in the lanes when the cpu goes to idle, to take advantage of the available cpu cycles for processing. This should minimize any latency for the multi-buffer algorithm.

[PATCH v3 6/6] crypto: SHA1 multibuffer - flush the jobs before going into idle

This patch adds a notifier to the SHA1 multi-buffer algorithm when CPU is giong idle, so it can take advantage of the available CPU power to flush out any partially completed jobs. This will eliminate possible extended latency in the multi-buffer algorithm. Signed-off-by: Tim Chen

[PATCH v3 4/6] crypto: SHA1 multibuffer crypto computation (x8 AVX2)

This patch introduces the assembly routines to do SHA1 computation on buffers belonging to serveral jobs at once. The assembly routines are optimized with AVX2 instructions that have 8 data lanes and using AVX2 registers. Signed-off-by: Tim Chen tim.c.c...@linux.intel.com ---

[PATCH v3 2/6] crypto: SHA1 multibuffer algorithm data structures

This patch introduces the data structures and prototypes of functions needed for computing SHA1 hash using multi-buffer. Included are the structures of the multi-buffer SHA1 job, job scheduler in C and x86 assembly. Signed-off-by: Tim Chen tim.c.c...@linux.intel.com ---

[PATCH v3 3/6] crypto: SHA1 multibuffer submit and flush routines for AVX2

This patch introduces the routines used to submit and flush buffers belonging to SHA1 crypto jobs to the SHA1 multibuffer algorithm. It is implemented mostly in assembly optimized with AVX2 instructions. Signed-off-by: Tim Chen tim.c.c...@linux.intel.com ---

[PATCH v3 1/6] crypto: SHA1 multibuffer crypto hash infrastructure

This patch introduces the multi-buffer crypto daemon which is responsible for submitting crypto jobs in a work queue to the responsible multi-buffer crypto algorithm. The idea of the multi-buffer algorihtm is to put data streams from multiple jobs in a wide (AVX2) register and then take advantage

[PATCH v3 5/6] crypto: SHA1 multibuffer scheduler

This patch introduces the multi-buffer scheduler which is responsible for submitting scatter-gather buffers from several SHA1 jobs to the multi-buffer algorithm. It also contains the flush routine to that's called by the crypto daemon to complete the job when no new jobs arrive before the

Re: [PATCH] crypto:caam - Modify width of few read only registers

On Tue, 29 Apr 2014 15:34:37 +0530 Ruchika Gupta ruchika.gu...@freescale.com wrote: Few read only registers like CHAVID, CTPR etc were wrongly defined as 64 bit registers. This functioned properly on the powerpc platforms. However ARM SoC's wouldn't function correctly if these registers are