[PATCH v11 4/5] crypto: Add Allwinner Security System crypto accelerator

Add support for the Security System included in Allwinner SoC A20. The Security System is a hardware cryptographic accelerator that support: - MD5 and SHA1 hash algorithms - AES block cipher in CBC/ECB mode with 128/196/256bits keys. - DES and 3DES block cipher in CBC/ECB mode Signed-off-by:

[PATCH v11 5/5] MAINTAINERS: Add myself as maintainer of Allwinner Security System

Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2d3d55c..308da53 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -556,6 +556,12 @@ S: Maintained F:

[PATCH v11 3/5] ARM: sun4i: dt: Add DT bindings documentation for SUN4I Security System

This patch adds documentation for Device-Tree bindings for the Security System cryptographic accelerator driver. Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com --- Documentation/devicetree/bindings/crypto/sun4i-ss.txt | 19 +++ 1 file changed, 19 insertions(+) create

[PATCH v11] crypto: Add Allwinner Security System crypto accelerator

Hello This is the driver for the Security System included in Allwinner SoC A20. The Security System (SS for short) is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG algorithms. It could be found on others Allwinner SoC: - A10, A10s, A13, A31 and A33 manual give the

[PATCH v11 1/5] ARM: sun4i: dt: Add Security System to A10 SoC DTS

The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG algorithms. It could be found on many Allwinner SoC. This patch enable the Security System on the Allwinner A10 SoC Device-tree. Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com ---

[PATCH 2/4] crypto: caam - fix snooping for write transactions

HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010, i.e. AXI3 Cacheable bit set. For platforms that have HW coherency support: -PPC-based: the update has no effect; CAAM coherency already works due

[PATCH 1/4] crypto: caam - fix ERA property reading

From: Alex Porosanu alexandru.poros...@freescale.com In order to ensure that the ERA property is properly read from DT on all platforms, of_property_read* function needs to be used. Signed-off-by: Alex Porosanu alexandru.poros...@freescale.com Signed-off-by: Horia Geantă

[PATCH 4/4] crypto: caam - fix warning in APPEND_MATH_IMM_u64

From: Tudor Ambarus tudor.amba...@freescale.com An implicit truncation is done when using a variable of 64 bits in MATH command: warning: large integer implicitly truncated to unsigned type [-Woverflow] Silence the compiler by feeding it with an explicit truncated value. Signed-off-by: Tudor

[PATCH 3/4] crypto: caam - fix RNG init descriptor ret. code checking

When successful, the descriptor that performs RNG initialization is allowed to return a status code of 7000_h, since last command in the descriptor is a JUMP HALT. Signed-off-by: Horia Geantă horia.gea...@freescale.com --- drivers/crypto/caam/ctrl.c | 5 +++-- 1 file changed, 3

Re: [PATCH v2 00/10] crypto: x86_64 - Add SSE/AVX2 ChaCha20/Poly1305 ciphers

On Thu, Jul 16, 2015 at 07:13:58PM +0200, Martin Willi wrote: This patch series adds both ChaCha20 and Poly1305 specific ciphers for x86_64 using SSE2/SSSE3 and AVX2 instructions. The idea is to have a drop-in replacement for AESNI/CLMUL-accelerated AES-GCM providing at least somewhat

Re: [PATCH v3 0/4] crypto: qat - add RSA support to qat driver

On Wed, Jul 15, 2015 at 03:28:21PM -0700, Tadeusz Struk wrote: This series adds RSA support to the qat driver. First patch adds the logic in FW loader to load the Modular Math Processor(MMP) firmware to the device's internal memory. Second patch adds logic to load MMP firmware from disk.