Re: [PATCH v2 0/5] crypto:chelsio: Bug fixes and cleanup

On Tue, Mar 6, 2018 at 11:22 AM, Herbert Xu wrote: > On Tue, Mar 06, 2018 at 10:37:47AM +0530, Harsh Jain wrote: >> It includes bug fixes and code cleanup. >> >> Changes from v1: >> >> Remove Redundant soffset initialisation from 2/5. > > Hmm, the first series has

Re: [RESEND PATCH v3] crypto: add zBeWalgo compression for zram

Hello, On (03/06/18 20:59), Benjamin Warnke wrote: >Currently ZRAM uses compression-algorithms from the crypto-api. ZRAM >compresses each page individually. As a result the compression algorithm >is >forced to use a very small sliding window. None of the available >compression

[PATCH] crypto: virtio - remove dependency on CRYPTO_AUTHENC

virtio_crypto does not use function crypto_authenc_extractkeys, remove this unnecessary dependency. Compiles fine and passes cryptodev-linux cipher and speed tests from https://wiki.qemu.org/Features/VirtioCrypto Fixes: dbaf0624ffa5 ("crypto: add virtio-crypto driver") Signed-off-by: Peter Wu

Re: [PATCH v3 3/4] crypto: jz4780-rng: Add RNG node to jz4780.dtsi

Le 2018-03-06 10:32, James Hogan a écrit : On Mon, Sep 18, 2017 at 07:32:40PM +0530, PrasannaKumar Muralidharan wrote: Add RNG node to jz4780 dtsi. This driver uses registers that are part of the register set used by Ingenic CGU driver. Use regmap in RNG driver to access its register. Create

Re: [RESEND PATCH v3] crypto: add zBeWalgo compression for zram

Hi Benjamin, On Tue, Mar 06, 2018 at 09:23:08PM +0100, Benjamin Warnke wrote: > Currently ZRAM uses compression-algorithms from the crypto-api. ZRAM > compresses each page individually. As a result the compression algorithm is > forced to use a very small sliding window. None of the available

[RESEND PATCH v3] crypto: add zBeWalgo compression for zram

Currently ZRAM uses compression-algorithms from the crypto-api. ZRAM compresses each page individually. As a result the compression algorithm is forced to use a very small sliding window. None of the available compression algorithms is designed to achieve high compression ratios with small inputs.

[PATCH] X.509: unpack RSA signatureValue field from BIT STRING

The signatureValue field of a X.509 certificate is encoded as a BIT STRING. For RSA signatures this BIT STRING is of so-called primitive subtype, which contains a u8 prefix indicating a count of unused bits in the encoding. We have to strip this prefix from signature data, just as we already do

Re: [PATCH] crypto: hash.h: Prevent use of req->digest in ahash update

On 3/6/2018 5:45 AM, Kamil Konieczny wrote: > Prevent improper use of req->digest field in ahash update, init, export and Shouldn't that be req->result (here and below)? Thanks, Tom > import functions in drivers code. A driver should use ahash request context > if it needs to save internal

Re: [PATCH v11 7/7] ntb: ntb_hw_switchtec: Cleanup 64bit IO defines to use the common header

On 06/03/18 04:57 AM, Andy Shevchenko wrote: On Tue, Mar 6, 2018 at 1:46 PM, Greg Kroah-Hartman wrote: On Tue, Mar 06, 2018 at 12:48:29PM +0200, Andy Shevchenko wrote: On Mon, Mar 5, 2018 at 9:08 PM, Logan Gunthorpe wrote: Clean up the

Re: [PATCH v11 6/7] crypto: caam: cleanup CONFIG_64BIT ifdefs when using io{read|write}64

On 06/03/18 05:37 AM, Horia Geantă wrote: On 3/5/2018 9:08 PM, Logan Gunthorpe wrote: Clean up the extra ifdefs which defined the wr_reg64 and rd_reg64 functions in non-64bit cases in favour of the new common io-64-nonatomic-lo-hi header. To be consistent with CAAM engine HW spec: in case of

RE: [PATCH v9 crypto 00/12] Chelsio Inline TLS

-Original Message- From: Vakul Garg [mailto:vakul.g...@nxp.com] Sent: Tuesday, March 6, 2018 9:09 PM To: Atul Gupta ; davejwat...@fb.com; da...@davemloft.net; herb...@gondor.apana.org.au Cc: linux-crypto@vger.kernel.org; net...@vger.kernel.org; Ganesh GR

[PATCH v9 crypto 05/12] cxgb4: Inline TLS FW Interface

Key area size in hw-config file. CPL struct for TLS request and response. Work request for Inline TLS. Signed-off-by: Atul Gupta --- drivers/net/ethernet/chelsio/cxgb4/t4_msg.h | 121 ++- drivers/net/ethernet/chelsio/cxgb4/t4_regs.h | 2 +

[PATCH v9 crypto 06/12] cxgb4: LLD driver changes to enable TLS

Read FW capability. Read key area size. Dump the TLS record count. Signed-off-by: Atul Gupta --- drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 32 +--- drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h | 7 ++ drivers/net/ethernet/chelsio/cxgb4/sge.c| 98

[PATCH v9 crypto 12/12] Makefile Kconfig

Entry for Inline TLS as another driver dependent on cxgb4 and chcr Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/Kconfig| 11 +++ drivers/crypto/chelsio/Makefile | 1 + drivers/crypto/chelsio/chtls/Makefile | 4 3 files changed, 16

[PATCH v9 crypto 08/12] chtls: Key program

Program the tx and rx key on chip. Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/chtls/chtls_hw.c | 394 1 file changed, 394 insertions(+) create mode 100644 drivers/crypto/chelsio/chtls/chtls_hw.c diff --git

[PATCH v9 crypto 11/12] chtls: Register chtls Inline TLS with net tls

Register chtls as Inline TLS driver, chtls is ULD to cxgb4. Setsockopt to program (tx/rx) keys on chip. Support AES GCM of key size 128. Support both Inline Rx and Tx. Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/chtls/chtls_main.c | 600

[PATCH v9 crypto 09/12] chtls: CPL handler definition

CPL handlers for TLS session, record transmit and receive. Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/chtls/chtls_cm.c | 2041 +++ net/ipv4/tcp_minisocks.c|1 + 2 files changed, 2042 insertions(+) create mode

[PATCH v9 crypto 10/12] chtls: Inline crypto request Tx/Rx

TLS handler for record transmit and receive. Create Inline TLS work request and post to FW. Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/chtls/chtls_io.c | 1867 +++ 1 file changed, 1867 insertions(+) create mode 100644

[PATCH v9 crypto 07/12] chcr: Key Macro

Define macro for TLS Key context Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/chcr_algo.h | 42 + drivers/crypto/chelsio/chcr_core.h | 55 +- 2 files changed, 96 insertions(+), 1 deletion(-) diff

[PATCH v9 crypto 04/12] chtls: structure and macro definiton

Inline TLS state, connection management. Supporting macros definition. Signed-off-by: Atul Gupta --- drivers/crypto/chelsio/chtls/chtls.h| 487 drivers/crypto/chelsio/chtls/chtls_cm.h | 202 + 2 files changed, 689

RE: [PATCH v9 crypto 00/12] Chelsio Inline TLS

> -Original Message- > From: linux-crypto-ow...@vger.kernel.org [mailto:linux-crypto- > ow...@vger.kernel.org] On Behalf Of Atul Gupta > Sent: Tuesday, March 6, 2018 9:05 PM > To: davejwat...@fb.com; da...@davemloft.net; > herb...@gondor.apana.org.au > Cc: linux-crypto@vger.kernel.org;

[PATCH v9 crypto 02/12] ethtool: enable Inline TLS in HW

Signed-off-by: Atul Gupta --- include/linux/netdev_features.h | 2 ++ net/core/ethtool.c | 1 + 2 files changed, 3 insertions(+) diff --git a/include/linux/netdev_features.h b/include/linux/netdev_features.h index db84c51..aacabe2 100644 ---

[PATCH v9 crypto 03/12] tls: support for inline tls

Facility to register Inline TLS drivers to net/tls. Setup TLS_FULL_HW prot to listen on offload device. Cases handled 1. Inline TLS device exists, setup prot for TLS_FULL_HW 2. Atleast one Inline TLS exists, sets TLS_FULL_HW. If non-inline capable device establish connection move to TLS_SW_TX

[PATCH v9 crypto 01/12] tls: tls_device struct to register TLS drivers

tls_device structure to register Inline TLS drivers with net/tls Signed-off-by: Atul Gupta --- include/net/tls.h | 26 ++ 1 file changed, 26 insertions(+) diff --git a/include/net/tls.h b/include/net/tls.h index 4913430..9bfb91f 100644 ---

Re: [PATCH v3 3/4] crypto: jz4780-rng: Add RNG node to jz4780.dtsi

On Tue, Mar 6, 2018 at 3:32 AM, James Hogan wrote: > On Mon, Sep 18, 2017 at 07:32:40PM +0530, PrasannaKumar Muralidharan wrote: >> Add RNG node to jz4780 dtsi. This driver uses registers that are part of >> the register set used by Ingenic CGU driver. Use regmap in RNG driver

Re: [RFC PATCH] crypto: arm64/speck - add NEON-accelerated implementation of Speck-XTS

On Tue, Mar 06, 2018 at 12:47:45PM +, Ard Biesheuvel wrote: > On 6 March 2018 at 12:35, Dave Martin wrote: > > On Mon, Mar 05, 2018 at 11:17:07AM -0800, Eric Biggers wrote: > >> Add a NEON-accelerated implementation of Speck128-XTS and Speck64-XTS > >> for ARM64. This is

Re: [RFC PATCH] crypto: arm64/speck - add NEON-accelerated implementation of Speck-XTS

On 6 March 2018 at 12:35, Dave Martin wrote: > On Mon, Mar 05, 2018 at 11:17:07AM -0800, Eric Biggers wrote: >> Add a NEON-accelerated implementation of Speck128-XTS and Speck64-XTS >> for ARM64. This is ported from the 32-bit version. It may be useful on >> devices with

Re: [PATCH v11 6/7] crypto: caam: cleanup CONFIG_64BIT ifdefs when using io{read|write}64

On 3/5/2018 9:08 PM, Logan Gunthorpe wrote: > Clean up the extra ifdefs which defined the wr_reg64 and rd_reg64 > functions in non-64bit cases in favour of the new common > io-64-nonatomic-lo-hi header. > > To be consistent with CAAM engine HW spec: in case of 64-bit registers, > irrespective of

Re: [RFC PATCH] crypto: arm64/speck - add NEON-accelerated implementation of Speck-XTS

On Mon, Mar 05, 2018 at 11:17:07AM -0800, Eric Biggers wrote: > Add a NEON-accelerated implementation of Speck128-XTS and Speck64-XTS > for ARM64. This is ported from the 32-bit version. It may be useful on > devices with 64-bit ARM CPUs that don't have the Cryptography > Extensions, so cannot

Re: [PATCH v11 7/7] ntb: ntb_hw_switchtec: Cleanup 64bit IO defines to use the common header

On Tue, Mar 6, 2018 at 1:46 PM, Greg Kroah-Hartman wrote: > On Tue, Mar 06, 2018 at 12:48:29PM +0200, Andy Shevchenko wrote: >> On Mon, Mar 5, 2018 at 9:08 PM, Logan Gunthorpe wrote: >> > Clean up the ifdefs which conditionally defined the

Re: [PATCH v11 7/7] ntb: ntb_hw_switchtec: Cleanup 64bit IO defines to use the common header

On Tue, Mar 06, 2018 at 12:48:29PM +0200, Andy Shevchenko wrote: > On Mon, Mar 5, 2018 at 9:08 PM, Logan Gunthorpe wrote: > > Clean up the ifdefs which conditionally defined the io{read|write}64 > > functions in favour of the new common io-64-nonatomic-lo-hi header. > > >

[PATCH] crypto: hash.h: Prevent use of req->digest in ahash update

Prevent improper use of req->digest field in ahash update, init, export and import functions in drivers code. A driver should use ahash request context if it needs to save internal state. Signed-off-by: Kamil Konieczny --- include/crypto/hash.h | 11 +++

Re: [PATCH v11 7/7] ntb: ntb_hw_switchtec: Cleanup 64bit IO defines to use the common header

On Mon, Mar 5, 2018 at 9:08 PM, Logan Gunthorpe wrote: > Clean up the ifdefs which conditionally defined the io{read|write}64 > functions in favour of the new common io-64-nonatomic-lo-hi header. > #include > #include > #include > +#include A nit, can we preserve

[PATCH 1/2] crypto: introduce SM4 symmetric cipher algorithm

Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016). SM4 (GBT.32907-2016) is a cryptographic standard issued by the Organization of State Commercial Administration of China (OSCCA) as an authorized cryptographic algorithms for the use within China. SMS4 was originally created for use in

[PATCH 2/2] crypto: introduce SM4 testmgr tests

Add testmgr tests for the newly introduced SM4 ECB symmetric cipher. Signed-off-by: Gilad Ben-Yossef --- crypto/tcrypt.c | 3 ++ crypto/testmgr.c | 9 crypto/testmgr.h | 131 +++ 3 files changed, 143

[PATCH 0/2] crypto: introduce SM4 symmetric cipher algorithm

Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016) and related tests. SM4 (GBT.32907-2016) is a cryptographic standard issued by the Organization of State Commercial Administration of China (OSCCA) as an authorized cryptographic algorithms for the use within China. SMS4 was originally

Re: [PATCH v3 3/4] crypto: jz4780-rng: Add RNG node to jz4780.dtsi

On Mon, Sep 18, 2017 at 07:32:40PM +0530, PrasannaKumar Muralidharan wrote: > Add RNG node to jz4780 dtsi. This driver uses registers that are part of > the register set used by Ingenic CGU driver. Use regmap in RNG driver to > access its register. Create 'simple-bus' node, make CGU and RNG node