Re: [PATCH v2 2/6] crypto: engine - Permit to enqueue all async requests

[Fabien DESSENNE]

Adding my tested-by for the AEAD part which is new in v2


On 26/01/18 20:15, Corentin Labbe wrote:
> The crypto engine could actually only enqueue hash and ablkcipher request.
> This patch permit it to enqueue any type of crypto_async_request.
>
> Signed-off-by: Corentin Labbe <clabbe.montj...@gmail.com>
> Tested-by: Fabien Dessenne <fabien.desse...@st.com>

Tested-by: Fabien Dessenne <fabien.desse...@st.com>


> ---
>   crypto/crypto_engine.c  | 301 
> ++--
>   include/crypto/engine.h |  68 ++-
>   2 files changed, 203 insertions(+), 166 deletions(-)
>
> diff --git a/crypto/crypto_engine.c b/crypto/crypto_engine.c
> index 61e7c4e02fd2..992e8d8dcdd9 100644
> --- a/crypto/crypto_engine.c
> +++ b/crypto/crypto_engine.c
> @@ -15,13 +15,50 @@
>   #include 
>   #include 
>   #include 
> -#include 
>   #include 
>   #include "internal.h"
>   
>   #define CRYPTO_ENGINE_MAX_QLEN 10
>   
>   /**
> + * crypto_finalize_request - finalize one request if the request is done
> + * @engine: the hardware engine
> + * @req: the request need to be finalized
> + * @err: error number
> + */
> +static void crypto_finalize_request(struct crypto_engine *engine,
> +  struct crypto_async_request *req, int err)
> +{
> + unsigned long flags;
> + bool finalize_cur_req = false;
> + int ret;
> + struct crypto_engine_ctx *enginectx;
> +
> + spin_lock_irqsave(>queue_lock, flags);
> + if (engine->cur_req == req)
> + finalize_cur_req = true;
> + spin_unlock_irqrestore(>queue_lock, flags);
> +
> + if (finalize_cur_req) {
> + enginectx = crypto_tfm_ctx(req->tfm);
> + if (engine->cur_req_prepared &&
> + enginectx->op.unprepare_request) {
> + ret = enginectx->op.unprepare_request(engine, req);
> + if (ret)
> + dev_err(engine->dev, "failed to unprepare 
> request\n");
> + }
> + spin_lock_irqsave(>queue_lock, flags);
> + engine->cur_req = NULL;
> + engine->cur_req_prepared = false;
> + spin_unlock_irqrestore(>queue_lock, flags);
> + }
> +
> + req->complete(req, err);
> +
> + kthread_queue_work(engine->kworker, >pump_requests);
> +}
> +
> +/**
>* crypto_pump_requests - dequeue one request from engine queue to process
>* @engine: the hardware engine
>* @in_kthread: true if we are in the context of the request pump thread
> @@ -34,11 +71,10 @@ static void crypto_pump_requests(struct crypto_engine 
> *engine,
>bool in_kthread)
>   {
>   struct crypto_async_request *async_req, *backlog;
> - struct ahash_request *hreq;
> - struct ablkcipher_request *breq;
>   unsigned long flags;
>   bool was_busy = false;
> - int ret, rtype;
> + int ret;
> + struct crypto_engine_ctx *enginectx;
>   
>   spin_lock_irqsave(>queue_lock, flags);
>   
> @@ -94,7 +130,6 @@ static void crypto_pump_requests(struct crypto_engine 
> *engine,
>   
>   spin_unlock_irqrestore(>queue_lock, flags);
>   
> - rtype = crypto_tfm_alg_type(engine->cur_req->tfm);
>   /* Until here we get the request need to be encrypted successfully */
>   if (!was_busy && engine->prepare_crypt_hardware) {
>   ret = engine->prepare_crypt_hardware(engine);
> @@ -104,57 +139,31 @@ static void crypto_pump_requests(struct crypto_engine 
> *engine,
>   }
>   }
>   
> - switch (rtype) {
> - case CRYPTO_ALG_TYPE_AHASH:
> - hreq = ahash_request_cast(engine->cur_req);
> - if (engine->prepare_hash_request) {
> - ret = engine->prepare_hash_request(engine, hreq);
> - if (ret) {
> - dev_err(engine->dev, "failed to prepare 
> request: %d\n",
> - ret);
> - goto req_err;
> - }
> - engine->cur_req_prepared = true;
> - }
> - ret = engine->hash_one_request(engine, hreq);
> - if (ret) {
> - dev_err(engine->dev, "failed to hash one request from 
> queue\n");
> - goto req_err;
> - }
> - return;
> - case CRYPTO_ALG_TYPE_ABLKCIPHER:
> - breq = ablkcipher_request_cast(engine->cu

[PATCH 0/2] crypto: stm32/cryp - add AEAD cipher algorithms

[Fabien Dessenne]

This patchset depends on "crypto: engine - Permit to enqueue all async requests"
proposed by Corentin Labbe [https://lkml.org/lkml/2018/1/26/608].
stm32-cryp uses this updated crpyto engine to handle AEAD cipher algortihms.

Fabien Dessenne (2):
  crypto: stm32/cryp - add aes gcm / ccm support
  crypto: stm32/cryp - add stm32mp1 support

 drivers/crypto/stm32/stm32-cryp.c | 937 --
 1 file changed, 908 insertions(+), 29 deletions(-)

-- 
2.7.4

[PATCH 1/2] crypto: stm32/cryp - add aes gcm / ccm support

[Fabien Dessenne]

Add AEAD cipher algorithms for aes gcm and ccm.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 drivers/crypto/stm32/stm32-cryp.c | 931 --
 1 file changed, 902 insertions(+), 29 deletions(-)

diff --git a/drivers/crypto/stm32/stm32-cryp.c 
b/drivers/crypto/stm32/stm32-cryp.c
index 0f0e2ba..6a1fe98 100644
--- a/drivers/crypto/stm32/stm32-cryp.c
+++ b/drivers/crypto/stm32/stm32-cryp.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define DRIVER_NAME "stm32-cryp"
 
@@ -29,8 +30,12 @@
 #define FLG_ECB BIT(4)
 #define FLG_CBC BIT(5)
 #define FLG_CTR BIT(6)
+#define FLG_GCM BIT(7)
+#define FLG_CCM BIT(8)
 /* Mode mask = bits [15..0] */
 #define FLG_MODE_MASK   GENMASK(15, 0)
+/* Bit [31..16] status  */
+#define FLG_CCM_PADDED_WA   BIT(16)
 
 /* Registers */
 #define CRYP_CR 0x
@@ -53,6 +58,8 @@
 #define CRYP_IV0RR  0x0044
 #define CRYP_IV1LR  0x0048
 #define CRYP_IV1RR  0x004C
+#define CRYP_CSGCMCCM0R 0x0050
+#define CRYP_CSGCM0R0x0070
 
 /* Registers values */
 #define CR_DEC_NOT_ENC  0x0004
@@ -64,6 +71,8 @@
 #define CR_AES_CBC  0x0028
 #define CR_AES_CTR  0x0030
 #define CR_AES_KP   0x0038
+#define CR_AES_GCM  0x0008
+#define CR_AES_CCM  0x00080008
 #define CR_AES_UNKNOWN  0x
 #define CR_ALGO_MASK0x00080038
 #define CR_DATA32   0x
@@ -75,6 +84,12 @@
 #define CR_KEY256   0x0200
 #define CR_FFLUSH   0x4000
 #define CR_CRYPEN   0x8000
+#define CR_PH_INIT  0x
+#define CR_PH_HEADER0x0001
+#define CR_PH_PAYLOAD   0x0002
+#define CR_PH_FINAL 0x0003
+#define CR_PH_MASK  0x0003
+#define CR_NBPBL_SHIFT  20
 
 #define SR_BUSY 0x0010
 #define SR_OFNE 0x0004
@@ -87,9 +102,15 @@
 
 /* Misc */
 #define AES_BLOCK_32(AES_BLOCK_SIZE / sizeof(u32))
+#define GCM_CTR_INIT2
 #define _walked_in  (cryp->in_walk.offset - cryp->in_sg->offset)
 #define _walked_out (cryp->out_walk.offset - cryp->out_sg->offset)
 
+struct stm32_cryp_caps {
+   boolswap_final;
+   boolpadding_wa;
+};
+
 struct stm32_cryp_ctx {
struct crypto_engine_ctx enginectx;
struct stm32_cryp   *cryp;
@@ -109,13 +130,16 @@ struct stm32_cryp {
struct clk  *clk;
unsigned long   flags;
u32 irq_status;
+   const struct stm32_cryp_caps *caps;
struct stm32_cryp_ctx   *ctx;
 
struct crypto_engine*engine;
 
-   struct mutexlock; /* protects req */
+   struct mutexlock; /* protects req / areq */
struct ablkcipher_request *req;
+   struct aead_request *areq;
 
+   size_t  authsize;
size_t  hw_blocksize;
 
size_t  total_in;
@@ -138,6 +162,7 @@ struct stm32_cryp {
struct scatter_walk out_walk;
 
u32 last_ctr[4];
+   u32 gcm_ctr;
 };
 
 struct stm32_cryp_list {
@@ -180,6 +205,16 @@ static inline bool is_ctr(struct stm32_cryp *cryp)
return cryp->flags & FLG_CTR;
 }
 
+static inline bool is_gcm(struct stm32_cryp *cryp)
+{
+   return cryp->flags & FLG_GCM;
+}
+
+static inline bool is_ccm(struct stm32_cryp *cryp)
+{
+   return cryp->flags & FLG_CCM;
+}
+
 static inline bool is_encrypt(struct stm32_cryp *cryp)
 {
return cryp->flags & FLG_ENCRYPT;
@@ -208,6 +243,24 @@ static inline int stm32_cryp_wait_busy(struct stm32_cryp 
*cryp)
!(status & SR_BUSY), 10, 10);
 }
 
+static inline int stm32_cryp_wait_enable(struct stm32_cryp *cryp)
+{
+   u32 status;
+
+   return readl_relaxed_poll_timeout(cryp->regs + CRYP_CR, status,
+   !(status & CR_CRYPEN), 10, 10);
+}
+
+static inline int stm32_cryp_wait_output(struct stm32_cryp *cryp)
+{
+   u32 status;
+
+   return readl_relaxed_poll_timeout(cryp->regs + CRYP_SR, status,
+   status & SR_OFNE, 10, 10);
+}
+
+static int stm32_cryp_read_auth_tag(struct stm32_cryp *cryp);
+
 static struct stm32_cryp *stm32_cryp_find_dev(struct stm32_cryp_ctx *ctx)
 {
struct stm32_cryp *tmp, *cryp = NULL;
@@ -366,6 +419,12 @@ static u32 stm32_cryp_get_hw_mode(struct stm32_cryp *cryp)
if (is_aes(cryp) && is_ctr(cryp))
return CR_AES_CTR;
 
+   if (is_aes(cryp) &

[PATCH 2/2] crypto: stm32/cryp - add stm32mp1 support

[Fabien Dessenne]

stm32mp1 differs from stm32f7 in the way it handles byte ordering and
padding for aes gcm & ccm algo.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 drivers/crypto/stm32/stm32-cryp.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/crypto/stm32/stm32-cryp.c 
b/drivers/crypto/stm32/stm32-cryp.c
index 6a1fe98..c5d3efc 100644
--- a/drivers/crypto/stm32/stm32-cryp.c
+++ b/drivers/crypto/stm32/stm32-cryp.c
@@ -1906,8 +1906,14 @@ static const struct stm32_cryp_caps f7_data = {
.padding_wa = true,
 };
 
+static const struct stm32_cryp_caps mp1_data = {
+   .swap_final = false,
+   .padding_wa = false,
+};
+
 static const struct of_device_id stm32_dt_ids[] = {
{ .compatible = "st,stm32f756-cryp", .data = _data},
+   { .compatible = "st,stm32mp1-cryp", .data = _data},
{},
 };
 MODULE_DEVICE_TABLE(of, stm32_dt_ids);
-- 
2.7.4

Re: [PATCH -next] crypto: stm32 - remove redundant dev_err call in stm32_cryp_probe()

[Fabien DESSENNE]

Hi,


Thank you for the patch.


On 17/01/18 12:40, Wei Yongjun wrote:
> There is a error message within devm_ioremap_resource
> already, so remove the dev_err call to avoid redundant
> error message.
>
> Signed-off-by: Wei Yongjun <weiyongj...@huawei.com>
Reviewed-by: Fabien Dessenne <fabien.desse...@st.com>
> ---
>   drivers/crypto/stm32/stm32-cryp.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/crypto/stm32/stm32-cryp.c 
> b/drivers/crypto/stm32/stm32-cryp.c
> index cf1dddb..4a06a7a 100644
> --- a/drivers/crypto/stm32/stm32-cryp.c
> +++ b/drivers/crypto/stm32/stm32-cryp.c
> @@ -1052,10 +1052,8 @@ static int stm32_cryp_probe(struct platform_device 
> *pdev)
>   
>   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>   cryp->regs = devm_ioremap_resource(dev, res);
> - if (IS_ERR(cryp->regs)) {
> - dev_err(dev, "Cannot map CRYP IO\n");
> + if (IS_ERR(cryp->regs))
>   return PTR_ERR(cryp->regs);
> - }
>   
>   irq = platform_get_irq(pdev, 0);
>   if (irq < 0) {
>

Re: [PATCH 6/6] crypto: stm32-cryp: convert to the new crypto engine API

[Fabien DESSENNE]

(Adding my tested by)


On 10/01/18 15:25, Fabien DESSENNE wrote:
>
> On 03/01/18 21:11, Corentin Labbe wrote:
>> This patch convert the stm32-cryp driver to the new crypto engine API.
>> Signed-off-by: Corentin Labbe <clabbe.montj...@gmail.com>

Tested-by: Fabien Dessenne <fabien.desse...@st.com>

>> ---
>>drivers/crypto/stm32/stm32-cryp.c | 21 -
>>1 file changed, 16 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/crypto/stm32/stm32-cryp.c 
>> b/drivers/crypto/stm32/stm32-cryp.c
>> index cf1dddbeaa2c..99e0473ef247 100644
>> --- a/drivers/crypto/stm32/stm32-cryp.c
>> +++ b/drivers/crypto/stm32/stm32-cryp.c
>> @@ -91,6 +91,7 @@
>>#define _walked_out (cryp->out_walk.offset - 
>> cryp->out_sg->offset)
>>
>>struct stm32_cryp_ctx {
>> +struct crypto_engine_reqctx enginectx;
>>  struct stm32_cryp   *cryp;
>>  int keylen;
>>  u32 key[AES_KEYSIZE_256 / sizeof(u32)];
>> @@ -494,10 +495,20 @@ static int stm32_cryp_cpu_start(struct stm32_cryp 
>> *cryp)
>>  return 0;
>>}
>>
>> +static int stm32_cryp_cipher_one_req(struct crypto_engine *engine,
>> + void *areq);
> Merge these 2 lines in a single one
>
>> +static int stm32_cryp_prepare_cipher_req(struct crypto_engine *engine,
>> + void *areq);
>> +
>>static int stm32_cryp_cra_init(struct crypto_tfm *tfm)
>>{
>> +struct stm32_cryp_ctx *ctx = crypto_tfm_ctx(tfm);
>> +
>>  tfm->crt_ablkcipher.reqsize = sizeof(struct stm32_cryp_reqctx);
>>
>> +ctx->enginectx.op.do_one_request = stm32_cryp_cipher_one_req;
>> +ctx->enginectx.op.prepare_request = stm32_cryp_prepare_cipher_req;
>> +ctx->enginectx.op.unprepare_request = NULL;
>>  return 0;
>>}
>>
>> @@ -695,14 +706,17 @@ static int stm32_cryp_prepare_req(struct crypto_engine 
>> *engine,
>>}
>>
>>static int stm32_cryp_prepare_cipher_req(struct crypto_engine *engine,
>> - struct ablkcipher_request *req)
>> + void *areq)
>>{
>> +struct ablkcipher_request *req = container_of(areq, struct 
>> ablkcipher_request, base);
>   > 80 characters (CHECKPATCH)
>
>> +
>>  return stm32_cryp_prepare_req(engine, req);
>>}
>>
>>static int stm32_cryp_cipher_one_req(struct crypto_engine *engine,
>> - struct ablkcipher_request *req)
>> + void *areq)
> Merge these 2 lines in a single one
>
>>{
>> +struct ablkcipher_request *req = container_of(areq, struct 
>> ablkcipher_request, base);
>   > 80 characters (CHECKPATCH)
>
>>  struct stm32_cryp_ctx *ctx = crypto_ablkcipher_ctx(
>>  crypto_ablkcipher_reqtfm(req));
>>  struct stm32_cryp *cryp = ctx->cryp;
>> @@ -1104,9 +1118,6 @@ static int stm32_cryp_probe(struct platform_device 
>> *pdev)
>>  goto err_engine1;
>>  }
>>
>> -cryp->engine->prepare_cipher_request = stm32_cryp_prepare_cipher_req;
>> -cryp->engine->cipher_one_request = stm32_cryp_cipher_one_req;
>> -
>>  ret = crypto_engine_start(cryp->engine);
>>  if (ret) {
>>  dev_err(dev, "Could not start crypto engine\n");

Re: [PATCH 2/6] crypto: engine - Permit to enqueue all async requests

[Fabien DESSENNE]

(adding my tested by)


On 10/01/18 15:19, Fabien DESSENNE wrote:
> On 03/01/18 21:11, Corentin Labbe wrote:
>> The crypto engine could actually only enqueue hash and ablkcipher request.
>> This patch permit it to enqueue any type of crypto_async_request.
>>
>> Signed-off-by: Corentin Labbe <clabbe.montj...@gmail.com>

Tested-by: Fabien Dessenne <fabien.desse...@st.com>

>> ---
>>crypto/crypto_engine.c  | 230 
>> 
>>include/crypto/engine.h |  59 +++--
>>2 files changed, 148 insertions(+), 141 deletions(-)
>>
>> diff --git a/crypto/crypto_engine.c b/crypto/crypto_engine.c
>> index 61e7c4e02fd2..036270b61648 100644
>> --- a/crypto/crypto_engine.c
>> +++ b/crypto/crypto_engine.c
>> @@ -15,7 +15,6 @@
>>#include 
>>#include 
>>#include 
>> -#include 
>>#include 
>>#include "internal.h"
>>
>> @@ -34,11 +33,10 @@ static void crypto_pump_requests(struct crypto_engine 
>> *engine,
>>   bool in_kthread)
>>{
>>  struct crypto_async_request *async_req, *backlog;
>> -struct ahash_request *hreq;
>> -struct ablkcipher_request *breq;
>>  unsigned long flags;
>>  bool was_busy = false;
>> -int ret, rtype;
>> +int ret;
>> +struct crypto_engine_reqctx *enginectx;
>>
>>  spin_lock_irqsave(>queue_lock, flags);
>>
>> @@ -94,7 +92,6 @@ static void crypto_pump_requests(struct crypto_engine 
>> *engine,
>>
>>  spin_unlock_irqrestore(>queue_lock, flags);
>>
>> -rtype = crypto_tfm_alg_type(engine->cur_req->tfm);
>>  /* Until here we get the request need to be encrypted successfully */
>>  if (!was_busy && engine->prepare_crypt_hardware) {
>>  ret = engine->prepare_crypt_hardware(engine);
>> @@ -104,57 +101,31 @@ static void crypto_pump_requests(struct crypto_engine 
>> *engine,
>>  }
>>  }
>>
>> -switch (rtype) {
>> -case CRYPTO_ALG_TYPE_AHASH:
>> -hreq = ahash_request_cast(engine->cur_req);
>> -if (engine->prepare_hash_request) {
>> -ret = engine->prepare_hash_request(engine, hreq);
>> -if (ret) {
>> -dev_err(engine->dev, "failed to prepare 
>> request: %d\n",
>> -ret);
>> -goto req_err;
>> -}
>> -engine->cur_req_prepared = true;
>> -}
>> -ret = engine->hash_one_request(engine, hreq);
>> -if (ret) {
>> -dev_err(engine->dev, "failed to hash one request from 
>> queue\n");
>> -goto req_err;
>> -}
>> -return;
>> -case CRYPTO_ALG_TYPE_ABLKCIPHER:
>> -breq = ablkcipher_request_cast(engine->cur_req);
>> -if (engine->prepare_cipher_request) {
>> -ret = engine->prepare_cipher_request(engine, breq);
>> -if (ret) {
>> -dev_err(engine->dev, "failed to prepare 
>> request: %d\n",
>> -ret);
>> -goto req_err;
>> -}
>> -engine->cur_req_prepared = true;
>> -}
>> -ret = engine->cipher_one_request(engine, breq);
>> +enginectx = crypto_tfm_ctx(async_req->tfm);
>> +
>> +if (enginectx->op.prepare_request) {
>> +ret = enginectx->op.prepare_request(engine, async_req);
>>  if (ret) {
>> -dev_err(engine->dev, "failed to cipher one request from 
>> queue\n");
>> +dev_err(engine->dev, "failed to prepare request: %d\n",
>> +ret);
>>  goto req_err;
>>  }
>> -return;
>> -default:
>> -dev_err(engine->dev, "failed to prepare request of unknown 
>> type\n");
>> -return;
>> +engine->cur_req_prepared = true;
>> +}
>> +if (!enginectx->op.do_one_request) {
>> +dev_err(engine->dev, "failed to do request\n");
>> +  

Re: [PATCH 5/6] crypto: stm32-hash: convert to the new crypto engine API

[Fabien DESSENNE]

(adding my tested my)


On 10/01/18 15:24, Fabien DESSENNE wrote:
>
> On 03/01/18 21:11, Corentin Labbe wrote:
>> This patch convert the stm32-hash driver to the new crypto engine API.
>>
>> Signed-off-by: Corentin Labbe <clabbe.montj...@gmail.com>

Tested-by: Fabien Dessenne <fabien.desse...@st.com>

>> ---
>>drivers/crypto/stm32/stm32-hash.c | 18 +-
>>1 file changed, 13 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/crypto/stm32/stm32-hash.c 
>> b/drivers/crypto/stm32/stm32-hash.c
>> index 4ca4a264a833..9790c2c936c7 100644
>> --- a/drivers/crypto/stm32/stm32-hash.c
>> +++ b/drivers/crypto/stm32/stm32-hash.c
>> @@ -122,6 +122,7 @@ enum stm32_hash_data_format {
>>#define HASH_DMA_THRESHOLD50
>>
>>struct stm32_hash_ctx {
>> +struct crypto_engine_reqctx enginectx;
>>  struct stm32_hash_dev   *hdev;
>>  unsigned long   flags;
>>
>> @@ -828,6 +829,11 @@ static int stm32_hash_hw_init(struct stm32_hash_dev 
>> *hdev,
>>  return 0;
>>}
>>
>> +static int stm32_hash_one_request(struct crypto_engine *engine,
>> +  void *areq);
> merge these two lines in a single one
>
>> +static int stm32_hash_prepare_req(struct crypto_engine *engine,
>> +  void *areq);
> merge these two lines in a single one
>
>> +
>>static int stm32_hash_handle_queue(struct stm32_hash_dev *hdev,
>> struct ahash_request *req)
>>{
>> @@ -835,8 +841,9 @@ static int stm32_hash_handle_queue(struct stm32_hash_dev 
>> *hdev,
>>}
>>
>>static int stm32_hash_prepare_req(struct crypto_engine *engine,
>> -  struct ahash_request *req)
>> +  void *areq)
> merge these two lines in a single one
>
>>{
>> +struct ahash_request *req = container_of(areq, struct ahash_request, 
>> base);
>   > 80 characters (CHECKPATCH)
>
>>  struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
>>  struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
>>  struct stm32_hash_request_ctx *rctx;
>> @@ -855,8 +862,9 @@ static int stm32_hash_prepare_req(struct crypto_engine 
>> *engine,
>>}
>>
>>static int stm32_hash_one_request(struct crypto_engine *engine,
>> -  struct ahash_request *req)
>> +  void *areq)
> merge these two lines in a single one
>
>>{
>> +struct ahash_request *req = container_of(areq, struct ahash_request, 
>> base);
>   > 80 characters (CHECKPATCH)
>
>>  struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
>>  struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
>>  struct stm32_hash_request_ctx *rctx;
>> @@ -1033,6 +1041,9 @@ static int stm32_hash_cra_init_algs(struct crypto_tfm 
>> *tfm,
>>  if (algs_hmac_name)
>>  ctx->flags |= HASH_FLAGS_HMAC;
>>
>> +ctx->enginectx.op.do_one_request = stm32_hash_one_request;
>> +ctx->enginectx.op.prepare_request = stm32_hash_prepare_req;
>> +ctx->enginectx.op.unprepare_request = NULL;
>>  return 0;
>>}
>>
>> @@ -1493,9 +1504,6 @@ static int stm32_hash_probe(struct platform_device 
>> *pdev)
>>  goto err_engine;
>>  }
>>
>> -hdev->engine->prepare_hash_request = stm32_hash_prepare_req;
>> -hdev->engine->hash_one_request = stm32_hash_one_request;
>> -
>>  ret = crypto_engine_start(hdev->engine);
>>  if (ret)
>>  goto err_engine_start;

Re: [PATCH 6/6] crypto: stm32-cryp: convert to the new crypto engine API

[Fabien DESSENNE]

On 03/01/18 21:11, Corentin Labbe wrote:
> This patch convert the stm32-cryp driver to the new crypto engine API.
> Signed-off-by: Corentin Labbe 
> ---
>   drivers/crypto/stm32/stm32-cryp.c | 21 -
>   1 file changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/crypto/stm32/stm32-cryp.c 
> b/drivers/crypto/stm32/stm32-cryp.c
> index cf1dddbeaa2c..99e0473ef247 100644
> --- a/drivers/crypto/stm32/stm32-cryp.c
> +++ b/drivers/crypto/stm32/stm32-cryp.c
> @@ -91,6 +91,7 @@
>   #define _walked_out (cryp->out_walk.offset - 
> cryp->out_sg->offset)
>   
>   struct stm32_cryp_ctx {
> + struct crypto_engine_reqctx enginectx;
>   struct stm32_cryp   *cryp;
>   int keylen;
>   u32 key[AES_KEYSIZE_256 / sizeof(u32)];
> @@ -494,10 +495,20 @@ static int stm32_cryp_cpu_start(struct stm32_cryp *cryp)
>   return 0;
>   }
>   
> +static int stm32_cryp_cipher_one_req(struct crypto_engine *engine,
> +  void *areq);

Merge these 2 lines in a single one

> +static int stm32_cryp_prepare_cipher_req(struct crypto_engine *engine,
> +  void *areq);
> +
>   static int stm32_cryp_cra_init(struct crypto_tfm *tfm)
>   {
> + struct stm32_cryp_ctx *ctx = crypto_tfm_ctx(tfm);
> +
>   tfm->crt_ablkcipher.reqsize = sizeof(struct stm32_cryp_reqctx);
>   
> + ctx->enginectx.op.do_one_request = stm32_cryp_cipher_one_req;
> + ctx->enginectx.op.prepare_request = stm32_cryp_prepare_cipher_req;
> + ctx->enginectx.op.unprepare_request = NULL;
>   return 0;
>   }
>   
> @@ -695,14 +706,17 @@ static int stm32_cryp_prepare_req(struct crypto_engine 
> *engine,
>   }
>   
>   static int stm32_cryp_prepare_cipher_req(struct crypto_engine *engine,
> -  struct ablkcipher_request *req)
> +  void *areq)
>   {
> + struct ablkcipher_request *req = container_of(areq, struct 
> ablkcipher_request, base);

 > 80 characters (CHECKPATCH)

> +
>   return stm32_cryp_prepare_req(engine, req);
>   }
>   
>   static int stm32_cryp_cipher_one_req(struct crypto_engine *engine,
> -  struct ablkcipher_request *req)
> +  void *areq)

Merge these 2 lines in a single one

>   {
> + struct ablkcipher_request *req = container_of(areq, struct 
> ablkcipher_request, base);

 > 80 characters (CHECKPATCH)

>   struct stm32_cryp_ctx *ctx = crypto_ablkcipher_ctx(
>   crypto_ablkcipher_reqtfm(req));
>   struct stm32_cryp *cryp = ctx->cryp;
> @@ -1104,9 +1118,6 @@ static int stm32_cryp_probe(struct platform_device 
> *pdev)
>   goto err_engine1;
>   }
>   
> - cryp->engine->prepare_cipher_request = stm32_cryp_prepare_cipher_req;
> - cryp->engine->cipher_one_request = stm32_cryp_cipher_one_req;
> -
>   ret = crypto_engine_start(cryp->engine);
>   if (ret) {
>   dev_err(dev, "Could not start crypto engine\n");

Re: [PATCH 5/6] crypto: stm32-hash: convert to the new crypto engine API

[Fabien DESSENNE]

On 03/01/18 21:11, Corentin Labbe wrote:
> This patch convert the stm32-hash driver to the new crypto engine API.
>
> Signed-off-by: Corentin Labbe 
> ---
>   drivers/crypto/stm32/stm32-hash.c | 18 +-
>   1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/crypto/stm32/stm32-hash.c 
> b/drivers/crypto/stm32/stm32-hash.c
> index 4ca4a264a833..9790c2c936c7 100644
> --- a/drivers/crypto/stm32/stm32-hash.c
> +++ b/drivers/crypto/stm32/stm32-hash.c
> @@ -122,6 +122,7 @@ enum stm32_hash_data_format {
>   #define HASH_DMA_THRESHOLD  50
>   
>   struct stm32_hash_ctx {
> + struct crypto_engine_reqctx enginectx;
>   struct stm32_hash_dev   *hdev;
>   unsigned long   flags;
>   
> @@ -828,6 +829,11 @@ static int stm32_hash_hw_init(struct stm32_hash_dev 
> *hdev,
>   return 0;
>   }
>   
> +static int stm32_hash_one_request(struct crypto_engine *engine,
> +   void *areq);

merge these two lines in a single one

> +static int stm32_hash_prepare_req(struct crypto_engine *engine,
> +   void *areq);

merge these two lines in a single one

> +
>   static int stm32_hash_handle_queue(struct stm32_hash_dev *hdev,
>  struct ahash_request *req)
>   {
> @@ -835,8 +841,9 @@ static int stm32_hash_handle_queue(struct stm32_hash_dev 
> *hdev,
>   }
>   
>   static int stm32_hash_prepare_req(struct crypto_engine *engine,
> -   struct ahash_request *req)
> +   void *areq)

merge these two lines in a single one

>   {
> + struct ahash_request *req = container_of(areq, struct ahash_request, 
> base);

 > 80 characters (CHECKPATCH)

>   struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
>   struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
>   struct stm32_hash_request_ctx *rctx;
> @@ -855,8 +862,9 @@ static int stm32_hash_prepare_req(struct crypto_engine 
> *engine,
>   }
>   
>   static int stm32_hash_one_request(struct crypto_engine *engine,
> -   struct ahash_request *req)
> +   void *areq)

merge these two lines in a single one

>   {
> + struct ahash_request *req = container_of(areq, struct ahash_request, 
> base);

 > 80 characters (CHECKPATCH)

>   struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
>   struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
>   struct stm32_hash_request_ctx *rctx;
> @@ -1033,6 +1041,9 @@ static int stm32_hash_cra_init_algs(struct crypto_tfm 
> *tfm,
>   if (algs_hmac_name)
>   ctx->flags |= HASH_FLAGS_HMAC;
>   
> + ctx->enginectx.op.do_one_request = stm32_hash_one_request;
> + ctx->enginectx.op.prepare_request = stm32_hash_prepare_req;
> + ctx->enginectx.op.unprepare_request = NULL;
>   return 0;
>   }
>   
> @@ -1493,9 +1504,6 @@ static int stm32_hash_probe(struct platform_device 
> *pdev)
>   goto err_engine;
>   }
>   
> - hdev->engine->prepare_hash_request = stm32_hash_prepare_req;
> - hdev->engine->hash_one_request = stm32_hash_one_request;
> -
>   ret = crypto_engine_start(hdev->engine);
>   if (ret)
>   goto err_engine_start;

Re: [PATCH 2/6] crypto: engine - Permit to enqueue all async requests

[Fabien DESSENNE]

On 03/01/18 21:11, Corentin Labbe wrote:
> The crypto engine could actually only enqueue hash and ablkcipher request.
> This patch permit it to enqueue any type of crypto_async_request.
>
> Signed-off-by: Corentin Labbe 
> ---
>   crypto/crypto_engine.c  | 230 
> 
>   include/crypto/engine.h |  59 +++--
>   2 files changed, 148 insertions(+), 141 deletions(-)
>
> diff --git a/crypto/crypto_engine.c b/crypto/crypto_engine.c
> index 61e7c4e02fd2..036270b61648 100644
> --- a/crypto/crypto_engine.c
> +++ b/crypto/crypto_engine.c
> @@ -15,7 +15,6 @@
>   #include 
>   #include 
>   #include 
> -#include 
>   #include 
>   #include "internal.h"
>   
> @@ -34,11 +33,10 @@ static void crypto_pump_requests(struct crypto_engine 
> *engine,
>bool in_kthread)
>   {
>   struct crypto_async_request *async_req, *backlog;
> - struct ahash_request *hreq;
> - struct ablkcipher_request *breq;
>   unsigned long flags;
>   bool was_busy = false;
> - int ret, rtype;
> + int ret;
> + struct crypto_engine_reqctx *enginectx;
>   
>   spin_lock_irqsave(>queue_lock, flags);
>   
> @@ -94,7 +92,6 @@ static void crypto_pump_requests(struct crypto_engine 
> *engine,
>   
>   spin_unlock_irqrestore(>queue_lock, flags);
>   
> - rtype = crypto_tfm_alg_type(engine->cur_req->tfm);
>   /* Until here we get the request need to be encrypted successfully */
>   if (!was_busy && engine->prepare_crypt_hardware) {
>   ret = engine->prepare_crypt_hardware(engine);
> @@ -104,57 +101,31 @@ static void crypto_pump_requests(struct crypto_engine 
> *engine,
>   }
>   }
>   
> - switch (rtype) {
> - case CRYPTO_ALG_TYPE_AHASH:
> - hreq = ahash_request_cast(engine->cur_req);
> - if (engine->prepare_hash_request) {
> - ret = engine->prepare_hash_request(engine, hreq);
> - if (ret) {
> - dev_err(engine->dev, "failed to prepare 
> request: %d\n",
> - ret);
> - goto req_err;
> - }
> - engine->cur_req_prepared = true;
> - }
> - ret = engine->hash_one_request(engine, hreq);
> - if (ret) {
> - dev_err(engine->dev, "failed to hash one request from 
> queue\n");
> - goto req_err;
> - }
> - return;
> - case CRYPTO_ALG_TYPE_ABLKCIPHER:
> - breq = ablkcipher_request_cast(engine->cur_req);
> - if (engine->prepare_cipher_request) {
> - ret = engine->prepare_cipher_request(engine, breq);
> - if (ret) {
> - dev_err(engine->dev, "failed to prepare 
> request: %d\n",
> - ret);
> - goto req_err;
> - }
> - engine->cur_req_prepared = true;
> - }
> - ret = engine->cipher_one_request(engine, breq);
> + enginectx = crypto_tfm_ctx(async_req->tfm);
> +
> + if (enginectx->op.prepare_request) {
> + ret = enginectx->op.prepare_request(engine, async_req);
>   if (ret) {
> - dev_err(engine->dev, "failed to cipher one request from 
> queue\n");
> + dev_err(engine->dev, "failed to prepare request: %d\n",
> + ret);
>   goto req_err;
>   }
> - return;
> - default:
> - dev_err(engine->dev, "failed to prepare request of unknown 
> type\n");
> - return;
> + engine->cur_req_prepared = true;
> + }
> + if (!enginectx->op.do_one_request) {
> + dev_err(engine->dev, "failed to do request\n");
> + ret = -EINVAL;
> + goto req_err;
> + }
> + ret = enginectx->op.do_one_request(engine, async_req);
> + if (ret) {
> + dev_err(engine->dev, "Failed to do one request from queue: 
> %d\n", ret);
> + goto req_err;
>   }
> + return;
>   
>   req_err:
> - switch (rtype) {
> - case CRYPTO_ALG_TYPE_AHASH:
> - hreq = ahash_request_cast(engine->cur_req);
> - crypto_finalize_hash_request(engine, hreq, ret);
> - break;
> - case CRYPTO_ALG_TYPE_ABLKCIPHER:
> - breq = ablkcipher_request_cast(engine->cur_req);
> - crypto_finalize_cipher_request(engine, breq, ret);
> - break;
> - }
> + crypto_finalize_request(engine, async_req, ret);
>   return;
>   
>   out:
> @@ -170,13 +141,12 @@ static void crypto_pump_work(struct kthread_work *work)
>   }
>   
>   /**
> - * crypto_transfer_cipher_request - transfer the new request into the
> - * enginequeue
> + 

Re: [PATCH 1/6] Documentation: crypto: document crypto engine API

[Fabien DESSENNE]

Hi Corentin,


Thank you for this new version which I have testes successfully with the 
stm32 hash & cryp drivers.

As a general comment on this patchset, I would say that it does not 
cover all async requests: typically I need (for the pending stm32 cryp 
driver uprade) to use CryptoEngine to process AEAD requests which is not 
covered here.

Could you please consider adding the 'transfer' and 'finalize' EXPORTed 
functions for aead requests? (the implementation is quite trivial)

Have also a look at struct acomp_req (acompress.h) and struct 
kpp_request (kpp.h) which also use "struct crypto_async_request base"


BR

Fabien


On 03/01/18 21:11, Corentin Labbe wrote:
> Signed-off-by: Corentin Labbe 
> ---
>   Documentation/crypto/crypto_engine.rst | 46 
> ++
>   1 file changed, 46 insertions(+)
>   create mode 100644 Documentation/crypto/crypto_engine.rst
>
> diff --git a/Documentation/crypto/crypto_engine.rst 
> b/Documentation/crypto/crypto_engine.rst
> new file mode 100644
> index ..b0ed37f9fb0c
> --- /dev/null
> +++ b/Documentation/crypto/crypto_engine.rst
> @@ -0,0 +1,46 @@
> +=
> +CRYPTO ENGINE
> +=
> +
> +Overview
> +
> +The crypto engine API (CE), is a crypto queue manager.
> +
> +Requirement
> +---
> +You have to put at start of your tfm_ctx the struct crypto_engine_reqctx
> +struct your_tfm_ctx {
> +struct crypto_engine_reqctx enginectx;
> +...
> +};
> +Why: Since CE manage only crypto_async_request, it cannot know the underlying
> +request_type and so have access only on the TFM.
> +So using container_of for accessing __ctx is impossible.
> +Furthermore, the crypto engine cannot know the "struct your_tfm_ctx",
> +so it must assume that crypto_engine_reqctx is at start of it.
> +
> +Order of operations
> +---
> +You have to obtain a struct crypto_engine via crypto_engine_alloc_init().
> +And start it via crypto_engine_start().
> +
> +Before transferring any request, you have to fill the enginectx.
> +- prepare_request: (taking a function pointer) If you need to do some 
> processing before doing the request
> +- unprepare_request: (taking a function pointer) Undoing what's done in 
> prepare_request
> +- do_one_request: (taking a function pointer) Do encryption for current 
> request
> +
> +Note: that those three functions get the crypto_async_request associated 
> with the received request.
> +So your need to get the original request via container_of(areq, struct 
> yourrequesttype_request, base);
> +
> +When your driver receive a crypto_request, you have to transfer it to
> +the cryptoengine via one of:
> +- crypto_transfer_cipher_request_to_engine()
> +- crypto_transfer_skcipher_request_to_engine()
> +- crypto_transfer_akcipher_request_to_engine()
> +- crypto_transfer_hash_request_to_engine()
> +
> +At the end of the request process, a call to one of the following function 
> is needed:
> +- crypto_finalize_cipher_request
> +- crypto_finalize_skcipher_request
> +- crypto_finalize_akcipher_request
> +- crypto_finalize_hash_request

Re: [PATCH] crypto: stm32 - Use standard CONFIG name

[Fabien DESSENNE]

Hi Corentin


Thank you for the patch.


On 20/12/17 19:19, Corentin Labbe wrote:
> All hardware crypto devices have their CONFIG names using the following
> convention:
> CRYPTO_DEV_name_algo
>
> This patch apply this conventions on STM32 CONFIG names.
>
> Signed-off-by: Corentin Labbe <cla...@baylibre.com>
Reviewed-by: Fabien Dessenne <fabien.desse...@st.com>
> ---
>   drivers/crypto/stm32/Kconfig  | 6 +++---
>   drivers/crypto/stm32/Makefile | 6 +++---
>   2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
> index 61ef00b6bf45..63aa78c0b12b 100644
> --- a/drivers/crypto/stm32/Kconfig
> +++ b/drivers/crypto/stm32/Kconfig
> @@ -1,4 +1,4 @@
> -config CRC_DEV_STM32
> +config CRYPTO_DEV_STM32_CRC
>   tristate "Support for STM32 crc accelerators"
>   depends on ARCH_STM32
>   select CRYPTO_HASH
> @@ -6,7 +6,7 @@ config CRC_DEV_STM32
> This enables support for the CRC32 hw accelerator which can be 
> found
> on STMicroelectronics STM32 SOC.
>   
> -config HASH_DEV_STM32
> +config CRYPTO_DEV_STM32_HASH
>   tristate "Support for STM32 hash accelerators"
>   depends on ARCH_STM32
>   depends on HAS_DMA
> @@ -19,7 +19,7 @@ config HASH_DEV_STM32
> This enables support for the HASH hw accelerator which can be 
> found
> on STMicroelectronics STM32 SOC.
>   
> -config CRYP_DEV_STM32
> +config CRYPTO_DEV_STM32_CRYP
>   tristate "Support for STM32 cryp accelerators"
>   depends on ARCH_STM32
>   select CRYPTO_HASH
> diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
> index 2c19fc155bfd..53d1bb94b221 100644
> --- a/drivers/crypto/stm32/Makefile
> +++ b/drivers/crypto/stm32/Makefile
> @@ -1,3 +1,3 @@
> -obj-$(CONFIG_CRC_DEV_STM32) += stm32_crc32.o
> -obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
> -obj-$(CONFIG_CRYP_DEV_STM32) += stm32-cryp.o
> +obj-$(CONFIG_CRYPTO_DEV_STM32_CRC) += stm32_crc32.o
> +obj-$(CONFIG_CRYPTO_DEV_STM32_HASH) += stm32-hash.o
> +obj-$(CONFIG_CRYPTO_DEV_STM32_CRYP) += stm32-cryp.o

Re: [PATCH] crypto: stm32: fix modular build

[Fabien DESSENNE]

Hi Arnd,

This issue was reported a few days ago, and Herbert applied the patch 2 
minutes before you send the mail (see 
[https://www.mail-archive.com/linux-crypto@vger.kernel.org/msg29762.html]).

Anyway, thank you for reporting this.

Fabien


On 11/12/17 12:47, Arnd Bergmann wrote:
> Building the stm32 crypto suport as a loadable module causes a build
> failure from a simple typo:
>
> drivers/crypto/stm32/stm32-cryp.c:1035:25: error: 'sti_dt_ids' undeclared 
> here (not in a function); did you mean 'stm32_dt_ids'?
>
> This renames the reference to point to the correct symbol.
>
> Fixes: 9e054ec21ef8 ("crypto: stm32 - Support for STM32 CRYP crypto module")
> Signed-off-by: Arnd Bergmann 
> ---
>   drivers/crypto/stm32/stm32-cryp.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/stm32/stm32-cryp.c 
> b/drivers/crypto/stm32/stm32-cryp.c
> index 459755940632..cf1dddbeaa2c 100644
> --- a/drivers/crypto/stm32/stm32-cryp.c
> +++ b/drivers/crypto/stm32/stm32-cryp.c
> @@ -1032,7 +1032,7 @@ static const struct of_device_id stm32_dt_ids[] = {
>   { .compatible = "st,stm32f756-cryp", },
>   {},
>   };
> -MODULE_DEVICE_TABLE(of, sti_dt_ids);
> +MODULE_DEVICE_TABLE(of, stm32_dt_ids);
>   
>   static int stm32_cryp_probe(struct platform_device *pdev)
>   {

Re: [PATCH RFC 4/4] crypto: stm32: convert to the new crypto engine API

[Fabien DESSENNE]

Hi,


On 29/11/17 09:41, Corentin Labbe wrote:
> This patch convert the driver to the new crypto engine API.
>
> Signed-off-by: Corentin Labbe <clabbe.montj...@gmail.com>

Tested-by: Fabien Dessenne <fabien.desse...@st.com>

> ---
>   drivers/crypto/stm32/stm32-hash.c | 22 +++---
>   1 file changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/crypto/stm32/stm32-hash.c 
> b/drivers/crypto/stm32/stm32-hash.c
> index 4ca4a264a833..e3f9f7b04ce2 100644
> --- a/drivers/crypto/stm32/stm32-hash.c
> +++ b/drivers/crypto/stm32/stm32-hash.c
> @@ -122,6 +122,7 @@ enum stm32_hash_data_format {
>   #define HASH_DMA_THRESHOLD  50
>   
>   struct stm32_hash_ctx {
> + struct crypto_engine_reqctx enginectx;
>   struct stm32_hash_dev   *hdev;
>   unsigned long   flags;
>   
> @@ -811,7 +812,7 @@ static void stm32_hash_finish_req(struct ahash_request 
> *req, int err)
>   rctx->flags |= HASH_FLAGS_ERRORS;
>   }
>   
> - crypto_finalize_hash_request(hdev->engine, req, err);
> + crypto_finalize_request(hdev->engine, >base, err);
>   }
>   
>   static int stm32_hash_hw_init(struct stm32_hash_dev *hdev,
> @@ -828,15 +829,21 @@ static int stm32_hash_hw_init(struct stm32_hash_dev 
> *hdev,
>   return 0;
>   }
>   
> +static int stm32_hash_one_request(struct crypto_engine *engine,
> +   struct crypto_async_request *areq);
> +static int stm32_hash_prepare_req(struct crypto_engine *engine,
> +   struct crypto_async_request *areq);
> +
>   static int stm32_hash_handle_queue(struct stm32_hash_dev *hdev,
>  struct ahash_request *req)
>   {
> - return crypto_transfer_hash_request_to_engine(hdev->engine, req);
> + return crypto_transfer_request_to_engine(hdev->engine, >base);
>   }
>   
>   static int stm32_hash_prepare_req(struct crypto_engine *engine,
> -   struct ahash_request *req)
> +   struct crypto_async_request *areq)
>   {
> + struct ahash_request *req = ahash_request_cast(areq);
>   struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
>   struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
>   struct stm32_hash_request_ctx *rctx;
> @@ -855,8 +862,9 @@ static int stm32_hash_prepare_req(struct crypto_engine 
> *engine,
>   }
>   
>   static int stm32_hash_one_request(struct crypto_engine *engine,
> -   struct ahash_request *req)
> +   struct crypto_async_request *areq)
>   {
> + struct ahash_request *req = ahash_request_cast(areq);
>   struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
>   struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
>   struct stm32_hash_request_ctx *rctx;
> @@ -1033,6 +1041,9 @@ static int stm32_hash_cra_init_algs(struct crypto_tfm 
> *tfm,
>   if (algs_hmac_name)
>   ctx->flags |= HASH_FLAGS_HMAC;
>   
> + ctx->enginectx.op.do_one_request = stm32_hash_one_request;
> + ctx->enginectx.op.prepare_request = stm32_hash_prepare_req;
> + ctx->enginectx.op.unprepare_request = NULL;
>   return 0;
>   }
>   
> @@ -1493,9 +1504,6 @@ static int stm32_hash_probe(struct platform_device 
> *pdev)
>   goto err_engine;
>   }
>   
> - hdev->engine->prepare_hash_request = stm32_hash_prepare_req;
> - hdev->engine->hash_one_request = stm32_hash_one_request;
> -
>   ret = crypto_engine_start(hdev->engine);
>   if (ret)
>   goto err_engine_start;

Re: [PATCH RFC 1/4] crypto: engine - Permit to enqueue all async requests

[Fabien DESSENNE]

On 29/11/17 09:41, Corentin Labbe wrote:
> The crypto engine could actually only enqueue hash and ablkcipher request.
> This patch permit it to enqueue any type of crypto_async_request.
>
> Signed-off-by: Corentin Labbe 
> ---
>   crypto/crypto_engine.c  | 188 
> +++-
>   include/crypto/engine.h |  46 +---
>   2 files changed, 60 insertions(+), 174 deletions(-)
>
> diff --git a/crypto/crypto_engine.c b/crypto/crypto_engine.c
> index 61e7c4e02fd2..f7c4c4c1f41b 100644
> --- a/crypto/crypto_engine.c
> +++ b/crypto/crypto_engine.c
> @@ -34,11 +34,10 @@ static void crypto_pump_requests(struct crypto_engine 
> *engine,
>bool in_kthread)
>   {
>   struct crypto_async_request *async_req, *backlog;
> - struct ahash_request *hreq;
> - struct ablkcipher_request *breq;
>   unsigned long flags;
>   bool was_busy = false;
> - int ret, rtype;
> + int ret;
> + struct crypto_engine_reqctx *enginectx;
>   
>   spin_lock_irqsave(>queue_lock, flags);
>   
> @@ -94,7 +93,6 @@ static void crypto_pump_requests(struct crypto_engine 
> *engine,
>   
>   spin_unlock_irqrestore(>queue_lock, flags);
>   
> - rtype = crypto_tfm_alg_type(engine->cur_req->tfm);
>   /* Until here we get the request need to be encrypted successfully */
>   if (!was_busy && engine->prepare_crypt_hardware) {
>   ret = engine->prepare_crypt_hardware(engine);
> @@ -104,57 +102,31 @@ static void crypto_pump_requests(struct crypto_engine 
> *engine,
>   }
>   }
>   
> - switch (rtype) {
> - case CRYPTO_ALG_TYPE_AHASH:
> - hreq = ahash_request_cast(engine->cur_req);
> - if (engine->prepare_hash_request) {
> - ret = engine->prepare_hash_request(engine, hreq);
> - if (ret) {
> - dev_err(engine->dev, "failed to prepare 
> request: %d\n",
> - ret);
> - goto req_err;
> - }
> - engine->cur_req_prepared = true;
> - }
> - ret = engine->hash_one_request(engine, hreq);
> - if (ret) {
> - dev_err(engine->dev, "failed to hash one request from 
> queue\n");
> - goto req_err;
> - }
> - return;
> - case CRYPTO_ALG_TYPE_ABLKCIPHER:
> - breq = ablkcipher_request_cast(engine->cur_req);
> - if (engine->prepare_cipher_request) {
> - ret = engine->prepare_cipher_request(engine, breq);
> - if (ret) {
> - dev_err(engine->dev, "failed to prepare 
> request: %d\n",
> - ret);
> - goto req_err;
> - }
> - engine->cur_req_prepared = true;
> - }
> - ret = engine->cipher_one_request(engine, breq);
> + enginectx = crypto_tfm_ctx(async_req->tfm);
> +
> + if (enginectx->op.prepare_request) {
> + ret = enginectx->op.prepare_request(engine, async_req);
>   if (ret) {
> - dev_err(engine->dev, "failed to cipher one request from 
> queue\n");
> + dev_err(engine->dev, "failed to prepare request: %d\n",
> + ret);
>   goto req_err;
>   }
> - return;
> - default:
> - dev_err(engine->dev, "failed to prepare request of unknown 
> type\n");
> - return;
> + engine->cur_req_prepared = true;
> + }
> + if (!enginectx->op.do_one_request) {
> + dev_err(engine->dev, "failed to do request\n");
> + ret = -EINVAL;
> + goto req_err;
> + }
> + ret = enginectx->op.do_one_request(engine, async_req);
> + if (ret) {
> + dev_err(engine->dev, "failed to hash one request from queue\n");
> + goto req_err;
>   }
> + return;
>   
>   req_err:
> - switch (rtype) {
> - case CRYPTO_ALG_TYPE_AHASH:
> - hreq = ahash_request_cast(engine->cur_req);
> - crypto_finalize_hash_request(engine, hreq, ret);
> - break;
> - case CRYPTO_ALG_TYPE_ABLKCIPHER:
> - breq = ablkcipher_request_cast(engine->cur_req);
> - crypto_finalize_cipher_request(engine, breq, ret);
> - break;
> - }
> + crypto_finalize_request(engine, async_req, ret);
>   return;
>   
>   out:
> @@ -170,59 +142,16 @@ static void crypto_pump_work(struct kthread_work *work)
>   }
>   
>   /**
> - * crypto_transfer_cipher_request - transfer the new request into the
> - * enginequeue
> + * crypto_transfer_request - transfer the new request into the engine queue
>* @engine: the hardware engine
>* @req: the 

Re: [PATCH RFC 0/4] crypto: engine - Permit to enqueue all async requests

[Fabien DESSENNE]

Hi Corentin,


I am fine with this proposal: it is generic enough and I have been able 
to test and run the crypto engine with aead_request without changing any 
single line of code.

This is what I need to be able to send the AEAD extension of the 
stm32-cryp driver (successfully tested with your engine upgrade proposal).


I have also tested the stm32-hash patch.

Note that stm32-cryp (new driver applied by Herbert recently 
[https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git/commit/?id=9e054ec21ef8344345b28603fb272fe999f735db])
 
would also need to be converted to the new crypto engine API : this is a 
trivial patch.

Thank you for your proposal, I hope that this proposal is fine for 
Herbert too.

BR


Fabien


On 29/11/17 09:41, Corentin Labbe wrote:
> Hello
>
> The current crypto_engine support only ahash and ablkcipher.
> My first patch which try to add skcipher was Nacked, it will add too many 
> functions
> and adding other algs(aead, asymetric_key) will make the situation worst.
>
> This patchset remove all algs specific stuff and now only process generic 
> crypto_async_request.
>
> The requests handler function pointer are now moved out of struct engine and
> are now stored directly in a crypto_engine_reqctx.
>
> The original proposal of Herbert [1] cannot be done completly since the 
> crypto_engine
> could only dequeue crypto_async_request and it is impossible to access any 
> request_ctx
> without knowing the underlying request type.
>
> So I do something near that was requested: adding crypto_engine_reqctx in TFM 
> context.
> Note that the current implementation expect that crypto_engine_reqctx
> is the first member of the context.
>
> The first patch convert the crypto engine with the new way,
> while the following patchs convert the 3 existing users of crypto_engine.
> Note that this split break bisection, so probably the final commit will be 
> all merged.
>
> The 3 latest patch were compile tested only, but the first is tested 
> successfully
> with my new sun8i-ce driver.
>
> Regards
>
> [1] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1474434.html
>
> Corentin Labbe (4):
>crypto: engine - Permit to enqueue all async requests
>crypto: omap: convert to new crypto engine API
>crypto: virtio: convert to new crypto engine API
>crypto: stm32: convert to the new crypto engine API
>
>   crypto/crypto_engine.c   | 188 
> ++-
>   drivers/crypto/omap-aes.c|  21 ++-
>   drivers/crypto/omap-aes.h|   3 +
>   drivers/crypto/omap-des.c|  24 +++-
>   drivers/crypto/stm32/stm32-hash.c|  22 +++-
>   drivers/crypto/virtio/virtio_crypto_algs.c   |  15 ++-
>   drivers/crypto/virtio/virtio_crypto_common.h |   2 +-
>   drivers/crypto/virtio/virtio_crypto_core.c   |   3 -
>   include/crypto/engine.h  |  46 +++
>   9 files changed, 122 insertions(+), 202 deletions(-)
>

Re: [PATCH] crypto: stm32: fix module device table name

[Fabien DESSENNE]

Hi Corentin


Thank you for the patch.


On 30/11/17 12:04, Corentin Labbe wrote:
> This patch fix the following build failure:
>CC [M]  drivers/crypto/stm32/stm32-cryp.o
> In file included from drivers/crypto/stm32/stm32-cryp.c:11:0:
> drivers/crypto/stm32/stm32-cryp.c:1049:25: error: 'sti_dt_ids' undeclared 
> here (not in a function)
>   MODULE_DEVICE_TABLE(of, sti_dt_ids);
>
> Let's replace sti_dt_ids with stm32_dt_ids which is just declared
> before.
>
> Signed-off-by: Corentin Labbe <clabbe.montj...@gmail.com>

Reviewed-by: Fabien Dessenne <fabien.desse...@st.com>

> ---
>   drivers/crypto/stm32/stm32-cryp.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/stm32/stm32-cryp.c 
> b/drivers/crypto/stm32/stm32-cryp.c
> index 098fad266c41..1807789b23f5 100644
> --- a/drivers/crypto/stm32/stm32-cryp.c
> +++ b/drivers/crypto/stm32/stm32-cryp.c
> @@ -1046,7 +1046,7 @@ static const struct of_device_id stm32_dt_ids[] = {
>   { .compatible = "st,stm32f756-cryp", },
>   {},
>   };
> -MODULE_DEVICE_TABLE(of, sti_dt_ids);
> +MODULE_DEVICE_TABLE(of, stm32_dt_ids);
>   
>   static int stm32_cryp_probe(struct platform_device *pdev)
>   {

Re: [PATCH v5 2/2] crypto: stm32 - Support for STM32 CRYP crypto module

[Fabien DESSENNE]

Just a gentle ping ... or have I missed out on a reply?


On 13/11/17 11:30, Fabien DESSENNE wrote:
> Hi Herbert,
>
> Can you check if this patchset (removed the AEAD part as you suggested +
> libkcapi test OK as suggested by Corentin) can be applied now?
>
> BR
>
> Fabien
>
>
> On 07/11/17 15:40, Fabien DESSENNE wrote:
>> On 22/10/17 09:26, Corentin Labbe wrote:
>>> On Thu, Oct 19, 2017 at 05:10:30PM +0200, Fabien Dessenne wrote:
>>>> This module registers block cipher algorithms that make use of the
>>>> STMicroelectronics STM32 crypto "CRYP1" hardware.
>>>> The following algorithms are supported:
>>>> - aes: ecb, cbc, ctr
>>>> - des: ecb, cbc
>>>> - tdes: ecb, cbc
>>>>
>>>> Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
>>>> ---
>>>> drivers/crypto/stm32/Kconfig  |9 +
>>>> drivers/crypto/stm32/Makefile |3 +-
>>>> drivers/crypto/stm32/stm32-cryp.c | 1172 
>>>> +
>>>> 3 files changed, 1183 insertions(+), 1 deletion(-)
>>>> create mode 100644 drivers/crypto/stm32/stm32-cryp.c
>>>>
>>>> diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
>>>> +static void stm32_cryp_irq_write_block(struct stm32_cryp *cryp)
>>>> +{
>>>> +  unsigned int i, j;
>>>> +  u32 *src;
>>>> +  u8 d8[4];
>>>> +
>>>> +  src = sg_virt(cryp->in_sg) + _walked_in;
>>>> +
>>>> +  for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++) {
>>>> +  if (likely(cryp->total_in >= sizeof(u32))) {
>>>> +  /* Write a full u32 */
>>>> +  stm32_cryp_write(cryp, CRYP_DIN, *src);
>>> Hello
>>>
>>> Try also to test your driver with userspace via AF_ALG (libkcapi is a good 
>>> start).
>>> It should probably crash here.
>>> I have do the same on my first sunxi-ss driver and you should use kmap().
>>>
>>> Regards
>> Hi Corentin,
>>
>> Thank you for suggesting to test from userspace through the AF_ALG
>> socket with libkcapi.
>> This increases my test coverage.
>>
>> I ran the miscellaneous tests (kcapi-enc-test(large).sh + test.sh) and
>> could not observe any crash.
>> Note that I had already fixed some 'memory crashes' while testing with
>> testmgr / tcrypt while testing from the kernel.
>>
>> So it looks like the proposed implementation is fine.
>>
>> BR
>>
>> Fabien

Re: [PATCH v5 2/2] crypto: stm32 - Support for STM32 CRYP crypto module

[Fabien DESSENNE]

Hi Herbert,

Can you check if this patchset (removed the AEAD part as you suggested + 
libkcapi test OK as suggested by Corentin) can be applied now?

BR

Fabien


On 07/11/17 15:40, Fabien DESSENNE wrote:
>
> On 22/10/17 09:26, Corentin Labbe wrote:
>> On Thu, Oct 19, 2017 at 05:10:30PM +0200, Fabien Dessenne wrote:
>>> This module registers block cipher algorithms that make use of the
>>> STMicroelectronics STM32 crypto "CRYP1" hardware.
>>> The following algorithms are supported:
>>> - aes: ecb, cbc, ctr
>>> - des: ecb, cbc
>>> - tdes: ecb, cbc
>>>
>>> Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
>>> ---
>>>drivers/crypto/stm32/Kconfig  |9 +
>>>drivers/crypto/stm32/Makefile |3 +-
>>>drivers/crypto/stm32/stm32-cryp.c | 1172 
>>> +
>>>3 files changed, 1183 insertions(+), 1 deletion(-)
>>>create mode 100644 drivers/crypto/stm32/stm32-cryp.c
>>>
>>> diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
>>> +static void stm32_cryp_irq_write_block(struct stm32_cryp *cryp)
>>> +{
>>> +   unsigned int i, j;
>>> +   u32 *src;
>>> +   u8 d8[4];
>>> +
>>> +   src = sg_virt(cryp->in_sg) + _walked_in;
>>> +
>>> +   for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++) {
>>> +   if (likely(cryp->total_in >= sizeof(u32))) {
>>> +   /* Write a full u32 */
>>> +   stm32_cryp_write(cryp, CRYP_DIN, *src);
>> Hello
>>
>> Try also to test your driver with userspace via AF_ALG (libkcapi is a good 
>> start).
>> It should probably crash here.
>> I have do the same on my first sunxi-ss driver and you should use kmap().
>>
>> Regards
> Hi Corentin,
>
> Thank you for suggesting to test from userspace through the AF_ALG
> socket with libkcapi.
> This increases my test coverage.
>
> I ran the miscellaneous tests (kcapi-enc-test(large).sh + test.sh) and
> could not observe any crash.
> Note that I had already fixed some 'memory crashes' while testing with
> testmgr / tcrypt while testing from the kernel.
>
> So it looks like the proposed implementation is fine.
>
> BR
>
> Fabien

Re: [PATCH v5 2/2] crypto: stm32 - Support for STM32 CRYP crypto module

[Fabien DESSENNE]

On 22/10/17 09:26, Corentin Labbe wrote:
> On Thu, Oct 19, 2017 at 05:10:30PM +0200, Fabien Dessenne wrote:
>> This module registers block cipher algorithms that make use of the
>> STMicroelectronics STM32 crypto "CRYP1" hardware.
>> The following algorithms are supported:
>> - aes: ecb, cbc, ctr
>> - des: ecb, cbc
>> - tdes: ecb, cbc
>>
>> Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
>> ---
>>   drivers/crypto/stm32/Kconfig  |9 +
>>   drivers/crypto/stm32/Makefile |3 +-
>>   drivers/crypto/stm32/stm32-cryp.c | 1172 
>> +
>>   3 files changed, 1183 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/crypto/stm32/stm32-cryp.c
>>
>> diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
>> +static void stm32_cryp_irq_write_block(struct stm32_cryp *cryp)
>> +{
>> +unsigned int i, j;
>> +u32 *src;
>> +u8 d8[4];
>> +
>> +src = sg_virt(cryp->in_sg) + _walked_in;
>> +
>> +for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++) {
>> +if (likely(cryp->total_in >= sizeof(u32))) {
>> +/* Write a full u32 */
>> +stm32_cryp_write(cryp, CRYP_DIN, *src);
> Hello
>
> Try also to test your driver with userspace via AF_ALG (libkcapi is a good 
> start).
> It should probably crash here.
> I have do the same on my first sunxi-ss driver and you should use kmap().
>
> Regards
Hi Corentin,

Thank you for suggesting to test from userspace through the AF_ALG 
socket with libkcapi.
This increases my test coverage.

I ran the miscellaneous tests (kcapi-enc-test(large).sh + test.sh) and 
could not observe any crash.
Note that I had already fixed some 'memory crashes' while testing with 
testmgr / tcrypt while testing from the kernel.

So it looks like the proposed implementation is fine.

BR

Fabien

[PATCH v5 2/2] crypto: stm32 - Support for STM32 CRYP crypto module

[Fabien Dessenne]

This module registers block cipher algorithms that make use of the
STMicroelectronics STM32 crypto "CRYP1" hardware.
The following algorithms are supported:
- aes: ecb, cbc, ctr
- des: ecb, cbc
- tdes: ecb, cbc

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 drivers/crypto/stm32/Kconfig  |9 +
 drivers/crypto/stm32/Makefile |3 +-
 drivers/crypto/stm32/stm32-cryp.c | 1172 +
 3 files changed, 1183 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/stm32/stm32-cryp.c

diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
index 602332e..61ef00b 100644
--- a/drivers/crypto/stm32/Kconfig
+++ b/drivers/crypto/stm32/Kconfig
@@ -18,3 +18,12 @@ config HASH_DEV_STM32
help
   This enables support for the HASH hw accelerator which can be found
  on STMicroelectronics STM32 SOC.
+
+config CRYP_DEV_STM32
+   tristate "Support for STM32 cryp accelerators"
+   depends on ARCH_STM32
+   select CRYPTO_HASH
+   select CRYPTO_ENGINE
+   help
+  This enables support for the CRYP (AES/DES/TDES) hw accelerator which
+ can be found on STMicroelectronics STM32 SOC.
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
index 73cd56c..2c19fc1 100644
--- a/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_CRC_DEV_STM32) += stm32_crc32.o
-obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
\ No newline at end of file
+obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
+obj-$(CONFIG_CRYP_DEV_STM32) += stm32-cryp.o
diff --git a/drivers/crypto/stm32/stm32-cryp.c 
b/drivers/crypto/stm32/stm32-cryp.c
new file mode 100644
index 000..4597559
--- /dev/null
+++ b/drivers/crypto/stm32/stm32-cryp.c
@@ -0,0 +1,1172 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author: Fabien Dessenne <fabien.desse...@st.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#define DRIVER_NAME "stm32-cryp"
+
+/* Bit [0] encrypt / decrypt */
+#define FLG_ENCRYPT BIT(0)
+/* Bit [8..1] algo & operation mode */
+#define FLG_AES BIT(1)
+#define FLG_DES BIT(2)
+#define FLG_TDESBIT(3)
+#define FLG_ECB BIT(4)
+#define FLG_CBC BIT(5)
+#define FLG_CTR BIT(6)
+/* Mode mask = bits [15..0] */
+#define FLG_MODE_MASK   GENMASK(15, 0)
+
+/* Registers */
+#define CRYP_CR 0x
+#define CRYP_SR 0x0004
+#define CRYP_DIN0x0008
+#define CRYP_DOUT   0x000C
+#define CRYP_DMACR  0x0010
+#define CRYP_IMSCR  0x0014
+#define CRYP_RISR   0x0018
+#define CRYP_MISR   0x001C
+#define CRYP_K0LR   0x0020
+#define CRYP_K0RR   0x0024
+#define CRYP_K1LR   0x0028
+#define CRYP_K1RR   0x002C
+#define CRYP_K2LR   0x0030
+#define CRYP_K2RR   0x0034
+#define CRYP_K3LR   0x0038
+#define CRYP_K3RR   0x003C
+#define CRYP_IV0LR  0x0040
+#define CRYP_IV0RR  0x0044
+#define CRYP_IV1LR  0x0048
+#define CRYP_IV1RR  0x004C
+
+/* Registers values */
+#define CR_DEC_NOT_ENC  0x0004
+#define CR_TDES_ECB 0x
+#define CR_TDES_CBC 0x0008
+#define CR_DES_ECB  0x0010
+#define CR_DES_CBC  0x0018
+#define CR_AES_ECB  0x0020
+#define CR_AES_CBC  0x0028
+#define CR_AES_CTR  0x0030
+#define CR_AES_KP   0x0038
+#define CR_AES_UNKNOWN  0x
+#define CR_ALGO_MASK0x00080038
+#define CR_DATA32   0x
+#define CR_DATA16   0x0040
+#define CR_DATA80x0080
+#define CR_DATA10x00C0
+#define CR_KEY128   0x
+#define CR_KEY192   0x0100
+#define CR_KEY256   0x0200
+#define CR_FFLUSH   0x4000
+#define CR_CRYPEN   0x8000
+
+#define SR_BUSY 0x0010
+#define SR_OFNE 0x0004
+
+#define IMSCR_INBIT(0)
+#define IMSCR_OUT   BIT(1)
+
+#define MISR_IN BIT(0)
+#define MISR_OUTBIT(1)
+
+/* Misc */
+#define AES_BLOCK_32(AES_BLOCK_SIZE / sizeof(u32))
+#define _walked_in  (cryp->in_walk.offset - cryp->in_sg->offset)
+#define _walked_out (cryp->out_walk.offset - cryp->out_sg->offset)
+
+struct stm

[PATCH v5 1/2] dt-bindings: Document STM32 CRYP bindings

[Fabien Dessenne]

Document device tree bindings for the STM32 CRYP.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/crypto/st,stm32-cryp.txt  | 19 +++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt 
b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
new file mode 100644
index 000..970487f
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
@@ -0,0 +1,19 @@
+* STMicroelectronics STM32 CRYP
+
+Required properties:
+- compatible: Should be "st,stm32f756-cryp".
+- reg: The address and length of the peripheral registers space
+- clocks: The input clock of the CRYP instance
+- interrupts: The CRYP interrupt
+
+Optional properties:
+- resets: The input reset of the CRYP instance
+
+Example:
+crypto@5006 {
+   compatible = "st,stm32f756-cryp";
+   reg = <0x5006 0x400>;
+   interrupts = <79>;
+   clocks = < 0 STM32F7_AHB2_CLOCK(CRYP)>;
+   resets = < STM32F7_AHB2_RESET(CRYP)>;
+};
-- 
2.7.4

[PATCH v5 0/2] STM32 CRYP crypto driver

[Fabien Dessenne]

This set of patches adds a new crypto driver for STMicroelectronics stm32 HW.
This drivers uses the crypto API and provides with HW-enabled block cipher
algorithms.

This driver was successfully tested with tcrypt / testmgr.

Changes since v5:
-add timeout in wait_busy function
-clear key after use
-misc : remove unused functions, use -Exx, use dev_err

Changes since v4:
- remove AEAD support from crypto engine as proposed by Herbert : waiting for
  the crypto_engine interface clean up before
  [https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1474434.html]
- remove AES GCM & CCM algorithms

Changes since v3:
- update dt-bindings with Rob Herring remarks

Changes since v2:
- update dt-bindings (interrupts description)
- rebase on STM32 crypto patches (L. Debieve : update CRC32 + add HASH)

Fabien Dessenne (2):
  dt-bindings: Document STM32 CRYP bindings
  crypto: stm32 - Support for STM32 CRYP crypto module

 .../devicetree/bindings/crypto/st,stm32-cryp.txt   |   19 +
 drivers/crypto/stm32/Kconfig   |9 +
 drivers/crypto/stm32/Makefile  |3 +-
 drivers/crypto/stm32/stm32-cryp.c  | 1172 
 4 files changed, 1202 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
 create mode 100644 drivers/crypto/stm32/stm32-cryp.c

-- 
2.7.4

Re: [PATCH v4 2/2] crypto: stm32 - Support for STM32 CRYP crypto module

[Fabien DESSENNE]

Hi Corentin


Thank you for your comments. I will fix according to them. See also me 
answers/questions below

While we are at it, do you plan to deliver a new version of the 
crypto_engine update? (I had to remove the AEAD part of this new driver 
since it depends on that pending update)

BR

Fabien


On 19/10/17 12:34, Corentin Labbe wrote:
> Hello
>
> I have some minor comment below
>
> On Thu, Oct 19, 2017 at 11:03:59AM +0200, Fabien Dessenne wrote:
>> This module registers block cipher algorithms that make use of the
>> STMicroelectronics STM32 crypto "CRYP1" hardware.
>> The following algorithms are supported:
>> - aes: ecb, cbc, ctr
>> - des: ecb, cbc
>> - tdes: ecb, cbc
>>
>> Signed-off-by: Fabien Dessennie <fabien.desse...@st.com>
>> ---
>>   drivers/crypto/stm32/Kconfig  |9 +
>>   drivers/crypto/stm32/Makefile |3 +-
>>   drivers/crypto/stm32/stm32-cryp.c | 1188 
>> +
>>   3 files changed, 1199 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/crypto/stm32/stm32-cryp.c
>>
>> diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
>> index 602332e..61ef00b 100644
>> --- a/drivers/crypto/stm32/Kconfig
>> +++ b/drivers/crypto/stm32/Kconfig
> [...]
>> +/* Bit [0] encrypt / decrypt */
>> +#define FLG_ENCRYPT BIT(0)
>> +/* Bit [8..1] algo & operation mode */
>> +#define FLG_AES BIT(1)
>> +#define FLG_DES BIT(2)
>> +#define FLG_TDESBIT(3)
>> +#define FLG_ECB BIT(4)
>> +#define FLG_CBC BIT(5)
>> +#define FLG_CTR BIT(6)
>> +/* Mode mask = bits [15..0] */
>> +#define FLG_MODE_MASK   GENMASK(15, 0)
>> +
>> +/* Registers */
>> +#define CRYP_CR 0x
>> +#define CRYP_SR 0x0004
>> +#define CRYP_DIN0x0008
>> +#define CRYP_DOUT   0x000C
>> +#define CRYP_DMACR  0x0010
>> +#define CRYP_IMSCR  0x0014
>> +#define CRYP_RISR   0x0018
>> +#define CRYP_MISR   0x001C
>> +#define CRYP_K0LR   0x0020
>> +#define CRYP_K0RR   0x0024
>> +#define CRYP_K1LR   0x0028
>> +#define CRYP_K1RR   0x002C
>> +#define CRYP_K2LR   0x0030
>> +#define CRYP_K2RR   0x0034
>> +#define CRYP_K3LR   0x0038
>> +#define CRYP_K3RR   0x003C
>> +#define CRYP_IV0LR  0x0040
>> +#define CRYP_IV0RR  0x0044
>> +#define CRYP_IV1LR  0x0048
>> +#define CRYP_IV1RR  0x004C
>> +
>> +/* Registers values */
>> +#define CR_DEC_NOT_ENC  0x0004
>> +#define CR_TDES_ECB 0x
>> +#define CR_TDES_CBC 0x0008
>> +#define CR_DES_ECB  0x0010
>> +#define CR_DES_CBC  0x0018
>> +#define CR_AES_ECB  0x0020
>> +#define CR_AES_CBC  0x0028
>> +#define CR_AES_CTR  0x0030
>> +#define CR_AES_KP   0x0038
>> +#define CR_AES_UNKNOWN  0x
>> +#define CR_ALGO_MASK0x00080038
>> +#define CR_DATA32   0x
>> +#define CR_DATA16   0x0040
>> +#define CR_DATA80x0080
>> +#define CR_DATA10x00C0
>> +#define CR_KEY128   0x
>> +#define CR_KEY192   0x0100
>> +#define CR_KEY256   0x0200
>> +#define CR_FFLUSH   0x4000
>> +#define CR_CRYPEN   0x8000
> Why not using BIT(x) ?

Some values are not only 1 bit (then we may use BIT and BITGEN but this 
would be less readable), so I prefer to keep this values.

> Why not using also directly FLG_XX since CR_XX are arbitray values ? like 
> using instead CR_AES_CBC = FLG_AES | FLG_CBC

The CR_ values are used to write in the registers. FLG_ are arbitraty 
values, so we cannot mix them.

>
> [...]
>> +static inline void stm32_cryp_wait_enable(struct stm32_cryp *cryp)
>> +{
>> +while (stm32_cryp_read(cryp, CRYP_CR) & CR_CRYPEN)
>> +cpu_relax();
>> +}
> This function is not used, so you could remove it
>
>> +
>> +static inline void stm32_cryp_wait_busy(struct stm32_cryp *cryp)
>> +{
>> +while (stm32_cryp_read(cryp, CRYP_SR) & SR_BUSY)
&g

[PATCH v4 1/2] dt-bindings: Document STM32 CRYP bindings

[Fabien Dessenne]

Document device tree bindings for the STM32 CRYP.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/crypto/st,stm32-cryp.txt  | 19 +++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt 
b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
new file mode 100644
index 000..970487f
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
@@ -0,0 +1,19 @@
+* STMicroelectronics STM32 CRYP
+
+Required properties:
+- compatible: Should be "st,stm32f756-cryp".
+- reg: The address and length of the peripheral registers space
+- clocks: The input clock of the CRYP instance
+- interrupts: The CRYP interrupt
+
+Optional properties:
+- resets: The input reset of the CRYP instance
+
+Example:
+crypto@5006 {
+   compatible = "st,stm32f756-cryp";
+   reg = <0x5006 0x400>;
+   interrupts = <79>;
+   clocks = < 0 STM32F7_AHB2_CLOCK(CRYP)>;
+   resets = < STM32F7_AHB2_RESET(CRYP)>;
+};
-- 
2.7.4

[PATCH v4 2/2] crypto: stm32 - Support for STM32 CRYP crypto module

[Fabien Dessenne]

This module registers block cipher algorithms that make use of the
STMicroelectronics STM32 crypto "CRYP1" hardware.
The following algorithms are supported:
- aes: ecb, cbc, ctr
- des: ecb, cbc
- tdes: ecb, cbc

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 drivers/crypto/stm32/Kconfig  |9 +
 drivers/crypto/stm32/Makefile |3 +-
 drivers/crypto/stm32/stm32-cryp.c | 1188 +
 3 files changed, 1199 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/stm32/stm32-cryp.c

diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
index 602332e..61ef00b 100644
--- a/drivers/crypto/stm32/Kconfig
+++ b/drivers/crypto/stm32/Kconfig
@@ -18,3 +18,12 @@ config HASH_DEV_STM32
help
   This enables support for the HASH hw accelerator which can be found
  on STMicroelectronics STM32 SOC.
+
+config CRYP_DEV_STM32
+   tristate "Support for STM32 cryp accelerators"
+   depends on ARCH_STM32
+   select CRYPTO_HASH
+   select CRYPTO_ENGINE
+   help
+  This enables support for the CRYP (AES/DES/TDES) hw accelerator which
+ can be found on STMicroelectronics STM32 SOC.
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
index 73cd56c..2c19fc1 100644
--- a/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_CRC_DEV_STM32) += stm32_crc32.o
-obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
\ No newline at end of file
+obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
+obj-$(CONFIG_CRYP_DEV_STM32) += stm32-cryp.o
diff --git a/drivers/crypto/stm32/stm32-cryp.c 
b/drivers/crypto/stm32/stm32-cryp.c
new file mode 100644
index 000..ede2995
--- /dev/null
+++ b/drivers/crypto/stm32/stm32-cryp.c
@@ -0,0 +1,1188 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author: Fabien Dessenne <fabien.desse...@st.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#define DRIVER_NAME "stm32-cryp"
+
+/* Bit [0] encrypt / decrypt */
+#define FLG_ENCRYPT BIT(0)
+/* Bit [8..1] algo & operation mode */
+#define FLG_AES BIT(1)
+#define FLG_DES BIT(2)
+#define FLG_TDESBIT(3)
+#define FLG_ECB BIT(4)
+#define FLG_CBC BIT(5)
+#define FLG_CTR BIT(6)
+/* Mode mask = bits [15..0] */
+#define FLG_MODE_MASK   GENMASK(15, 0)
+
+/* Registers */
+#define CRYP_CR 0x
+#define CRYP_SR 0x0004
+#define CRYP_DIN0x0008
+#define CRYP_DOUT   0x000C
+#define CRYP_DMACR  0x0010
+#define CRYP_IMSCR  0x0014
+#define CRYP_RISR   0x0018
+#define CRYP_MISR   0x001C
+#define CRYP_K0LR   0x0020
+#define CRYP_K0RR   0x0024
+#define CRYP_K1LR   0x0028
+#define CRYP_K1RR   0x002C
+#define CRYP_K2LR   0x0030
+#define CRYP_K2RR   0x0034
+#define CRYP_K3LR   0x0038
+#define CRYP_K3RR   0x003C
+#define CRYP_IV0LR  0x0040
+#define CRYP_IV0RR  0x0044
+#define CRYP_IV1LR  0x0048
+#define CRYP_IV1RR  0x004C
+
+/* Registers values */
+#define CR_DEC_NOT_ENC  0x0004
+#define CR_TDES_ECB 0x
+#define CR_TDES_CBC 0x0008
+#define CR_DES_ECB  0x0010
+#define CR_DES_CBC  0x0018
+#define CR_AES_ECB  0x0020
+#define CR_AES_CBC  0x0028
+#define CR_AES_CTR  0x0030
+#define CR_AES_KP   0x0038
+#define CR_AES_UNKNOWN  0x
+#define CR_ALGO_MASK0x00080038
+#define CR_DATA32   0x
+#define CR_DATA16   0x0040
+#define CR_DATA80x0080
+#define CR_DATA10x00C0
+#define CR_KEY128   0x
+#define CR_KEY192   0x0100
+#define CR_KEY256   0x0200
+#define CR_FFLUSH   0x4000
+#define CR_CRYPEN   0x8000
+
+#define SR_BUSY 0x0010
+#define SR_OFNE 0x0004
+
+#define IMSCR_INBIT(0)
+#define IMSCR_OUT   BIT(1)
+
+#define MISR_IN BIT(0)
+#define MISR_OUTBIT(1)
+
+/* Misc */
+#define AES_BLOCK_32(AES_BLOCK_SIZE / sizeof(u32))
+#define _walked_in  (cryp->in_walk.offset - cryp->in_sg->offset)
+#define _walked_out (cryp->out_walk.offset - cryp->out_sg->offset)
+
+struct stm32_cryp_ctx {
+   struc

[PATCH v4 0/2] STM32 CRYP crypto driver

[Fabien Dessenne]

This set of patches adds a new crypto driver for STMicroelectronics stm32 HW.
This drivers uses the crypto API and provides with HW-enabled block cipher
algorithms.

This driver was successfully tested with tcrypt / testmgr.

Changes since v4:
- remove AEAD support from crypto engine as proposed by Herbert : waiting for
  the crypto_engine interface clean up before
  [https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1474434.html]
- remove AES GCM & CCM algorithms

Changes since v3:
- update dt-bindings with Rob Herring remarks

Changes since v2:
- update dt-bindings (interrupts description)
- rebase on STM32 crypto patches (L. Debieve : update CRC32 + add HASH)

Fabien Dessenne (3):
  crypto: engine - permit to enqueue aead_request
  dt-bindings: Document STM32 CRYP bindings
  crypto: stm32 - Support for STM32 CRYP crypto module

Fabien Dessenne (2):
  dt-bindings: Document STM32 CRYP bindings
  crypto: stm32 - Support for STM32 CRYP crypto module

 .../devicetree/bindings/crypto/st,stm32-cryp.txt   |   19 +
 drivers/crypto/stm32/Kconfig   |9 +
 drivers/crypto/stm32/Makefile  |3 +-
 drivers/crypto/stm32/stm32-cryp.c  | 1188 
 4 files changed, 1218 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
 create mode 100644 drivers/crypto/stm32/stm32-cryp.c

-- 
2.7.4

Re: [PATCH v3 1/3] crypto: engine - permit to enqueue aead_request

[Fabien DESSENNE]

On 22/09/17 11:09, Herbert Xu wrote:
> On Fri, Aug 18, 2017 at 11:19:04AM +0200, Fabien Dessenne wrote:
>> The current crypto engine allows ablkcipher_request and ahash_request to
>> be enqueued. Extend this to aead_request.
>>
>> Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
> I'd like to see the crypto_engine interface cleaned up a little
> before we expand it further.  Please refer to
>
> https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1474434.html
>
> Thanks,
It looks like there is no more activity around this "crypto_engine 
interface clean up" task.
This unfortunately has been blocking the introduction of this new STM32 
crypto driver for 3 months now.
Would it make sense to have this driver reviewed first, and then 
reworked (I expect minor update here) when the interface update is ready?

BR

Fabien

Re: [PATCH v3 0/3] STM32 CRYP crypto driver

[Fabien DESSENNE]

Just a gentle ping ... or have I missed out on a reply?


On 18/08/17 11:19, Fabien Dessenne wrote:
> This set of patches adds a new crypto driver for STMicroelectronics stm32 HW.
> This drivers uses the crypto API and provides with HW-enabled AEAD and block
> cipher algorithms.
> It makes use of the crypto engine which is upgraded in order to support AEAD
> requests.
>
> This driver was successfully tested with tcrypt / testmgr.
>
> Changes since v3:
> - update dt-bindings with Rob Herring remarks
>
> Changes since v2:
> - update dt-bindings (interrupts description)
> - rebase on STM32 crypto patches (L. Debieve : update CRC32 + add HASH)
>
> Fabien Dessenne (3):
>crypto: engine - permit to enqueue aead_request
>dt-bindings: Document STM32 CRYP bindings
>crypto: stm32 - Support for STM32 CRYP crypto module
>
>   .../devicetree/bindings/crypto/st,stm32-cryp.txt   |   19 +
>   crypto/crypto_engine.c |  101 +
>   drivers/crypto/stm32/Kconfig   |9 +
>   drivers/crypto/stm32/Makefile  |3 +-
>   drivers/crypto/stm32/stm32-cryp.c  | 1962 
> 
>   include/crypto/engine.h|   16 +
>   6 files changed, 2109 insertions(+), 1 deletion(-)
>   create mode 100644 
> Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
>   create mode 100644 drivers/crypto/stm32/stm32-cryp.c
>

[PATCH v3 3/3] crypto: stm32 - Support for STM32 CRYP crypto module

[Fabien Dessenne]

This module registers block and AEAD cipher algorithms that make use of
the STMicroelectronics STM32 crypto "CRYP1" hardware.
The following algorithms are supported:
- aes: ecb, cbc, ctr, gcm, ccm
- des: ecb, cbc
- tdes: ecb, cbc

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 drivers/crypto/stm32/Kconfig  |9 +
 drivers/crypto/stm32/Makefile |3 +-
 drivers/crypto/stm32/stm32-cryp.c | 1962 +
 3 files changed, 1973 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/stm32/stm32-cryp.c

diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
index 602332e..61ef00b 100644
--- a/drivers/crypto/stm32/Kconfig
+++ b/drivers/crypto/stm32/Kconfig
@@ -18,3 +18,12 @@ config HASH_DEV_STM32
help
   This enables support for the HASH hw accelerator which can be found
  on STMicroelectronics STM32 SOC.
+
+config CRYP_DEV_STM32
+   tristate "Support for STM32 cryp accelerators"
+   depends on ARCH_STM32
+   select CRYPTO_HASH
+   select CRYPTO_ENGINE
+   help
+  This enables support for the CRYP (AES/DES/TDES) hw accelerator which
+ can be found on STMicroelectronics STM32 SOC.
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
index 73cd56c..2c19fc1 100644
--- a/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_CRC_DEV_STM32) += stm32_crc32.o
-obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
\ No newline at end of file
+obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
+obj-$(CONFIG_CRYP_DEV_STM32) += stm32-cryp.o
diff --git a/drivers/crypto/stm32/stm32-cryp.c 
b/drivers/crypto/stm32/stm32-cryp.c
new file mode 100644
index 000..9a02d7c
--- /dev/null
+++ b/drivers/crypto/stm32/stm32-cryp.c
@@ -0,0 +1,1962 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author: Fabien Dessenne <fabien.desse...@st.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRIVER_NAME "stm32-cryp"
+
+/* Bit [0] encrypt / decrypt */
+#define FLG_ENCRYPT BIT(0)
+/* Bit [8..1] algo & operation mode */
+#define FLG_AES BIT(1)
+#define FLG_DES BIT(2)
+#define FLG_TDESBIT(3)
+#define FLG_ECB BIT(4)
+#define FLG_CBC BIT(5)
+#define FLG_CTR BIT(6)
+#define FLG_GCM BIT(7)
+#define FLG_CCM BIT(8)
+/* Mode mask = bits [15..0] */
+#define FLG_MODE_MASK   GENMASK(15, 0)
+/* Bit [31..16] status  */
+#define FLG_CCM_PADDED_WA   BIT(16)
+
+/* Registers */
+#define CRYP_CR 0x
+#define CRYP_SR 0x0004
+#define CRYP_DIN0x0008
+#define CRYP_DOUT   0x000C
+#define CRYP_DMACR  0x0010
+#define CRYP_IMSCR  0x0014
+#define CRYP_RISR   0x0018
+#define CRYP_MISR   0x001C
+#define CRYP_K0LR   0x0020
+#define CRYP_K0RR   0x0024
+#define CRYP_K1LR   0x0028
+#define CRYP_K1RR   0x002C
+#define CRYP_K2LR   0x0030
+#define CRYP_K2RR   0x0034
+#define CRYP_K3LR   0x0038
+#define CRYP_K3RR   0x003C
+#define CRYP_IV0LR  0x0040
+#define CRYP_IV0RR  0x0044
+#define CRYP_IV1LR  0x0048
+#define CRYP_IV1RR  0x004C
+#define CRYP_CSGCMCCM0R 0x0050
+#define CRYP_CSGCM0R0x0070
+
+/* Registers values */
+#define CR_DEC_NOT_ENC  0x0004
+#define CR_TDES_ECB 0x
+#define CR_TDES_CBC 0x0008
+#define CR_DES_ECB  0x0010
+#define CR_DES_CBC  0x0018
+#define CR_AES_ECB  0x0020
+#define CR_AES_CBC  0x0028
+#define CR_AES_CTR  0x0030
+#define CR_AES_KP   0x0038
+#define CR_AES_GCM  0x0008
+#define CR_AES_CCM  0x00080008
+#define CR_AES_UNKNOWN  0x
+#define CR_ALGO_MASK0x00080038
+#define CR_DATA32   0x
+#define CR_DATA16   0x0040
+#define CR_DATA80x0080
+#define CR_DATA10x00C0
+#define CR_KEY128   0x
+#define CR_KEY192   0x0100
+#define CR_KEY256   0x0200
+#define CR_FFLUSH   0x4000
+#define CR_CRYPEN   0x8000
+#define CR_PH_INIT  0x
+#define CR_PH_HEADER0x0001
+#define CR_PH_PAYLOAD   0x0002
+#define CR_PH_FINAL 0x0003
+#define CR_PH_M

[PATCH v3 2/3] dt-bindings: Document STM32 CRYP bindings

[Fabien Dessenne]

Document device tree bindings for the STM32 CRYP.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/crypto/st,stm32-cryp.txt  | 19 +++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt 
b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
new file mode 100644
index 000..970487f
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
@@ -0,0 +1,19 @@
+* STMicroelectronics STM32 CRYP
+
+Required properties:
+- compatible: Should be "st,stm32f756-cryp".
+- reg: The address and length of the peripheral registers space
+- clocks: The input clock of the CRYP instance
+- interrupts: The CRYP interrupt
+
+Optional properties:
+- resets: The input reset of the CRYP instance
+
+Example:
+crypto@5006 {
+   compatible = "st,stm32f756-cryp";
+   reg = <0x5006 0x400>;
+   interrupts = <79>;
+   clocks = < 0 STM32F7_AHB2_CLOCK(CRYP)>;
+   resets = < STM32F7_AHB2_RESET(CRYP)>;
+};
-- 
2.7.4

[PATCH v3 1/3] crypto: engine - permit to enqueue aead_request

[Fabien Dessenne]

The current crypto engine allows ablkcipher_request and ahash_request to
be enqueued. Extend this to aead_request.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 crypto/crypto_engine.c  | 101 
 include/crypto/engine.h |  16 
 2 files changed, 117 insertions(+)

diff --git a/crypto/crypto_engine.c b/crypto/crypto_engine.c
index 61e7c4e..3cdf051 100644
--- a/crypto/crypto_engine.c
+++ b/crypto/crypto_engine.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "internal.h"
@@ -35,6 +36,7 @@ static void crypto_pump_requests(struct crypto_engine *engine,
 {
struct crypto_async_request *async_req, *backlog;
struct ahash_request *hreq;
+   struct aead_request *areq;
struct ablkcipher_request *breq;
unsigned long flags;
bool was_busy = false;
@@ -122,6 +124,22 @@ static void crypto_pump_requests(struct crypto_engine 
*engine,
goto req_err;
}
return;
+   case CRYPTO_ALG_TYPE_AEAD:
+   areq = aead_request_cast(engine->cur_req);
+   if (engine->prepare_aead_request) {
+   ret = engine->prepare_aead_request(engine, areq);
+   if (ret) {
+   pr_err("failed to prepare request: %d\n", ret);
+   goto req_err;
+   }
+   engine->cur_req_prepared = true;
+   }
+   ret = engine->aead_one_request(engine, areq);
+   if (ret) {
+   pr_err("failed to do aead one request from queue\n");
+   goto req_err;
+   }
+   return;
case CRYPTO_ALG_TYPE_ABLKCIPHER:
breq = ablkcipher_request_cast(engine->cur_req);
if (engine->prepare_cipher_request) {
@@ -150,6 +168,10 @@ static void crypto_pump_requests(struct crypto_engine 
*engine,
hreq = ahash_request_cast(engine->cur_req);
crypto_finalize_hash_request(engine, hreq, ret);
break;
+   case CRYPTO_ALG_TYPE_AEAD:
+   areq = aead_request_cast(engine->cur_req);
+   crypto_finalize_aead_request(engine, areq, ret);
+   break;
case CRYPTO_ALG_TYPE_ABLKCIPHER:
breq = ablkcipher_request_cast(engine->cur_req);
crypto_finalize_cipher_request(engine, breq, ret);
@@ -255,6 +277,48 @@ int crypto_transfer_hash_request_to_engine(struct 
crypto_engine *engine,
 EXPORT_SYMBOL_GPL(crypto_transfer_hash_request_to_engine);
 
 /**
+ * crypto_transfer_aead_request - transfer the new request into the
+ * enginequeue
+ * @engine: the hardware engine
+ * @req: the request need to be listed into the engine queue
+ */
+int crypto_transfer_aead_request(struct crypto_engine *engine,
+struct aead_request *req, bool need_pump)
+{
+   unsigned long flags;
+   int ret;
+
+   spin_lock_irqsave(>queue_lock, flags);
+
+   if (!engine->running) {
+   spin_unlock_irqrestore(>queue_lock, flags);
+   return -ESHUTDOWN;
+   }
+
+   ret = aead_enqueue_request((struct aead_queue *)>queue, req);
+
+   if (!engine->busy && need_pump)
+   kthread_queue_work(engine->kworker, >pump_requests);
+
+   spin_unlock_irqrestore(>queue_lock, flags);
+   return ret;
+}
+EXPORT_SYMBOL_GPL(crypto_transfer_aead_request);
+
+/**
+ * crypto_transfer_aead_request_to_engine - transfer one request to list
+ * into the engine queue
+ * @engine: the hardware engine
+ * @req: the request need to be listed into the engine queue
+ */
+int crypto_transfer_aead_request_to_engine(struct crypto_engine *engine,
+  struct aead_request *req)
+{
+   return crypto_transfer_aead_request(engine, req, true);
+}
+EXPORT_SYMBOL_GPL(crypto_transfer_aead_request_to_engine);
+
+/**
  * crypto_finalize_cipher_request - finalize one request if the request is done
  * @engine: the hardware engine
  * @req: the request need to be finalized
@@ -329,6 +393,43 @@ void crypto_finalize_hash_request(struct crypto_engine 
*engine,
 EXPORT_SYMBOL_GPL(crypto_finalize_hash_request);
 
 /**
+ * crypto_finalize_aead_request - finalize one request if the request is done
+ * @engine: the hardware engine
+ * @req: the request need to be finalized
+ * @err: error number
+ */
+void crypto_finalize_aead_request(struct crypto_engine *engine,
+ struct aead_request *req, int err)
+{
+   unsigned long flags;
+   bool finalize_cur_req = false;
+   int ret;
+
+   spin_lock_irqsave(>queue_lock, flags);
+   if (engine->cur_req == >base)
+   

[PATCH v3 0/3] STM32 CRYP crypto driver

[Fabien Dessenne]

This set of patches adds a new crypto driver for STMicroelectronics stm32 HW.
This drivers uses the crypto API and provides with HW-enabled AEAD and block
cipher algorithms.
It makes use of the crypto engine which is upgraded in order to support AEAD
requests.

This driver was successfully tested with tcrypt / testmgr.

Changes since v3:
- update dt-bindings with Rob Herring remarks

Changes since v2:
- update dt-bindings (interrupts description)
- rebase on STM32 crypto patches (L. Debieve : update CRC32 + add HASH)

Fabien Dessenne (3):
  crypto: engine - permit to enqueue aead_request
  dt-bindings: Document STM32 CRYP bindings
  crypto: stm32 - Support for STM32 CRYP crypto module

 .../devicetree/bindings/crypto/st,stm32-cryp.txt   |   19 +
 crypto/crypto_engine.c |  101 +
 drivers/crypto/stm32/Kconfig   |9 +
 drivers/crypto/stm32/Makefile  |3 +-
 drivers/crypto/stm32/stm32-cryp.c  | 1962 
 include/crypto/engine.h|   16 +
 6 files changed, 2109 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
 create mode 100644 drivers/crypto/stm32/stm32-cryp.c

-- 
2.7.4

RE: [PATCH 2/3] crypto: engine - find request type with cra_type

[Fabien DESSENNE]

Hi Corentin,

Since I have just sent a patch to add the support of "aead_request" to crypto 
engine, I am wondering if your proposed change (checking cra_type instead of 
crypto_tfm_alg_type) and mine are compatible.
It looks like they are (assuming we export crypto_aead_type): can you confirm?
BR

Fabien.

>-Original Message-
>From: linux-crypto-ow...@vger.kernel.org [mailto:linux-crypto-
>ow...@vger.kernel.org] On Behalf Of Corentin Labbe
>Sent: lundi 14 août 2017 15:17
>To: herb...@gondor.apana.org.au; da...@davemloft.net
>Cc: linux-crypto@vger.kernel.org; linux-ker...@vger.kernel.org; Corentin Labbe
>
>Subject: [PATCH 2/3] crypto: engine - find request type with cra_type
>
>The current method for finding request type is based on crypto_tfm_alg_type.
>
>But in case of skcipher, it is the same than ablkcipher.
>Using cra_type for this work permits to make the distinction between the two.
>
>Signed-off-by: Corentin Labbe 
>---
> crypto/crypto_engine.c | 19 ---
> 1 file changed, 8 insertions(+), 11 deletions(-)
>
>diff --git a/crypto/crypto_engine.c b/crypto/crypto_engine.c index
>61e7c4e02fd2..74b840749074 100644
>--- a/crypto/crypto_engine.c
>+++ b/crypto/crypto_engine.c
>@@ -38,7 +38,8 @@ static void crypto_pump_requests(struct crypto_engine
>*engine,
>   struct ablkcipher_request *breq;
>   unsigned long flags;
>   bool was_busy = false;
>-  int ret, rtype;
>+  int ret;
>+  const struct crypto_type *cratype;
>
>   spin_lock_irqsave(>queue_lock, flags);
>
>@@ -94,7 +95,7 @@ static void crypto_pump_requests(struct crypto_engine
>*engine,
>
>   spin_unlock_irqrestore(>queue_lock, flags);
>
>-  rtype = crypto_tfm_alg_type(engine->cur_req->tfm);
>+  cratype = engine->cur_req->tfm->__crt_alg->cra_type;
>   /* Until here we get the request need to be encrypted successfully */
>   if (!was_busy && engine->prepare_crypt_hardware) {
>   ret = engine->prepare_crypt_hardware(engine);
>@@ -104,8 +105,7 @@ static void crypto_pump_requests(struct crypto_engine
>*engine,
>   }
>   }
>
>-  switch (rtype) {
>-  case CRYPTO_ALG_TYPE_AHASH:
>+  if (cratype == _ahash_type) {
>   hreq = ahash_request_cast(engine->cur_req);
>   if (engine->prepare_hash_request) {
>   ret = engine->prepare_hash_request(engine, hreq); @@
>-122,7 +122,7 @@ static void crypto_pump_requests(struct crypto_engine
>*engine,
>   goto req_err;
>   }
>   return;
>-  case CRYPTO_ALG_TYPE_ABLKCIPHER:
>+  } else if (cratype == _ablkcipher_type) {
>   breq = ablkcipher_request_cast(engine->cur_req);
>   if (engine->prepare_cipher_request) {
>   ret = engine->prepare_cipher_request(engine, breq);
>@@ -139,21 +139,18 @@ static void crypto_pump_requests(struct
>crypto_engine *engine,
>   goto req_err;
>   }
>   return;
>-  default:
>+  } else {
>   dev_err(engine->dev, "failed to prepare request of unknown
>type\n");
>   return;
>   }
>
> req_err:
>-  switch (rtype) {
>-  case CRYPTO_ALG_TYPE_AHASH:
>+  if (cratype == _ahash_type) {
>   hreq = ahash_request_cast(engine->cur_req);
>   crypto_finalize_hash_request(engine, hreq, ret);
>-  break;
>-  case CRYPTO_ALG_TYPE_ABLKCIPHER:
>+  } else if (cratype == _ablkcipher_type) {
>   breq = ablkcipher_request_cast(engine->cur_req);
>   crypto_finalize_cipher_request(engine, breq, ret);
>-  break;
>   }
>   return;
>
>--
>2.13.0

[PATCH v2 1/3] crypto: engine - permit to enqueue aead_request

[Fabien Dessenne]

The current crypto engine allows ablkcipher_request and ahash_request to
be enqueued. Extend this to aead_request.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 crypto/crypto_engine.c  | 101 
 include/crypto/engine.h |  16 
 2 files changed, 117 insertions(+)

diff --git a/crypto/crypto_engine.c b/crypto/crypto_engine.c
index 61e7c4e..3cdf051 100644
--- a/crypto/crypto_engine.c
+++ b/crypto/crypto_engine.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "internal.h"
@@ -35,6 +36,7 @@ static void crypto_pump_requests(struct crypto_engine *engine,
 {
struct crypto_async_request *async_req, *backlog;
struct ahash_request *hreq;
+   struct aead_request *areq;
struct ablkcipher_request *breq;
unsigned long flags;
bool was_busy = false;
@@ -122,6 +124,22 @@ static void crypto_pump_requests(struct crypto_engine 
*engine,
goto req_err;
}
return;
+   case CRYPTO_ALG_TYPE_AEAD:
+   areq = aead_request_cast(engine->cur_req);
+   if (engine->prepare_aead_request) {
+   ret = engine->prepare_aead_request(engine, areq);
+   if (ret) {
+   pr_err("failed to prepare request: %d\n", ret);
+   goto req_err;
+   }
+   engine->cur_req_prepared = true;
+   }
+   ret = engine->aead_one_request(engine, areq);
+   if (ret) {
+   pr_err("failed to do aead one request from queue\n");
+   goto req_err;
+   }
+   return;
case CRYPTO_ALG_TYPE_ABLKCIPHER:
breq = ablkcipher_request_cast(engine->cur_req);
if (engine->prepare_cipher_request) {
@@ -150,6 +168,10 @@ static void crypto_pump_requests(struct crypto_engine 
*engine,
hreq = ahash_request_cast(engine->cur_req);
crypto_finalize_hash_request(engine, hreq, ret);
break;
+   case CRYPTO_ALG_TYPE_AEAD:
+   areq = aead_request_cast(engine->cur_req);
+   crypto_finalize_aead_request(engine, areq, ret);
+   break;
case CRYPTO_ALG_TYPE_ABLKCIPHER:
breq = ablkcipher_request_cast(engine->cur_req);
crypto_finalize_cipher_request(engine, breq, ret);
@@ -255,6 +277,48 @@ int crypto_transfer_hash_request_to_engine(struct 
crypto_engine *engine,
 EXPORT_SYMBOL_GPL(crypto_transfer_hash_request_to_engine);
 
 /**
+ * crypto_transfer_aead_request - transfer the new request into the
+ * enginequeue
+ * @engine: the hardware engine
+ * @req: the request need to be listed into the engine queue
+ */
+int crypto_transfer_aead_request(struct crypto_engine *engine,
+struct aead_request *req, bool need_pump)
+{
+   unsigned long flags;
+   int ret;
+
+   spin_lock_irqsave(>queue_lock, flags);
+
+   if (!engine->running) {
+   spin_unlock_irqrestore(>queue_lock, flags);
+   return -ESHUTDOWN;
+   }
+
+   ret = aead_enqueue_request((struct aead_queue *)>queue, req);
+
+   if (!engine->busy && need_pump)
+   kthread_queue_work(engine->kworker, >pump_requests);
+
+   spin_unlock_irqrestore(>queue_lock, flags);
+   return ret;
+}
+EXPORT_SYMBOL_GPL(crypto_transfer_aead_request);
+
+/**
+ * crypto_transfer_aead_request_to_engine - transfer one request to list
+ * into the engine queue
+ * @engine: the hardware engine
+ * @req: the request need to be listed into the engine queue
+ */
+int crypto_transfer_aead_request_to_engine(struct crypto_engine *engine,
+  struct aead_request *req)
+{
+   return crypto_transfer_aead_request(engine, req, true);
+}
+EXPORT_SYMBOL_GPL(crypto_transfer_aead_request_to_engine);
+
+/**
  * crypto_finalize_cipher_request - finalize one request if the request is done
  * @engine: the hardware engine
  * @req: the request need to be finalized
@@ -329,6 +393,43 @@ void crypto_finalize_hash_request(struct crypto_engine 
*engine,
 EXPORT_SYMBOL_GPL(crypto_finalize_hash_request);
 
 /**
+ * crypto_finalize_aead_request - finalize one request if the request is done
+ * @engine: the hardware engine
+ * @req: the request need to be finalized
+ * @err: error number
+ */
+void crypto_finalize_aead_request(struct crypto_engine *engine,
+ struct aead_request *req, int err)
+{
+   unsigned long flags;
+   bool finalize_cur_req = false;
+   int ret;
+
+   spin_lock_irqsave(>queue_lock, flags);
+   if (engine->cur_req == >base)
+   

[PATCH v2 3/3] crypto: stm32 - Support for STM32 CRYP crypto module

[Fabien Dessenne]

This module registers block and AEAD cipher algorithms that make use of
the STMicroelectronics STM32 crypto "CRYP1" hardware.
The following algorithms are supported:
- aes: ecb, cbc, ctr, gcm, ccm
- des: ecb, cbc
- tdes: ecb, cbc

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 drivers/crypto/stm32/Kconfig  |9 +
 drivers/crypto/stm32/Makefile |3 +-
 drivers/crypto/stm32/stm32-cryp.c | 1962 +
 3 files changed, 1973 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/stm32/stm32-cryp.c

diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
index 602332e..61ef00b 100644
--- a/drivers/crypto/stm32/Kconfig
+++ b/drivers/crypto/stm32/Kconfig
@@ -18,3 +18,12 @@ config HASH_DEV_STM32
help
   This enables support for the HASH hw accelerator which can be found
  on STMicroelectronics STM32 SOC.
+
+config CRYP_DEV_STM32
+   tristate "Support for STM32 cryp accelerators"
+   depends on ARCH_STM32
+   select CRYPTO_HASH
+   select CRYPTO_ENGINE
+   help
+  This enables support for the CRYP (AES/DES/TDES) hw accelerator which
+ can be found on STMicroelectronics STM32 SOC.
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
index 73cd56c..2c19fc1 100644
--- a/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_CRC_DEV_STM32) += stm32_crc32.o
-obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
\ No newline at end of file
+obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
+obj-$(CONFIG_CRYP_DEV_STM32) += stm32-cryp.o
diff --git a/drivers/crypto/stm32/stm32-cryp.c 
b/drivers/crypto/stm32/stm32-cryp.c
new file mode 100644
index 000..9a02d7c
--- /dev/null
+++ b/drivers/crypto/stm32/stm32-cryp.c
@@ -0,0 +1,1962 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author: Fabien Dessenne <fabien.desse...@st.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRIVER_NAME "stm32-cryp"
+
+/* Bit [0] encrypt / decrypt */
+#define FLG_ENCRYPT BIT(0)
+/* Bit [8..1] algo & operation mode */
+#define FLG_AES BIT(1)
+#define FLG_DES BIT(2)
+#define FLG_TDESBIT(3)
+#define FLG_ECB BIT(4)
+#define FLG_CBC BIT(5)
+#define FLG_CTR BIT(6)
+#define FLG_GCM BIT(7)
+#define FLG_CCM BIT(8)
+/* Mode mask = bits [15..0] */
+#define FLG_MODE_MASK   GENMASK(15, 0)
+/* Bit [31..16] status  */
+#define FLG_CCM_PADDED_WA   BIT(16)
+
+/* Registers */
+#define CRYP_CR 0x
+#define CRYP_SR 0x0004
+#define CRYP_DIN0x0008
+#define CRYP_DOUT   0x000C
+#define CRYP_DMACR  0x0010
+#define CRYP_IMSCR  0x0014
+#define CRYP_RISR   0x0018
+#define CRYP_MISR   0x001C
+#define CRYP_K0LR   0x0020
+#define CRYP_K0RR   0x0024
+#define CRYP_K1LR   0x0028
+#define CRYP_K1RR   0x002C
+#define CRYP_K2LR   0x0030
+#define CRYP_K2RR   0x0034
+#define CRYP_K3LR   0x0038
+#define CRYP_K3RR   0x003C
+#define CRYP_IV0LR  0x0040
+#define CRYP_IV0RR  0x0044
+#define CRYP_IV1LR  0x0048
+#define CRYP_IV1RR  0x004C
+#define CRYP_CSGCMCCM0R 0x0050
+#define CRYP_CSGCM0R0x0070
+
+/* Registers values */
+#define CR_DEC_NOT_ENC  0x0004
+#define CR_TDES_ECB 0x
+#define CR_TDES_CBC 0x0008
+#define CR_DES_ECB  0x0010
+#define CR_DES_CBC  0x0018
+#define CR_AES_ECB  0x0020
+#define CR_AES_CBC  0x0028
+#define CR_AES_CTR  0x0030
+#define CR_AES_KP   0x0038
+#define CR_AES_GCM  0x0008
+#define CR_AES_CCM  0x00080008
+#define CR_AES_UNKNOWN  0x
+#define CR_ALGO_MASK0x00080038
+#define CR_DATA32   0x
+#define CR_DATA16   0x0040
+#define CR_DATA80x0080
+#define CR_DATA10x00C0
+#define CR_KEY128   0x
+#define CR_KEY192   0x0100
+#define CR_KEY256   0x0200
+#define CR_FFLUSH   0x4000
+#define CR_CRYPEN   0x8000
+#define CR_PH_INIT  0x
+#define CR_PH_HEADER0x0001
+#define CR_PH_PAYLOAD   0x0002
+#define CR_PH_FINAL 0x0003
+#define CR_PH_M

[PATCH v2 2/3] dt-bindings: Document STM32 CRYP bindings

[Fabien Dessenne]

Document device tree bindings for the STM32 CRYP.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 .../devicetree/bindings/crypto/st,stm32-cryp.txt | 20 
 1 file changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt 
b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
new file mode 100644
index 000..7c6d599
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
@@ -0,0 +1,20 @@
+* STMicroelectronics STM32 CRYP
+
+Required properties:
+- compatible: Should be "st,stm32f756-cryp".
+- reg: The address and length of the peripheral registers space
+- clocks: The input clock of the CRYP instance
+- interrupts: The CRYP interrupt
+
+Optional properties:
+- resets: The input reset of the CRYP instance
+
+Example:
+cryp1: cryp@5006 {
+   compatible = "st,stm32f756-cryp";
+   reg = <0x5006 0x400>;
+   interrupts = <79>;
+   clocks = < 0 STM32F7_AHB2_CLOCK(CRYP)>;
+   resets = < STM32F7_AHB2_RESET(CRYP)>;
+   status = "disabled";
+};
-- 
2.7.4

[PATCH v2 0/3] STM32 CRYP crypto driver

[Fabien Dessenne]

This set of patches adds a new crypto driver for STMicroelectronics stm32 HW.
This drivers uses the crypto API and provides with HW-enabled AEAD and block
cipher algorithms.
It makes use of the crypto engine which is upgraded in order to support AEAD
requests.

This driver was successfully tested with tcrypt / testmgr.

Changes since v2:
- update dt-bindings (interrupts description)
- rebase on STM32 crypto patches (L. Debieve : update CRC32 + add HASH)

Fabien Dessenne (3):
  crypto: engine - permit to enqueue aead_request
  dt-bindings: Document STM32 CRYP bindings
  crypto: stm32 - Support for STM32 CRYP crypto module

 .../devicetree/bindings/crypto/st,stm32-cryp.txt   |   20 +
 crypto/crypto_engine.c |  101 +
 drivers/crypto/stm32/Kconfig   |9 +
 drivers/crypto/stm32/Makefile  |3 +-
 drivers/crypto/stm32/stm32-cryp.c  | 1962 
 include/crypto/engine.h|   16 +
 6 files changed, 2110 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
 create mode 100644 drivers/crypto/stm32/stm32-cryp.c

-- 
2.7.4

[PATCH 3/3] crypto: stm32 - Support for STM32 CRYP crypto module

[Fabien Dessenne]

This module registers block and AEAD cipher algorithms that make use of
the STMicroelectronics STM32 crypto "CRYP1" hardware.
The following algorithms are supported:
- aes: ecb, cbc, ctr, gcm, ccm
- des: ecb, cbc
- tdes: ecb, cbc

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 drivers/crypto/stm32/Kconfig  |9 +
 drivers/crypto/stm32/Makefile |1 +
 drivers/crypto/stm32/stm32-cryp.c | 1962 +
 3 files changed, 1972 insertions(+)
 create mode 100644 drivers/crypto/stm32/stm32-cryp.c

diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
index 09b4ec8..c89d651 100644
--- a/drivers/crypto/stm32/Kconfig
+++ b/drivers/crypto/stm32/Kconfig
@@ -5,3 +5,12 @@ config CRYPTO_DEV_STM32
help
   This enables support for the CRC32 hw accelerator which can be found
  on STMicroelectronis STM32 SOC.
+
+config CRYP_DEV_STM32
+   tristate "Support for STM32 cryp accelerators"
+   depends on ARCH_STM32
+   select CRYPTO_HASH
+   select CRYPTO_ENGINE
+   help
+  This enables support for the CRYP (AES/DES/TDES) hw accelerator which
+ can be found on STMicroelectronics STM32 SOC.
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
index 73b4c6e..06b51c6 100644
--- a/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32_cryp.o
 stm32_cryp-objs := stm32_crc32.o
+obj-$(CONFIG_CRYP_DEV_STM32) += stm32-cryp.o
diff --git a/drivers/crypto/stm32/stm32-cryp.c 
b/drivers/crypto/stm32/stm32-cryp.c
new file mode 100644
index 000..9a02d7c
--- /dev/null
+++ b/drivers/crypto/stm32/stm32-cryp.c
@@ -0,0 +1,1962 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author: Fabien Dessenne <fabien.desse...@st.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRIVER_NAME "stm32-cryp"
+
+/* Bit [0] encrypt / decrypt */
+#define FLG_ENCRYPT BIT(0)
+/* Bit [8..1] algo & operation mode */
+#define FLG_AES BIT(1)
+#define FLG_DES BIT(2)
+#define FLG_TDESBIT(3)
+#define FLG_ECB BIT(4)
+#define FLG_CBC BIT(5)
+#define FLG_CTR BIT(6)
+#define FLG_GCM BIT(7)
+#define FLG_CCM BIT(8)
+/* Mode mask = bits [15..0] */
+#define FLG_MODE_MASK   GENMASK(15, 0)
+/* Bit [31..16] status  */
+#define FLG_CCM_PADDED_WA   BIT(16)
+
+/* Registers */
+#define CRYP_CR 0x
+#define CRYP_SR 0x0004
+#define CRYP_DIN0x0008
+#define CRYP_DOUT   0x000C
+#define CRYP_DMACR  0x0010
+#define CRYP_IMSCR  0x0014
+#define CRYP_RISR   0x0018
+#define CRYP_MISR   0x001C
+#define CRYP_K0LR   0x0020
+#define CRYP_K0RR   0x0024
+#define CRYP_K1LR   0x0028
+#define CRYP_K1RR   0x002C
+#define CRYP_K2LR   0x0030
+#define CRYP_K2RR   0x0034
+#define CRYP_K3LR   0x0038
+#define CRYP_K3RR   0x003C
+#define CRYP_IV0LR  0x0040
+#define CRYP_IV0RR  0x0044
+#define CRYP_IV1LR  0x0048
+#define CRYP_IV1RR  0x004C
+#define CRYP_CSGCMCCM0R 0x0050
+#define CRYP_CSGCM0R0x0070
+
+/* Registers values */
+#define CR_DEC_NOT_ENC  0x0004
+#define CR_TDES_ECB 0x
+#define CR_TDES_CBC 0x0008
+#define CR_DES_ECB  0x0010
+#define CR_DES_CBC  0x0018
+#define CR_AES_ECB  0x0020
+#define CR_AES_CBC  0x0028
+#define CR_AES_CTR  0x0030
+#define CR_AES_KP   0x0038
+#define CR_AES_GCM  0x0008
+#define CR_AES_CCM  0x00080008
+#define CR_AES_UNKNOWN  0x
+#define CR_ALGO_MASK0x00080038
+#define CR_DATA32   0x
+#define CR_DATA16   0x0040
+#define CR_DATA80x0080
+#define CR_DATA10x00C0
+#define CR_KEY128   0x
+#define CR_KEY192   0x0100
+#define CR_KEY256   0x0200
+#define CR_FFLUSH   0x4000
+#define CR_CRYPEN   0x8000
+#define CR_PH_INIT  0x
+#define CR_PH_HEADER0x0001
+#define CR_PH_PAYLOAD   0x0002
+#define CR_PH_FINAL 0x0003
+#define CR_PH_MASK  0x0003
+
+#define SR_BUSY 0x0010
+#define SR_OFNE 

[PATCH 2/3] dt-bindings: Document STM32 CRYP bindings

[Fabien Dessenne]

Document device tree bindings for the STM32 CRYP.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 .../devicetree/bindings/crypto/st,stm32-cryp.txt | 20 
 1 file changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt 
b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
new file mode 100644
index 000..f631c37
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
@@ -0,0 +1,20 @@
+* STMicroelectronics STM32 CRYP
+
+Required properties:
+- compatible: Should be "st,stm32f756-cryp".
+- reg: The address and length of the peripheral registers space
+- clocks: The input clock of the CRYP instance
+- interrupts: The CRYP interrupts
+
+Optional properties:
+- resets: The input reset of the CRYP instance
+
+Example:
+cryp1: cryp@5006 {
+   compatible = "st,stm32f756-cryp";
+   reg = <0x5006 0x400>;
+   interrupts = <79>;
+   clocks = < 0 STM32F7_AHB2_CLOCK(CRYP)>;
+   resets = < STM32F7_AHB2_RESET(CRYP)>;
+   status = "disabled";
+};
-- 
2.7.4

[PATCH 1/3] crypto: engine - permit to enqueue aead_request

[Fabien Dessenne]

The current crypto engine allows ablkcipher_request and ahash_request to
be enqueued. Extend this to aead_request.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 crypto/crypto_engine.c  | 101 
 include/crypto/engine.h |  16 
 2 files changed, 117 insertions(+)

diff --git a/crypto/crypto_engine.c b/crypto/crypto_engine.c
index 727bd5c..01701ac 100644
--- a/crypto/crypto_engine.c
+++ b/crypto/crypto_engine.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "internal.h"
@@ -35,6 +36,7 @@ static void crypto_pump_requests(struct crypto_engine *engine,
 {
struct crypto_async_request *async_req, *backlog;
struct ahash_request *hreq;
+   struct aead_request *areq;
struct ablkcipher_request *breq;
unsigned long flags;
bool was_busy = false;
@@ -121,6 +123,22 @@ static void crypto_pump_requests(struct crypto_engine 
*engine,
goto req_err;
}
return;
+   case CRYPTO_ALG_TYPE_AEAD:
+   areq = aead_request_cast(engine->cur_req);
+   if (engine->prepare_aead_request) {
+   ret = engine->prepare_aead_request(engine, areq);
+   if (ret) {
+   pr_err("failed to prepare request: %d\n", ret);
+   goto req_err;
+   }
+   engine->cur_req_prepared = true;
+   }
+   ret = engine->aead_one_request(engine, areq);
+   if (ret) {
+   pr_err("failed to do aead one request from queue\n");
+   goto req_err;
+   }
+   return;
case CRYPTO_ALG_TYPE_ABLKCIPHER:
breq = ablkcipher_request_cast(engine->cur_req);
if (engine->prepare_cipher_request) {
@@ -148,6 +166,10 @@ static void crypto_pump_requests(struct crypto_engine 
*engine,
hreq = ahash_request_cast(engine->cur_req);
crypto_finalize_hash_request(engine, hreq, ret);
break;
+   case CRYPTO_ALG_TYPE_AEAD:
+   areq = aead_request_cast(engine->cur_req);
+   crypto_finalize_aead_request(engine, areq, ret);
+   break;
case CRYPTO_ALG_TYPE_ABLKCIPHER:
breq = ablkcipher_request_cast(engine->cur_req);
crypto_finalize_cipher_request(engine, breq, ret);
@@ -253,6 +275,48 @@ int crypto_transfer_hash_request_to_engine(struct 
crypto_engine *engine,
 EXPORT_SYMBOL_GPL(crypto_transfer_hash_request_to_engine);
 
 /**
+ * crypto_transfer_aead_request - transfer the new request into the
+ * enginequeue
+ * @engine: the hardware engine
+ * @req: the request need to be listed into the engine queue
+ */
+int crypto_transfer_aead_request(struct crypto_engine *engine,
+struct aead_request *req, bool need_pump)
+{
+   unsigned long flags;
+   int ret;
+
+   spin_lock_irqsave(>queue_lock, flags);
+
+   if (!engine->running) {
+   spin_unlock_irqrestore(>queue_lock, flags);
+   return -ESHUTDOWN;
+   }
+
+   ret = aead_enqueue_request((struct aead_queue *)>queue, req);
+
+   if (!engine->busy && need_pump)
+   kthread_queue_work(engine->kworker, >pump_requests);
+
+   spin_unlock_irqrestore(>queue_lock, flags);
+   return ret;
+}
+EXPORT_SYMBOL_GPL(crypto_transfer_aead_request);
+
+/**
+ * crypto_transfer_aead_request_to_engine - transfer one request to list
+ * into the engine queue
+ * @engine: the hardware engine
+ * @req: the request need to be listed into the engine queue
+ */
+int crypto_transfer_aead_request_to_engine(struct crypto_engine *engine,
+  struct aead_request *req)
+{
+   return crypto_transfer_aead_request(engine, req, true);
+}
+EXPORT_SYMBOL_GPL(crypto_transfer_aead_request_to_engine);
+
+/**
  * crypto_finalize_cipher_request - finalize one request if the request is done
  * @engine: the hardware engine
  * @req: the request need to be finalized
@@ -327,6 +391,43 @@ void crypto_finalize_hash_request(struct crypto_engine 
*engine,
 EXPORT_SYMBOL_GPL(crypto_finalize_hash_request);
 
 /**
+ * crypto_finalize_aead_request - finalize one request if the request is done
+ * @engine: the hardware engine
+ * @req: the request need to be finalized
+ * @err: error number
+ */
+void crypto_finalize_aead_request(struct crypto_engine *engine,
+ struct aead_request *req, int err)
+{
+   unsigned long flags;
+   bool finalize_cur_req = false;
+   int ret;
+
+   spin_lock_irqsave(>queue_lock, flags);
+   if (engine->cur_req == >base)
+   

[PATCH 0/3] STM32 CRYP crypto driver

[Fabien Dessenne]

This set of patches adds a new crypto driver for STMicroelectronics stm32 HW.
This drivers uses the crypto API and provides with HW-enabled AEAD and block
cipher algorithms.
It makes use of the crypto engine which is upgraded in order to support AEAD
requests.

This driver was successfully tested with tcrypt / testmgr.

Note:
Since two other set of patches (update of STM32 CRC32 and addition of STM32
HASH) are being proposed, it may happen that there are some minor conflicts in
'Kconfig' and 'Makefile'. In that case, I will fix the issue in due course.

Fabien Dessenne (3):
  crypto: engine - permit to enqueue aead_request
  dt-bindings: Document STM32 CRYP bindings
  crypto: stm32 - Support for STM32 CRYP crypto module

 .../devicetree/bindings/crypto/st,stm32-cryp.txt   |   20 +
 crypto/crypto_engine.c |  101 +
 drivers/crypto/stm32/Kconfig   |9 +
 drivers/crypto/stm32/Makefile  |1 +
 drivers/crypto/stm32/stm32-cryp.c  | 1962 
 include/crypto/engine.h|   16 +
 6 files changed, 2109 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt
 create mode 100644 drivers/crypto/stm32/stm32-cryp.c

-- 
2.7.4

Re: [PATCH v3 2/5] crypto : stm32 - Add STM32F4 CRC32 support

[Fabien DESSENNE]

loc(dev, sizeof(*crc), GFP_KERNEL);
>   if (!crc)
> @@ -269,13 +303,26 @@ static int stm32_crc_probe(struct platform_device *pdev)
>   return ret;
>   }
>   
> + /* set key, poly and reverse support if device is of F7 series */
> + if (of_device_is_compatible(crc->dev->of_node, "st,stm32f7-crc")) {
> + crc->key_support = true;
> + crc->poly_support = true;
> + crc->reverse_support = true;
> + }
> +
>   platform_set_drvdata(pdev, crc);
>   
>   spin_lock(_list.lock);
>   list_add(>list, _list.dev_list);
>   spin_unlock(_list.lock);
>   
> - ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
> + /* For F4 series only CRC32 algorithm will be used */
> +     if (of_device_is_compatible(crc->dev->of_node, "st,stm32f4-crc"))
> + algs_size = 1;
> + else
> + algs_size = ARRAY_SIZE(algs);
> +
> + ret = crypto_register_shashes(algs, algs_size);
>   if (ret) {
>   dev_err(dev, "Failed to register\n");
>   clk_disable_unprepare(crc->clk);
> @@ -304,6 +351,7 @@ static int stm32_crc_remove(struct platform_device *pdev)
>   
>   static const struct of_device_id stm32_dt_ids[] = {
>   { .compatible = "st,stm32f7-crc", },
> + { .compatible = "st,stm32f4-crc", },
>   {},
>   };
>   MODULE_DEVICE_TABLE(of, stm32_dt_ids);
Reviewed-by: Fabien Dessenne <fabien.desse...@st.com>

Re: [PATCH v2 2/5] crypto: stm32 - Support for STM32 CRC32 crypto module

[Fabien DESSENNE]

On 24/03/17 05:28, PrasannaKumar Muralidharan wrote:
> On 21 March 2017 at 20:43, Fabien Dessenne <fabien.desse...@st.com> wrote:
>> This module registers a CRC32 ("Ethernet") and a CRC32C (Castagnoli)
>> algorithm that make use of the STMicroelectronics STM32 crypto hardware.
>>
>> Theses algorithms are compatible with the little-endian generic ones.
>> Both algorithms use ~0 as default seed (key).
>> With CRC32C the output is xored with ~0.
>>
>> Using TCRYPT CRC32C speed test, this shows up to 900% speedup compared
>> to the crc32c-generic algorithm.
> Comparing with crc3c-generic alogrithm does not sound like a good
> metric for someone who has to decide between hw crypto or not.
> Wouldn't it be better if the comparison is between crc32 using NEON
> with hw crypto module? It will help in choosing between hw crypto or
> arch optimised crc routiene.

The STM32 microcontrollers are based on ARM Cortex-M7 (or older core) 
that do not have NEON support.
Moreover, the purpose of this introduction is not to provide with a 
(full) benchmark. It just gives a hint of the HW performance.

>> Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
>> ---
>>   drivers/crypto/Kconfig |   2 +
>>   drivers/crypto/Makefile|   1 +
>>   drivers/crypto/stm32/Kconfig   |   8 +
>>   drivers/crypto/stm32/Makefile  |   2 +
>>   drivers/crypto/stm32/stm32_crc32.c | 324 
>> +
>>   5 files changed, 337 insertions(+)
>>   create mode 100644 drivers/crypto/stm32/Kconfig
>>   create mode 100644 drivers/crypto/stm32/Makefile
>>   create mode 100644 drivers/crypto/stm32/stm32_crc32.c
>>
>> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
>> index 473d312..922b323 100644
>> --- a/drivers/crypto/Kconfig
>> +++ b/drivers/crypto/Kconfig
>> @@ -619,4 +619,6 @@ config CRYPTO_DEV_BCM_SPU
>>Secure Processing Unit (SPU). The SPU driver registers ablkcipher,
>>ahash, and aead algorithms with the kernel cryptographic API.
>>
>> +source "drivers/crypto/stm32/Kconfig"
>> +
>>   endif # CRYPTO_HW
>> diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
>> index 7396094..95bf2f9 100644
>> --- a/drivers/crypto/Makefile
>> +++ b/drivers/crypto/Makefile
>> @@ -30,6 +30,7 @@ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
>>   obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
>>   obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
>>   obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
>> +obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32/
>>   obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
>>   obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
>>   obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
>> diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
>> new file mode 100644
>> index 000..792335b
>> --- /dev/null
>> +++ b/drivers/crypto/stm32/Kconfig
>> @@ -0,0 +1,8 @@
>> +config CRYPTO_DEV_STM32
>> +   tristate "Support for STM32 crypto accelerators"
>> +   depends on ARCH_STM32
>> +   select CRYPTO_HASH
>> +   help
>> +  This enables support for the CRC32 hw accelerator which can be 
>> found
>> + on STMicroelectronis STM32 SOC.
>> +
>> diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
>> new file mode 100644
>> index 000..73b4c6e
>> --- /dev/null
>> +++ b/drivers/crypto/stm32/Makefile
>> @@ -0,0 +1,2 @@
>> +obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32_cryp.o
>> +stm32_cryp-objs := stm32_crc32.o
>> diff --git a/drivers/crypto/stm32/stm32_crc32.c 
>> b/drivers/crypto/stm32/stm32_crc32.c
>> new file mode 100644
>> index 000..7652822
>> --- /dev/null
>> +++ b/drivers/crypto/stm32/stm32_crc32.c
>> @@ -0,0 +1,324 @@
>> +/*
>> + * Copyright (C) STMicroelectronics SA 2017
>> + * Author: Fabien Dessenne <fabien.desse...@st.com>
>> + * License terms:  GNU General Public License (GPL), version 2
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include 
>> +
>> +#include 
>> +
>> +#define DRIVER_NAME "stm32-crc32"
>> +#define CHKSUM_DIGEST_SIZE  4
>> +#define CHKSUM_BLOCK_SIZE   1
>> +
>> +/* Registers */
>> +#define CRC_DR  0x
>> +#define CRC_CR  0x0008
>> +#define CRC_INIT0x0010
>> +#define CRC_POL 0x0014
>> +
>> 

[PATCH v2 5/5] ARM: configs: stm32: Add crypto support

[Fabien Dessenne]

Add STM32 crypto support in stm32_defconfig file.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 arch/arm/configs/stm32_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index a9d8e3c..03437f8 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -75,5 +75,7 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_FTRACE is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_DEV_STM32=y
 CONFIG_CRC_ITU_T=y
 CONFIG_CRC7=y
-- 
2.7.4

[PATCH v2 3/5] ARM: dts: stm32: Add CRC support to stm32f746

[Fabien Dessenne]

Add CRC (CRC32 crypto) support to stm32f746.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 arch/arm/boot/dts/stm32f746.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index f321ffe..755fb92 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -289,6 +289,13 @@
};
};
 
+   crc: crc@40023000 {
+   compatible = "st,stm32f7-crc";
+   reg = <0x40023000 0x400>;
+   clocks = < 0 12>;
+   status = "disabled";
+   };
+
rcc: rcc@40023800 {
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
-- 
2.7.4

[PATCH v2 4/5] ARM: dts: stm32: enable CRC on stm32746g-eval board

[Fabien Dessenne]

Enable the CRC (CRC32 crypto) on stm32746g-eval board

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 arch/arm/boot/dts/stm32746g-eval.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/stm32746g-eval.dts 
b/arch/arm/boot/dts/stm32746g-eval.dts
index aa03fac..0dc18a0 100644
--- a/arch/arm/boot/dts/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
@@ -89,6 +89,10 @@
clock-frequency = <2500>;
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-0 = <_pins_a>;
pinctrl-names = "default";
-- 
2.7.4

[PATCH v2 2/5] crypto: stm32 - Support for STM32 CRC32 crypto module

[Fabien Dessenne]

This module registers a CRC32 ("Ethernet") and a CRC32C (Castagnoli)
algorithm that make use of the STMicroelectronics STM32 crypto hardware.

Theses algorithms are compatible with the little-endian generic ones.
Both algorithms use ~0 as default seed (key).
With CRC32C the output is xored with ~0.

Using TCRYPT CRC32C speed test, this shows up to 900% speedup compared
to the crc32c-generic algorithm.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 drivers/crypto/Kconfig |   2 +
 drivers/crypto/Makefile|   1 +
 drivers/crypto/stm32/Kconfig   |   8 +
 drivers/crypto/stm32/Makefile  |   2 +
 drivers/crypto/stm32/stm32_crc32.c | 324 +
 5 files changed, 337 insertions(+)
 create mode 100644 drivers/crypto/stm32/Kconfig
 create mode 100644 drivers/crypto/stm32/Makefile
 create mode 100644 drivers/crypto/stm32/stm32_crc32.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 473d312..922b323 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -619,4 +619,6 @@ config CRYPTO_DEV_BCM_SPU
  Secure Processing Unit (SPU). The SPU driver registers ablkcipher,
  ahash, and aead algorithms with the kernel cryptographic API.
 
+source "drivers/crypto/stm32/Kconfig"
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 7396094..95bf2f9 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
 obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
 obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
 obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
+obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32/
 obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
 obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
 obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
new file mode 100644
index 000..792335b
--- /dev/null
+++ b/drivers/crypto/stm32/Kconfig
@@ -0,0 +1,8 @@
+config CRYPTO_DEV_STM32
+   tristate "Support for STM32 crypto accelerators"
+   depends on ARCH_STM32
+   select CRYPTO_HASH
+   help
+  This enables support for the CRC32 hw accelerator which can be found
+ on STMicroelectronis STM32 SOC.
+
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
new file mode 100644
index 000..73b4c6e
--- /dev/null
+++ b/drivers/crypto/stm32/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32_cryp.o
+stm32_cryp-objs := stm32_crc32.o
diff --git a/drivers/crypto/stm32/stm32_crc32.c 
b/drivers/crypto/stm32/stm32_crc32.c
new file mode 100644
index 000..7652822
--- /dev/null
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author: Fabien Dessenne <fabien.desse...@st.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+
+#define DRIVER_NAME "stm32-crc32"
+#define CHKSUM_DIGEST_SIZE  4
+#define CHKSUM_BLOCK_SIZE   1
+
+/* Registers */
+#define CRC_DR  0x
+#define CRC_CR  0x0008
+#define CRC_INIT0x0010
+#define CRC_POL 0x0014
+
+/* Registers values */
+#define CRC_CR_RESETBIT(0)
+#define CRC_CR_REVERSE  (BIT(7) | BIT(6) | BIT(5))
+#define CRC_INIT_DEFAULT0x
+
+/* Polynomial reversed */
+#define POLY_CRC32  0xEDB88320
+#define POLY_CRC32C 0x82F63B78
+
+struct stm32_crc {
+   struct list_head list;
+   struct device*dev;
+   void __iomem *regs;
+   struct clk   *clk;
+   u8   pending_data[sizeof(u32)];
+   size_t   nb_pending_bytes;
+};
+
+struct stm32_crc_list {
+   struct list_head dev_list;
+   spinlock_t   lock; /* protect dev_list */
+};
+
+static struct stm32_crc_list crc_list = {
+   .dev_list = LIST_HEAD_INIT(crc_list.dev_list),
+   .lock = __SPIN_LOCK_UNLOCKED(crc_list.lock),
+};
+
+struct stm32_crc_ctx {
+   u32 key;
+   u32 poly;
+};
+
+struct stm32_crc_desc_ctx {
+   u32partial; /* crc32c: partial in first 4 bytes of that struct */
+   struct stm32_crc *crc;
+};
+
+static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
+{
+   struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
+
+   mctx->key = CRC_INIT_DEFAULT;
+   mctx->poly = POLY_CRC32;
+   return 0;
+}
+
+static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
+{
+   struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
+
+   mctx->key = CRC_INIT_DEFAULT;
+   mctx->poly = POLY_CRC32C;
+   return 0;
+}
+
+static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key,
+   unsigned int keylen)
+{
+   struct stm32_crc_ctx *

[PATCH v2 1/5] dt-bindings: Document STM32 CRC bindings

[Fabien Dessenne]

Document device tree bindings for the STM32 CRC (crypto CRC32)

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 .../devicetree/bindings/crypto/st,stm32-crc.txt  | 16 
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-crc.txt

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt 
b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
new file mode 100644
index 000..3ba92a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
@@ -0,0 +1,16 @@
+* STMicroelectronics STM32 CRC
+
+Required properties:
+- compatible: Should be "st,stm32f7-crc".
+- reg: The address and length of the peripheral registers space
+- clocks: The input clock of the CRC instance
+
+Optional properties: none
+
+Example:
+
+crc: crc@40023000 {
+   compatible = "st,stm32f7-crc";
+   reg = <0x40023000 0x400>;
+   clocks = < 0 12>;
+};
-- 
2.7.4

[PATCH v2 0/5] STM32 CRC crypto driver

[Fabien Dessenne]

This set of patches adds a new crypto driver for STMicroelectronics stm32f746.
The drivers uses the crypto API and provides with an HW-enabled CRC32 algorithm.
It was developed and tested (tcrypt / testmgr) on evaluation board stm32746g.

v2 changes:
- remove useless check of crc / crc->clk
- enable crypto in stm32 defconfig
- typo fix in dt-bindings

Fabien Dessenne (5):
  dt-bindings: Document STM32 CRC bindings
  crypto: stm32 - Support for STM32 CRC32 crypto module
  ARM: dts: stm32: Add CRC support to stm32f746
  ARM: dts: stm32: enable CRC on stm32746g-eval board
  ARM: configs: stm32: Add crypto support

 .../devicetree/bindings/crypto/st,stm32-crc.txt|  16 +
 arch/arm/boot/dts/stm32746g-eval.dts   |   4 +
 arch/arm/boot/dts/stm32f746.dtsi   |   7 +
 arch/arm/configs/stm32_defconfig   |   2 +
 drivers/crypto/Kconfig |   2 +
 drivers/crypto/Makefile|   1 +
 drivers/crypto/stm32/Kconfig   |   8 +
 drivers/crypto/stm32/Makefile  |   2 +
 drivers/crypto/stm32/stm32_crc32.c | 324 +
 9 files changed, 366 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
 create mode 100644 drivers/crypto/stm32/Kconfig
 create mode 100644 drivers/crypto/stm32/Makefile
 create mode 100644 drivers/crypto/stm32/stm32_crc32.c

-- 
2.7.4

[PATCH 4/4] ARM: dts: stm32: enable CRC on stm32746g-eval board

[Fabien Dessenne]

Enable the CRC (CRC32 crypto) on stm32746g-eval board

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 arch/arm/boot/dts/stm32746g-eval.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/stm32746g-eval.dts 
b/arch/arm/boot/dts/stm32746g-eval.dts
index aa03fac..0dc18a0 100644
--- a/arch/arm/boot/dts/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
@@ -89,6 +89,10 @@
clock-frequency = <2500>;
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-0 = <_pins_a>;
pinctrl-names = "default";
-- 
2.7.4

[PATCH 1/4] dt-bindings: Document STM32 CRC bindings

[Fabien Dessenne]

Document device tree bindings for the STM32 CRC (crypto CRC32)

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 .../devicetree/bindings/crypto/st,stm32-crc.txt  | 16 
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-crc.txt

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt 
b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
new file mode 100644
index 000..2312e8a
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
@@ -0,0 +1,16 @@
+* STMicroelectronics STM32 CRC
+
+Required properties:
+- compatible: shoudl be "st,stm32f7-crc".
+- reg: The address and length of the peripheral registers space
+- clocks: The input clock of the CRC instance
+
+Optional properties: none
+
+Example:
+
+crc: crc@40023000 {
+   compatible = "st,stm32f7-crc";
+   reg = <0x40023000 0x400>;
+   clocks = < 0 12>;
+};
-- 
2.7.4

[PATCH 2/4] crypto: stm32 - Support for STM32 CRC32 crypto module

[Fabien Dessenne]

This module registers a CRC32 ("Ethernet") and a CRC32C (Castagnoli)
algorithm that make use of the STMicroelectronics STM32 crypto hardware.

Theses algorithms are compatible with the little-endian generic ones.
Both algorithms use ~0 as default seed (key).
With CRC32C the output is xored with ~0.

Using TCRYPT CRC32C speed test, this shows up to 900% speedup compared
to the crc32c-generic algorithm.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 drivers/crypto/Kconfig |   2 +
 drivers/crypto/Makefile|   1 +
 drivers/crypto/stm32/Kconfig   |   8 +
 drivers/crypto/stm32/Makefile  |   2 +
 drivers/crypto/stm32/stm32_crc32.c | 325 +
 5 files changed, 338 insertions(+)
 create mode 100644 drivers/crypto/stm32/Kconfig
 create mode 100644 drivers/crypto/stm32/Makefile
 create mode 100644 drivers/crypto/stm32/stm32_crc32.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 473d312..922b323 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -619,4 +619,6 @@ config CRYPTO_DEV_BCM_SPU
  Secure Processing Unit (SPU). The SPU driver registers ablkcipher,
  ahash, and aead algorithms with the kernel cryptographic API.
 
+source "drivers/crypto/stm32/Kconfig"
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 7396094..95bf2f9 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
 obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
 obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
 obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
+obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32/
 obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
 obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
 obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
new file mode 100644
index 000..792335b
--- /dev/null
+++ b/drivers/crypto/stm32/Kconfig
@@ -0,0 +1,8 @@
+config CRYPTO_DEV_STM32
+   tristate "Support for STM32 crypto accelerators"
+   depends on ARCH_STM32
+   select CRYPTO_HASH
+   help
+  This enables support for the CRC32 hw accelerator which can be found
+ on STMicroelectronis STM32 SOC.
+
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
new file mode 100644
index 000..73b4c6e
--- /dev/null
+++ b/drivers/crypto/stm32/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32_cryp.o
+stm32_cryp-objs := stm32_crc32.o
diff --git a/drivers/crypto/stm32/stm32_crc32.c 
b/drivers/crypto/stm32/stm32_crc32.c
new file mode 100644
index 000..ba780a6
--- /dev/null
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -0,0 +1,325 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author: Fabien Dessenne <fabien.desse...@st.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+
+#define DRIVER_NAME "stm32-crc32"
+#define CHKSUM_DIGEST_SIZE  4
+#define CHKSUM_BLOCK_SIZE   1
+
+/* Registers */
+#define CRC_DR  0x
+#define CRC_CR  0x0008
+#define CRC_INIT0x0010
+#define CRC_POL 0x0014
+
+/* Registers values */
+#define CRC_CR_RESETBIT(0)
+#define CRC_CR_REVERSE  (BIT(7) | BIT(6) | BIT(5))
+#define CRC_INIT_DEFAULT0x
+
+/* Polynomial reversed */
+#define POLY_CRC32  0xEDB88320
+#define POLY_CRC32C 0x82F63B78
+
+struct stm32_crc {
+   struct list_head list;
+   struct device*dev;
+   void __iomem *regs;
+   struct clk   *clk;
+   u8   pending_data[sizeof(u32)];
+   size_t   nb_pending_bytes;
+};
+
+struct stm32_crc_list {
+   struct list_head dev_list;
+   spinlock_t   lock; /* protect dev_list */
+};
+
+static struct stm32_crc_list crc_list = {
+   .dev_list = LIST_HEAD_INIT(crc_list.dev_list),
+   .lock = __SPIN_LOCK_UNLOCKED(crc_list.lock),
+};
+
+struct stm32_crc_ctx {
+   u32 key;
+   u32 poly;
+};
+
+struct stm32_crc_desc_ctx {
+   u32partial; /* crc32c: partial in first 4 bytes of that struct */
+   struct stm32_crc *crc;
+};
+
+static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
+{
+   struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
+
+   mctx->key = CRC_INIT_DEFAULT;
+   mctx->poly = POLY_CRC32;
+   return 0;
+}
+
+static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
+{
+   struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
+
+   mctx->key = CRC_INIT_DEFAULT;
+   mctx->poly = POLY_CRC32C;
+   return 0;
+}
+
+static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key,
+   unsigned int keylen)
+{
+   struct stm32_crc_ctx *

[PATCH 0/4] STM32 CRC crypto driver

[Fabien Dessenne]

This set of patches adds a new crypto driver for STMicroelectronics stm32f746.
The drivers uses the crypto API and provides with an HW-enabled CRC32 algorithm.
It was developed and tested (tcrypt / testmgr) on evaluation board stm32746g.

Fabien Dessenne (4):
  dt-bindings: Document STM32 CRC bindings
  crypto: stm32 - Support for STM32 CRC32 crypto module
  ARM: dts: stm32: Add CRC support to stm32f746
  ARM: dts: stm32: enable CRC on stm32746g-eval board

 .../devicetree/bindings/crypto/st,stm32-crc.txt|  16 +
 arch/arm/boot/dts/stm32746g-eval.dts   |   4 +
 arch/arm/boot/dts/stm32f746.dtsi   |   7 +
 drivers/crypto/Kconfig |   2 +
 drivers/crypto/Makefile|   1 +
 drivers/crypto/stm32/Kconfig   |   8 +
 drivers/crypto/stm32/Makefile  |   2 +
 drivers/crypto/stm32/stm32_crc32.c | 325 +
 8 files changed, 365 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
 create mode 100644 drivers/crypto/stm32/Kconfig
 create mode 100644 drivers/crypto/stm32/Makefile
 create mode 100644 drivers/crypto/stm32/stm32_crc32.c

-- 
2.7.4

[PATCH 3/4] ARM: dts: stm32: Add CRC support to stm32f746

[Fabien Dessenne]

Add CRC (CRC32 crypto) support to stm32f746.

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 arch/arm/boot/dts/stm32f746.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index f321ffe..755fb92 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -289,6 +289,13 @@
};
};
 
+   crc: crc@40023000 {
+   compatible = "st,stm32f7-crc";
+   reg = <0x40023000 0x400>;
+   clocks = < 0 12>;
+   status = "disabled";
+   };
+
rcc: rcc@40023800 {
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
-- 
2.7.4

[PATCH] crypto: doc - fix typo (struct sdesc)

[Fabien Dessenne]

Add missing " " in api-samples.rst

Signed-off-by: Fabien Dessenne <fabien.desse...@st.com>
---
 Documentation/crypto/api-samples.rst | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/crypto/api-samples.rst 
b/Documentation/crypto/api-samples.rst
index 0a10819..d021fd9 100644
--- a/Documentation/crypto/api-samples.rst
+++ b/Documentation/crypto/api-samples.rst
@@ -155,9 +155,9 @@ Code Example For Use of Operational State Memory With SHASH
 char ctx[];
 };
 
-static struct sdescinit_sdesc(struct crypto_shash *alg)
+static struct sdesc init_sdesc(struct crypto_shash *alg)
 {
-struct sdescsdesc;
+struct sdesc sdesc;
 int size;
 
 size = sizeof(struct shash_desc) + crypto_shash_descsize(alg);
@@ -172,7 +172,7 @@ Code Example For Use of Operational State Memory With SHASH
 static int calc_hash(struct crypto_shashalg,
  const unsigned chardata, unsigned int datalen,
  unsigned chardigest) {
-struct sdescsdesc;
+struct sdesc sdesc;
 int ret;
 
 sdesc = init_sdesc(alg);
-- 
2.7.4