Re: [PATCH v3] MIPS: Fix build breakage caused by header file changes

[James Hogan]

Hi Guenter,

On Mon, Mar 06, 2017 at 11:13:55AM -0800, Guenter Roeck wrote:
> Since commit f3ac60671954 ("sched/headers: Move task-stack related
> APIs from  to ") and commit
> f780d89a0e82 ("sched/headers: Remove  from
> "), various mips builds fail as follows.
> 
> arch/mips/kernel/smp-mt.c: In function ‘vsmp_boot_secondary’:
> arch/mips/include/asm/processor.h:384:41: error:
>   implicit declaration of function ‘task_stack_page’
> 
> In file included from
>   /opt/buildbot/slave/hwmon-testing/build/arch/mips/kernel/pm.c:
> arch/mips/include/asm/fpu.h: In function '__own_fpu':
> arch/mips/include/asm/processor.h:385:31: error:
>   invalid application of 'sizeof' to incomplete type 'struct pt_regs'

This one is in an inline function, so I think it'd affect multiple
includes of  even if __own_fpu isn't used, so I think the
following patch which adds the include ptrace.h in fpu.h is more robust
than adding to the individual c files affected:
https://patchwork.linux-mips.org/patch/15386/

Admitedly it could probably have a more specific subject line since
there are more similar errors.

Cheers
James

> 
> arch/mips/netlogic/common/smp.c: In function 'nlm_boot_secondary':
> arch/mips/netlogic/common/smp.c:157:2: error:
>   implicit declaration of function 'task_stack_page'
> 
> and more similar errors.
> 
> Fixes: f3ac60671954 ("sched/headers: Move task-stack related APIs ...")
> Fixes: f780d89a0e82 ("sched/headers: Remove  from ...")
> Cc: Ingo Molnar 
> Signed-off-by: Guenter Roeck 
> ---
> v3: Catch more build errors
> 
>  arch/mips/cavium-octeon/cpu.c  | 3 ++-
>  arch/mips/cavium-octeon/crypto/octeon-crypto.c | 1 +
>  arch/mips/cavium-octeon/smp.c  | 2 +-
>  arch/mips/kernel/pm.c  | 1 +
>  arch/mips/kernel/smp-mt.c  | 2 +-
>  arch/mips/netlogic/common/smp.c| 1 +
>  arch/mips/netlogic/xlp/cop2-ex.c   | 3 ++-
>  arch/mips/power/cpu.c  | 1 +
>  8 files changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/mips/cavium-octeon/cpu.c b/arch/mips/cavium-octeon/cpu.c
> index a5b427909b5c..b826b7a87c57 100644
> --- a/arch/mips/cavium-octeon/cpu.c
> +++ b/arch/mips/cavium-octeon/cpu.c
> @@ -10,7 +10,8 @@
>  #include 
>  #include 
>  #include 
> -#include 
> +#include 
> +#include 
>  
>  #include 
>  #include 
> diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.c 
> b/arch/mips/cavium-octeon/crypto/octeon-crypto.c
> index 4d22365844af..cfb4a146cf17 100644
> --- a/arch/mips/cavium-octeon/crypto/octeon-crypto.c
> +++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.c
> @@ -9,6 +9,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  #include "octeon-crypto.h"
>  
> diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
> index 4b94b7fbafa3..d475c0146347 100644
> --- a/arch/mips/cavium-octeon/smp.c
> +++ b/arch/mips/cavium-octeon/smp.c
> @@ -10,8 +10,8 @@
>  #include 
>  #include 
>  #include 
> -#include 
>  #include 
> +#include 
>  #include 
>  #include 
>  
> diff --git a/arch/mips/kernel/pm.c b/arch/mips/kernel/pm.c
> index dc814892133c..fab05022ab39 100644
> --- a/arch/mips/kernel/pm.c
> +++ b/arch/mips/kernel/pm.c
> @@ -11,6 +11,7 @@
>  
>  #include 
>  #include 
> +#include 
>  
>  #include 
>  #include 
> diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
> index e077ea3e11fb..effc1ed18954 100644
> --- a/arch/mips/kernel/smp-mt.c
> +++ b/arch/mips/kernel/smp-mt.c
> @@ -18,7 +18,7 @@
>   * Copyright (C) 2006 Ralf Baechle (r...@linux-mips.org)
>   */
>  #include 
> -#include 
> +#include 
>  #include 
>  #include 
>  #include 
> diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
> index 10d86d54880a..9035558920c1 100644
> --- a/arch/mips/netlogic/common/smp.c
> +++ b/arch/mips/netlogic/common/smp.c
> @@ -37,6 +37,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  #include 
>  
> diff --git a/arch/mips/netlogic/xlp/cop2-ex.c 
> b/arch/mips/netlogic/xlp/cop2-ex.c
> index 52bc5de42005..d990b7fc84aa 100644
> --- a/arch/mips/netlogic/xlp/cop2-ex.c
> +++ b/arch/mips/netlogic/xlp/cop2-ex.c
> @@ -13,7 +13,8 @@
>  #include 
>  #include 
>  #include 
> -#include 
> +#include 
> +#include 
>  
>  #include 
>  #include 
> diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c
> index 2129e67723ff..6e26bf7f 100644
> --- a/arch/mips/power/cpu.c
> +++ b/arch/mips/power/cpu.c
> @@ -7,6 +7,7 @@
>   * Author: Hu Hongbing 
>   *  Wu Zhangjin 
>   */
> +#include 
>  #include 
>  #include 
>  #include 
> -- 
> 2.7.4
> 
> 


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Re: [PATCH v3] MIPS: Fix build breakage caused by header file changes

[James Hogan]

Hi Ingo,

On Tue, Mar 07, 2017 at 08:38:05AM +0100, Ingo Molnar wrote:
> Just a quick question: is your MIPS build fix going to be merged and sent to 
> Linus? I can apply it too, and send it to Linus later today, together with a 
> few 
> other sched.h header related build fixes.

One for Ralf...

> Assuming it's all properly tested - my limited MIPS defconfig builds worked 
> fine - 
> but MIPS has a lot of build variations.

If you have a branch with other generic fixes I'm happy to push it to
our MIPS buildbot too to double check.

Cheers
James


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Re: [PATCH v3] MIPS: Fix build breakage caused by header file changes

[James Hogan]

On Mon, Mar 06, 2017 at 07:30:05PM -0800, Guenter Roeck wrote:
> On 03/06/2017 03:20 PM, James Hogan wrote:
> > On Mon, Mar 06, 2017 at 11:13:55AM -0800, Guenter Roeck wrote:
> >> Since commit f3ac60671954 ("sched/headers: Move task-stack related
> >> APIs from  to ") and commit
> >> f780d89a0e82 ("sched/headers: Remove  from
> >> "), various mips builds fail as follows.
> >>
> >> arch/mips/kernel/smp-mt.c: In function ‘vsmp_boot_secondary’:
> >> arch/mips/include/asm/processor.h:384:41: error:
> >>implicit declaration of function ‘task_stack_page’
> >>
> >> In file included from
> >>/opt/buildbot/slave/hwmon-testing/build/arch/mips/kernel/pm.c:
> >> arch/mips/include/asm/fpu.h: In function '__own_fpu':
> >> arch/mips/include/asm/processor.h:385:31: error:
> >>invalid application of 'sizeof' to incomplete type 'struct pt_regs'
> >
> > This one is in an inline function, so I think it'd affect multiple
> > includes of  even if __own_fpu isn't used, so I think the
> > following patch which adds the include ptrace.h in fpu.h is more robust
> > than adding to the individual c files affected:
> > https://patchwork.linux-mips.org/patch/15386/
> >
> Agreed.
> 
> > Admitedly it could probably have a more specific subject line since
> > there are more similar errors.
> 
> Does that fix all compile problems ? Seems to me that we'll still need
> 
> -#include 
> +#include 
> 
> or did you prepare a patch for this as well ?

It fixed the config I was using at the time. I didn't do a full build
test of all configs at the time so didn't fix the above.

Cheers
James


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Re: [PATCH v3] MIPS: Fix build breakage caused by header file changes

[James Hogan]

Hi Guenter,

On Tue, Mar 07, 2017 at 09:33:40AM +, James Hogan wrote:
> On Mon, Mar 06, 2017 at 07:30:05PM -0800, Guenter Roeck wrote:
> > On 03/06/2017 03:20 PM, James Hogan wrote:
> > > On Mon, Mar 06, 2017 at 11:13:55AM -0800, Guenter Roeck wrote:
> > >> Since commit f3ac60671954 ("sched/headers: Move task-stack related
> > >> APIs from  to ") and commit
> > >> f780d89a0e82 ("sched/headers: Remove  from
> > >> "), various mips builds fail as follows.
> > >>
> > >> arch/mips/kernel/smp-mt.c: In function ‘vsmp_boot_secondary’:
> > >> arch/mips/include/asm/processor.h:384:41: error:
> > >>  implicit declaration of function ‘task_stack_page’
> > >>
> > >> In file included from
> > >>  /opt/buildbot/slave/hwmon-testing/build/arch/mips/kernel/pm.c:
> > >> arch/mips/include/asm/fpu.h: In function '__own_fpu':
> > >> arch/mips/include/asm/processor.h:385:31: error:
> > >>  invalid application of 'sizeof' to incomplete type 'struct pt_regs'
> > >
> > > This one is in an inline function, so I think it'd affect multiple
> > > includes of  even if __own_fpu isn't used, so I think the
> > > following patch which adds the include ptrace.h in fpu.h is more robust
> > > than adding to the individual c files affected:
> > > https://patchwork.linux-mips.org/patch/15386/
> > >
> > Agreed.
> > 
> > > Admitedly it could probably have a more specific subject line since
> > > there are more similar errors.
> > 
> > Does that fix all compile problems ? Seems to me that we'll still need
> > 
> > -#include 
> > +#include 
> > 
> > or did you prepare a patch for this as well ?
> 
> It fixed the config I was using at the time. I didn't do a full build
> test of all configs at the time so didn't fix the above.

More specifically your changes to the following files:
arch/mips/kernel/pm.c
arch/mips/power/cpu.c

Don't appear to be necessary with my patch above, but the rest look good
to me. With those changes removed:

Reviewed-by: James Hogan <james.ho...@imgtec.com>

Build testing of that in progress...

Thanks
James


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Re: [PATCH 2/2] MIPS: crypto: Add crc32 and crc32c hw accelerated module

[James Hogan]

Hi Marcin,

On Wed, Sep 27, 2017 at 02:18:36PM +0200, Marcin Nowakowski wrote:
> This module registers crc32 and crc32c algorithms that use the
> optional CRC32[bhwd] and CRC32C[bhwd] instructions in MIPSr6 cores.
> 
> Signed-off-by: Marcin Nowakowski 
> Cc: linux-crypto@vger.kernel.org
> Cc: Herbert Xu 
> Cc: "David S. Miller" 
> 
> ---
>  arch/mips/Kconfig |   4 +
>  arch/mips/Makefile|   3 +
>  arch/mips/crypto/Makefile |   5 +
>  arch/mips/crypto/crc32-mips.c | 361 
> ++
>  crypto/Kconfig|   9 ++
>  5 files changed, 382 insertions(+)
>  create mode 100644 arch/mips/crypto/Makefile
>  create mode 100644 arch/mips/crypto/crc32-mips.c
> 
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index cb7fcc4..0f96812 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -2036,6 +2036,7 @@ config CPU_MIPSR6
>   select CPU_HAS_RIXI
>   select HAVE_ARCH_BITREVERSE
>   select MIPS_ASID_BITS_VARIABLE
> + select MIPS_CRC_SUPPORT
>   select MIPS_SPRAM
>  
>  config EVA
> @@ -2503,6 +2504,9 @@ config MIPS_ASID_BITS
>  config MIPS_ASID_BITS_VARIABLE
>   bool
>  
> +config MIPS_CRC_SUPPORT
> + bool
> +
>  #
>  # - Highmem only makes sense for the 32-bit kernel.
>  # - The current highmem code will only work properly on physically indexed
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index a96d97a..aa77536 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -216,6 +216,8 @@ cflags-$(toolchain-msa)   += 
> -DTOOLCHAIN_SUPPORTS_MSA
>  endif
>  toolchain-virt   := $(call 
> cc-option-yn,$(mips-cflags) -mvirt)
>  cflags-$(toolchain-virt) += -DTOOLCHAIN_SUPPORTS_VIRT
> +toolchain-crc:= $(call 
> cc-option-yn,$(mips-cflags) -Wa$(comma)-mcrc)
> +cflags-$(toolchain-crc)  += -DTOOLCHAIN_SUPPORTS_CRC
>  
>  #
>  # Firmware support
> @@ -324,6 +326,7 @@ libs-y+= arch/mips/math-emu/
>  # See arch/mips/Kbuild for content of core part of the kernel
>  core-y += arch/mips/
>  
> +drivers-$(CONFIG_MIPS_CRC_SUPPORT) += arch/mips/crypto/
>  drivers-$(CONFIG_OPROFILE)   += arch/mips/oprofile/
>  
>  # suspend and hibernation support
> diff --git a/arch/mips/crypto/Makefile b/arch/mips/crypto/Makefile
> new file mode 100644
> index 000..665c725
> --- /dev/null
> +++ b/arch/mips/crypto/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# Makefile for MIPS crypto files..
> +#
> +
> +obj-$(CONFIG_CRYPTO_CRC32_MIPS) += crc32-mips.o
> diff --git a/arch/mips/crypto/crc32-mips.c b/arch/mips/crypto/crc32-mips.c
> new file mode 100644
> index 000..dfa8bb1
> --- /dev/null
> +++ b/arch/mips/crypto/crc32-mips.c
> @@ -0,0 +1,361 @@
> +/*
> + * crc32-mips.c - CRC32 and CRC32C using optional MIPSr6 instructions
> + *
> + * Module based on arm64/crypto/crc32-arm.c
> + *
> + * Copyright (C) 2014 Linaro Ltd 
> + * Copyright (C) 2017 Imagination Technologies, Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +enum crc_op_size {
> + b, h, w, d,
> +};
> +
> +enum crc_type {
> + crc32,
> + crc32c,
> +};
> +
> +#ifdef TOOLCHAIN_SUPPORTS_CRC
> +
> +#define _CRC32(crc, value, size, type)   \
> +do { \
> + __asm__ __volatile__(   \
> + ".set   push\n\t"   \
> + ".set   crc\n\t"\
> + #type #size "   %0, %1, %0\n\t" \
> + ".set   pop\n\t"\

Technically the \n\t on the last line is redundant.

> + : "+r" (crc)\
> + : "r" (value)   \
> +);   \
> +} while(0)
> +
> +#define CRC_REGISTER
> +
> +#else/* TOOLCHAIN_SUPPORTS_CRC */
> +/*
> + * Crc argument is currently ignored and the assembly below assumes
> + * the crc is stored in $2. As the register number is encoded in the
> + * instruction we can't let the compiler chose the register it wants.
> + * An alternative is to change the code to do
> + * move $2, %0
> + * crc32
> + * move %0, $2
> + * but that adds unnecessary operations that the crc32 operation is
> + * designed to avoid. This issue can go away once the assembler
> + * is extended to support this operation and the compiler can make
> + * the right register choice automatically
> + */
> +
> +#define _CRC32(crc, value, size, type)   
> \
> +do { 

[PATCH] lib/mpi: Fix umul_ppmm() for MIPS64r6

[James Hogan]

From: James Hogan <jho...@kernel.org>

Current MIPS64r6 toolchains aren't able to generate efficient
DMULU/DMUHU based code for the C implementation of umul_ppmm(), which
performs an unsigned 64 x 64 bit multiply and returns the upper and
lower 64-bit halves of the 128-bit result. Instead it widens the 64-bit
inputs to 128-bits and emits a __multi3 intrinsic call to perform a 128
x 128 multiply. This is both inefficient, and it results in a link error
since we don't include __multi3 in MIPS linux.

For example commit 90a53e4432b1 ("cfg80211: implement regdb signature
checking") merged in v4.15-rc1 recently broke the 64r6_defconfig and
64r6el_defconfig builds by indirectly selecting MPILIB. The same build
errors can be reproduced on older kernels by enabling e.g. CRYPTO_RSA:

lib/mpi/generic_mpih-mul1.o: In function `mpihelp_mul_1':
lib/mpi/generic_mpih-mul1.c:50: undefined reference to `__multi3'
lib/mpi/generic_mpih-mul2.o: In function `mpihelp_addmul_1':
lib/mpi/generic_mpih-mul2.c:49: undefined reference to `__multi3'
lib/mpi/generic_mpih-mul3.o: In function `mpihelp_submul_1':
lib/mpi/generic_mpih-mul3.c:49: undefined reference to `__multi3'
lib/mpi/mpih-div.o In function `mpihelp_divrem':
lib/mpi/mpih-div.c:205: undefined reference to `__multi3'
lib/mpi/mpih-div.c:142: undefined reference to `__multi3'

Therefore add an efficient MIPS64r6 implementation of umul_ppmm() using
inline assembly and the DMULU/DMUHU instructions, to prevent __multi3
calls being emitted.

Fixes: 7fd08ca58ae6 ("MIPS: Add build support for the MIPS R6 ISA")
Signed-off-by: James Hogan <jho...@kernel.org>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Herbert Xu <herb...@gondor.apana.org.au>
Cc: "David S. Miller" <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: linux-crypto@vger.kernel.org
---
Please can somebody apply this fix for v4.15, as the MIPS 64r6_defconfig
and 64r6el_defconfig builds are broken without it.
---
 lib/mpi/longlong.h | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/lib/mpi/longlong.h b/lib/mpi/longlong.h
index 57fd45ab7af1..08c60d10747f 100644
--- a/lib/mpi/longlong.h
+++ b/lib/mpi/longlong.h
@@ -671,7 +671,23 @@ do {   \
**  MIPS/64  **
***/
 #if (defined(__mips) && __mips >= 3) && W_TYPE_SIZE == 64
-#if (__GNUC__ >= 5) || (__GNUC__ >= 4 && __GNUC_MINOR__ >= 4)
+#if defined(__mips_isa_rev) && __mips_isa_rev >= 6
+/*
+ * GCC ends up emitting a __multi3 intrinsic call for MIPS64r6 with the plain C
+ * code below, so we special case MIPS64r6 until the compiler can do better.
+ */
+#define umul_ppmm(w1, w0, u, v)
\
+do {   \
+   __asm__ ("dmulu %0,%1,%2"   \
+: "=d" ((UDItype)(w0)) \
+: "d" ((UDItype)(u)),  \
+  "d" ((UDItype)(v))); \
+   __asm__ ("dmuhu %0,%1,%2"   \
+: "=d" ((UDItype)(w1)) \
+: "d" ((UDItype)(u)),  \
+  "d" ((UDItype)(v))); \
+} while (0)
+#elif (__GNUC__ >= 5) || (__GNUC__ >= 4 && __GNUC_MINOR__ >= 4)
 #define umul_ppmm(w1, w0, u, v) \
 do {   \
typedef unsigned int __ll_UTItype __attribute__((mode(TI)));\
-- 
2.14.1

[PATCH v3 2/3] MIPS: crypto: Add crc32 and crc32c hw accelerated module

[James Hogan]

From: Marcin Nowakowski <marcin.nowakow...@mips.com>

This module registers crc32 and crc32c algorithms that use the
optional CRC32[bhwd] and CRC32C[bhwd] instructions in MIPSr6 cores.

Signed-off-by: Marcin Nowakowski <marcin.nowakow...@mips.com>
Signed-off-by: James Hogan <jho...@kernel.org>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Herbert Xu <herb...@gondor.apana.org.au>
Cc: "David S. Miller" <da...@davemloft.net>
Cc: linux-m...@linux-mips.org
Cc: linux-crypto@vger.kernel.org
---
Changes in v3:
 - Convert to using assembler macros to support CRC instructions on
   older toolchains, using the helpers merged for 4.16. This removes the
   need to hardcode either rt or rs (i.e. as $v0 (CRC_REGISTER) and
   $at), and drops the C "register" keywords sprinkled everywhere.
 - Minor whitespace rearrangement of _CRC32 macro.
 - Add SPDX-License-Identifier to crc32-mips.c and the crypo Makefile.
 - Update copyright from ImgTec to MIPS Tech, LLC.
 - Update imgtec.com email addresses to mips.com.

Changes in v2:
 - minor code refactoring as suggested by JamesH which produces
   a better assembly output for 32-bit builds
---
 arch/mips/Kconfig |   4 +-
 arch/mips/Makefile|   3 +-
 arch/mips/crypto/Makefile |   6 +-
 arch/mips/crypto/crc32-mips.c | 346 +++-
 crypto/Kconfig|   9 +-
 5 files changed, 368 insertions(+)
 create mode 100644 arch/mips/crypto/Makefile
 create mode 100644 arch/mips/crypto/crc32-mips.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ac0f5bb10f0b..cccd17c07bfc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2023,6 +2023,7 @@ config CPU_MIPSR6
select CPU_HAS_RIXI
select HAVE_ARCH_BITREVERSE
select MIPS_ASID_BITS_VARIABLE
+   select MIPS_CRC_SUPPORT
select MIPS_SPRAM
 
 config EVA
@@ -2490,6 +2491,9 @@ config MIPS_ASID_BITS
 config MIPS_ASID_BITS_VARIABLE
bool
 
+config MIPS_CRC_SUPPORT
+   bool
+
 #
 # - Highmem only makes sense for the 32-bit kernel.
 # - The current highmem code will only work properly on physically indexed
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index d1ca839c3981..44a6ed53d018 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -222,6 +222,8 @@ xpa-cflags-y:= 
$(mips-cflags)
 xpa-cflags-$(micromips-ase)+= -mmicromips 
-Wa$(comma)-fatal-warnings
 toolchain-xpa  := $(call cc-option-yn,$(xpa-cflags-y) 
-mxpa)
 cflags-$(toolchain-xpa)+= -DTOOLCHAIN_SUPPORTS_XPA
+toolchain-crc  := $(call cc-option-yn,$(mips-cflags) 
-Wa$(comma)-mcrc)
+cflags-$(toolchain-crc)+= -DTOOLCHAIN_SUPPORTS_CRC
 
 #
 # Firmware support
@@ -330,6 +332,7 @@ libs-y  += arch/mips/math-emu/
 # See arch/mips/Kbuild for content of core part of the kernel
 core-y += arch/mips/
 
+drivers-$(CONFIG_MIPS_CRC_SUPPORT) += arch/mips/crypto/
 drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
 
 # suspend and hibernation support
diff --git a/arch/mips/crypto/Makefile b/arch/mips/crypto/Makefile
new file mode 100644
index ..e07aca572c2e
--- /dev/null
+++ b/arch/mips/crypto/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for MIPS crypto files..
+#
+
+obj-$(CONFIG_CRYPTO_CRC32_MIPS) += crc32-mips.o
diff --git a/arch/mips/crypto/crc32-mips.c b/arch/mips/crypto/crc32-mips.c
new file mode 100644
index ..8d4122f37fa5
--- /dev/null
+++ b/arch/mips/crypto/crc32-mips.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * crc32-mips.c - CRC32 and CRC32C using optional MIPSr6 instructions
+ *
+ * Module based on arm64/crypto/crc32-arm.c
+ *
+ * Copyright (C) 2014 Linaro Ltd <yazen.ghan...@linaro.org>
+ * Copyright (C) 2018 MIPS Tech, LLC
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+enum crc_op_size {
+   b, h, w, d,
+};
+
+enum crc_type {
+   crc32,
+   crc32c,
+};
+
+#ifndef TOOLCHAIN_SUPPORTS_CRC
+#define _ASM_MACRO_CRC32(OP, SZ, TYPE)   \
+_ASM_MACRO_3R(OP, rt, rs, rt2,   \
+   ".ifnc  \\rt, \\rt2\n\t"  \
+   ".error \"invalid operands \\\"" #OP " \\rt,\\rs,\\rt2\\\"\"\n\t" \
+   ".endif\n\t"  \
+   _ASM_INSN_IF_MIPS(0x7c0f | (__rt << 16) | (__rs << 21) |  \
+ ((SZ) <<  6) | ((TYPE) << 8))   \
+   _ASM_INSN32_IF_MM(0x0030 | (__rs << 16) | (__rt << 21) |  \
+ ((SZ) << 14) | ((TYPE) << 3)))
+_ASM_MACRO_CRC32(crc32b,  0, 0);
+_ASM_MACRO_CRC32(crc32h,  1

[PATCH v3 0/3] MIPS CRC instruction support

[James Hogan]

MIPSr6 architecture introduces a new CRC32(C) instruction. The following
patches add a crypto acceleration module for crc32 and crc32c algorithms
using the new instructions.

Changes in v3:
 - Convert to using assembler macros to support CRC instructions on
   older toolchains, using the helpers merged for 4.16. This removes the
   need to hardcode either rt or rs (i.e. as $v0 (CRC_REGISTER) and
   $at), and drops the C "register" keywords sprinkled everywhere.
 - Minor whitespace rearrangement of _CRC32 macro.
 - Add SPDX-License-Identifier to crc32-mips.c and the crypo Makefile.
 - Update copyright from ImgTec to MIPS Tech, LLC.
 - Update imgtec.com email addresses to mips.com.
 - New patch 3 to enable crc32-mips module on r6 configs.

Changes in v2:
 - minor code refactoring as suggested by JamesH which produces
   a better assembly output for 32-bit builds

Cc: Marcin Nowakowski <marcin.nowakow...@mips.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Herbert Xu <herb...@gondor.apana.org.au>
Cc: "David S. Miller" <da...@davemloft.net>
Cc: Paul Burton <paul.bur...@mips.com>
Cc: linux-m...@linux-mips.org
Cc: linux-crypto@vger.kernel.org

James Hogan (1):
  MIPS: generic: Enable crc32-mips on r6 configs

Marcin Nowakowski (2):
  MIPS: Add crc instruction support flag to elf_hwcap
  MIPS: crypto: Add crc32 and crc32c hw accelerated module

 arch/mips/Kconfig |   4 +-
 arch/mips/Makefile|   3 +-
 arch/mips/configs/generic/32r6.config |   2 +-
 arch/mips/configs/generic/64r6.config |   2 +-
 arch/mips/crypto/Makefile |   6 +-
 arch/mips/crypto/crc32-mips.c | 346 +++-
 arch/mips/include/asm/mipsregs.h  |   1 +-
 arch/mips/include/uapi/asm/hwcap.h|   1 +-
 arch/mips/kernel/cpu-probe.c  |   3 +-
 crypto/Kconfig|   9 +-
 10 files changed, 377 insertions(+)
 create mode 100644 arch/mips/crypto/Makefile
 create mode 100644 arch/mips/crypto/crc32-mips.c

base-commit: 791412dafbbfd860e78983d45cf71db603a82f67
-- 
git-series 0.9.1

Re: [PATCH v3 2/3] MIPS: crypto: Add crc32 and crc32c hw accelerated module

[James Hogan]

On Thu, Feb 15, 2018 at 04:33:16PM +0800, Herbert Xu wrote:
> Acked-by: Herbert Xu 
 
Thanks Herbert,

Series applied for 4.17.

Cheers
James


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Re: [PATCH v3 2/3] MIPS: crypto: Add crc32 and crc32c hw accelerated module

[James Hogan]

On Thu, Feb 15, 2018 at 02:22:14PM -0800, Eric Biggers wrote:
> On Fri, Feb 09, 2018 at 10:11:06PM +0000, James Hogan wrote:
> > +static struct shash_alg crc32_alg = {
> > +   .digestsize =   CHKSUM_DIGEST_SIZE,
> > +   .setkey =   chksum_setkey,
> > +   .init   =   chksum_init,
> > +   .update =   chksum_update,
> > +   .final  =   chksum_final,
> > +   .finup  =   chksum_finup,
> > +   .digest =   chksum_digest,
> > +   .descsize   =   sizeof(struct chksum_desc_ctx),
> > +   .base   =   {
> > +   .cra_name   =   "crc32",
> > +   .cra_driver_name=   "crc32-mips-hw",
> > +   .cra_priority   =   300,
> > +   .cra_blocksize  =   CHKSUM_BLOCK_SIZE,
> > +   .cra_alignmask  =   0,
> > +   .cra_ctxsize=   sizeof(struct chksum_ctx),
> > +   .cra_module =   THIS_MODULE,
> > +   .cra_init   =   chksum_cra_init,
> > +   }
> > +};
> > +
> > +
> > +static struct shash_alg crc32c_alg = {
> > +   .digestsize =   CHKSUM_DIGEST_SIZE,
> > +   .setkey =   chksum_setkey,
> > +   .init   =   chksum_init,
> > +   .update =   chksumc_update,
> > +   .final  =   chksumc_final,
> > +   .finup  =   chksumc_finup,
> > +   .digest =   chksumc_digest,
> > +   .descsize   =   sizeof(struct chksum_desc_ctx),
> > +   .base   =   {
> > +   .cra_name   =   "crc32c",
> > +   .cra_driver_name=   "crc32c-mips-hw",
> > +   .cra_priority   =   300,
> > +   .cra_blocksize  =   CHKSUM_BLOCK_SIZE,
> > +   .cra_alignmask  =   0,
> > +   .cra_ctxsize=   sizeof(struct chksum_ctx),
> > +   .cra_module =   THIS_MODULE,
> > +   .cra_init   =   chksum_cra_init,
> > +   }
> > +};
>
> Does this actually work on the latest kernel?  Now hash algorithms must have
> CRYPTO_ALG_OPTIONAL_KEY in .cra_flags if they have a .setkey method but don't
> require it to be called, otherwise the crypto API will think it's a keyed hash
> and not allow it to be used without a key.  I had to add this flag to the 
> other
> CRC32 and CRC32C algorithms (commit a208fa8f33031).  One of the CRC32C test
> vectors even doesn't set a key so it should be causing the self-tests to fail
> for "crc32c-mips-hw".  (We should add such a test vector for CRC32 too, 
> though.)

Thanks Eric. It does indeed fail now with:

alg: hash: digest failed on test 1 for crc32c-mips-hw: ret=161

I'll squash in the following change:

diff --git a/arch/mips/crypto/crc32-mips.c b/arch/mips/crypto/crc32-mips.c
index 8d4122f37fa5..7d1d2425746f 100644
--- a/arch/mips/crypto/crc32-mips.c
+++ b/arch/mips/crypto/crc32-mips.c
@@ -284,6 +284,7 @@ static struct shash_alg crc32_alg = {
.cra_name   =   "crc32",
.cra_driver_name=   "crc32-mips-hw",
.cra_priority   =   300,
+   .cra_flags  =   CRYPTO_ALG_OPTIONAL_KEY,
.cra_blocksize  =   CHKSUM_BLOCK_SIZE,
.cra_alignmask  =   0,
.cra_ctxsize=   sizeof(struct chksum_ctx),
@@ -305,6 +306,7 @@ static struct shash_alg crc32c_alg = {
.cra_name   =   "crc32c",
.cra_driver_name=   "crc32c-mips-hw",
.cra_priority   =   300,
+   .cra_flags  =   CRYPTO_ALG_OPTIONAL_KEY,
.cra_blocksize  =   CHKSUM_BLOCK_SIZE,
.cra_alignmask  =   0,
.cra_ctxsize=   sizeof(struct chksum_ctx),

Cheers
James


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Re: [PATCH v3 3/4] crypto: jz4780-rng: Add RNG node to jz4780.dtsi

[James Hogan]

On Mon, Sep 18, 2017 at 07:32:40PM +0530, PrasannaKumar Muralidharan wrote:
> Add RNG node to jz4780 dtsi. This driver uses registers that are part of
> the register set used by Ingenic CGU driver. Use regmap in RNG driver to
> access its register. Create 'simple-bus' node, make CGU and RNG node as
> child of it so that both the nodes are visible without changing CGU
> driver code.
> 
> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmku...@gmail.com>

Better late than never:
Acked-by: James Hogan <jho...@kernel.org>

(I presume its okay for the reg ranges to overlap, ISTR that being an
issue a few years ago, but maybe thats fixed now).

Cheers
James


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