The tsgl scatterlist must be re-initialized after each
operation. Otherwise the sticky bits in the page_link will corrupt the
list with pre-mature termination or false chaining.
Signed-off-by: Lars Persson lar...@axis.com
---
crypto/algif_aead.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.
Signed-off-by: Lars Persson <lar...@axis.com>
---
.../devicetree/bindings/crypto/artpec6-crypto.txt| 16
1 file changed, 16 insertions(+)
create mode 100644 Documen
This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.
The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.
Signed-off-by: Lars Persson <lar...@axis.com>
---
drivers/crypto/K
From: Rabin Vincent <rab...@axis.com>
There are already helpers to (un)register multiple normal
and AEAD algos. Add one for ahashes too.
Signed-off-by: Lars Persson <lar...@axis.com>
Signed-off-by: Rabin Vincent <rab...@axis.com>
---
crypto/ahash.c
of CRYPTO_ALG_TYPE_ABLKCIPHER
in cra_flags.
Lars Persson (3):
dt-bindings: crypto: add ARTPEC crypto
crypto: axis: add ARTPEC-6/7 crypto accelerator driver
MAINTAINERS: Add ARTPEC crypto maintainer
Rabin Vincent (1):
crypto: add crypto_(un)register_ahashes()
.../devicetree/bindings/crypto/artpec6-crypto.txt
Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.
Signed-off-by: Lars Persson <lar...@axis.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
On 08/10/2017 02:53 PM, Lars Persson wrote:
From: Rabin Vincent <rab...@axis.com>
There are already helpers to (un)register multiple normal
and AEAD algos. Add one for ahashes too.
Signed-off-by: Lars Persson <lar...@axis.com>
Signed-off-by: Rabin Vincent <rab...@a
This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.
The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.
Signed-off-by: Lars Persson <lar...@axis.com>
---
drivers/crypto/K
-off-by on patch 2.
Changelog v2:
- Use xts_check_key() for xts keys.
- Use CRYPTO_ALG_TYPE_SKCIPHER instead of CRYPTO_ALG_TYPE_ABLKCIPHER
in cra_flags.
Lars Persson (3):
dt-bindings: crypto: add ARTPEC crypto
crypto: axis: add ARTPEC-6/7 crypto accelerator driver
MAINTAINERS: Add ARTPEC
Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Lars Persson <lar...@axis.com>
---
.../devicetree/bindings/crypto/artpec6-crypto.txt| 16
1 file
Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.
Signed-off-by: Lars Persson <lar...@axis.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
From: Rabin Vincent <rab...@axis.com>
There are already helpers to (un)register multiple normal
and AEAD algos. Add one for ahashes too.
Signed-off-by: Lars Persson <lar...@axis.com>
Signed-off-by: Rabin Vincent <rab...@axis.com>
---
v4: crypto_register_skciph
This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.
The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.
Signed-off-by: Lars Persson <lar...@axis.com>
---
drivers/crypto/K
Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.
Signed-off-by: Lars Persson <lar...@axis.com>
---
.../devicetree/bindings/crypto/artpec6-crypto.txt| 16
1 file changed, 16 insertions(+)
create mode 100644 Documen
This series adds a driver for the crypto accelerator in the ARTPEC series of
SoCs from Axis Communications AB.
Lars Persson (3):
dt-bindings: crypto: add ARTPEC crypto
crypto: axis: add ARTPEC-6/7 crypto accelerator driver
MAINTAINERS: Add ARTPEC crypto maintainer
Rabin Vincent (1
Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.
Signed-off-by: Lars Persson <lar...@axis.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
From: Rabin Vincent <rab...@axis.com>
There are already helpers to (un)register multiple normal
and AEAD algos. Add one for ahashes too.
Signed-off-by: Lars Persson <lar...@axis.com>
---
crypto/ahash.c | 29 +
include/crypto/internal
On 07/20/2017 04:51 PM, Stephan Müller wrote:
Am Donnerstag, 20. Juli 2017, 15:44:31 CEST schrieb Lars Persson:
Hi Lars,
+static int
+artpec6_crypto_cipher_set_key(struct crypto_skcipher *cipher, const u8
*key, + unsigned int keylen)
+{
+ struct
This series adds a driver for the crypto accelerator in the ARTPEC series of
SoCs from Axis Communications AB.
Changelog v2:
- Use xts_check_key() for xts keys.
- Use CRYPTO_ALG_TYPE_SKCIPHER instead of CRYPTO_ALG_TYPE_ABLKCIPHER
in cra_flags.
Lars Persson (3):
dt-bindings: crypto: add
Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.
Signed-off-by: Lars Persson <lar...@axis.com>
---
.../devicetree/bindings/crypto/artpec6-crypto.txt| 16
1 file changed, 16 insertions(+)
create mode 100644 Documen
Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.
Signed-off-by: Lars Persson <lar...@axis.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.
The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.
Signed-off-by: Lars Persson <lar...@axis.com>
---
drivers/crypto/K
From: Rabin Vincent <rab...@axis.com>
There are already helpers to (un)register multiple normal
and AEAD algos. Add one for ahashes too.
Signed-off-by: Lars Persson <lar...@axis.com>
---
crypto/ahash.c | 29 +
include/crypto/internal
ECLARE_FAULT_ATTR(artpec6_crypto_fail_dma_array_full);
> @@ -2984,6 +2982,8 @@ struct dbgfs_u32 {
> char *desc;
> };
>
> +static struct dentry *dbgfs_root;
> +
> static void artpec6_crypto_init_debugfs(void)
> {
> dbgfs_root = debugfs_create_dir("artpec6_crypto", NULL);
> --
> 2.9.0
Acked-by: Lars Persson <lar...@axis.com>
Thanks,
Lars
The IV size should not include the 32 bit counter. Because we had the
IV size set as 16 the transform only worked when the IV input was zero
padded.
Fixes: a21eb94fc4d3 ("crypto: axis - add ARTPEC-6/7 crypto accelerator driver")
Signed-off-by: Lars Persson <lar...@axis.com>
---
The IV size should not include the 32 bit counter. Because we had the
IV size set as 16 the transform only worked when the IV input was zero
padded.
Fixes: a21eb94fc4d3 ("crypto: axis - add ARTPEC-6/7 crypto accelerator driver")
Signed-off-by: Lars Persson <lar...@axis.com
Jesper Nilsson <jesper.nils...@axis.com>
Cc: Lars Persson <lars.pers...@axis.com>
Cc: Niklas Cassel <niklas.cas...@axis.com>
Cc: "David S. Miller" <da...@davemloft.net>
Cc: Jamie Iles <ja...@jamieiles.com>
Cc: linux-arm-ker...@axis.com
Cc: linux-crypto@vger.kerne
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