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James Morris jmor...@namei.org wrote:
Pulled to my -next branch, but it's too late really for 4.2, for this
class of bugfix.
Thanks. That'll do.
David
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On Fri, Aug 07, 2015 at 09:59:15AM +0200, Andrzej Hajda wrote:
The patch was generated using fixed coccinelle semantic patch
scripts/coccinelle/api/memdup.cocci [1].
[1]: http://permalink.gmane.org/gmane.linux.kernel/2014320
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Actually I
The patch was generated using fixed coccinelle semantic patch
scripts/coccinelle/api/memdup.cocci [1].
[1]: http://permalink.gmane.org/gmane.linux.kernel/2014320
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
crypto/echainiv.c | 7 ++-
crypto/seqiv.c| 6 ++
2 files changed, 4
The ESP code has been updated to generate a completely linear
AD SG list. This unfortunately broke authencesn which expects
the AD to be divided into at least three parts.
This patch fixes it to cope with the new format. Later we will
fix it properly to accept arbitrary input and not rely on
This patch converts authencesn to the new AEAD interface.
Signed-off-by: Herbert Xu herb...@gondor.apana.org.au
diff --git a/crypto/authencesn.c b/crypto/authencesn.c
index a3da677..c30393e 100644
--- a/crypto/authencesn.c
+++ b/crypto/authencesn.c
@@ -4,6 +4,7 @@
*
* Copyright (C) 2010
Am Donnerstag, 6. August 2015, 14:49:00 schrieb Brian Norris:
Hi Brian,
The HTML output works a little nicer that way.
Signed-off-by: Brian Norris computersforpe...@gmail.com
Thank you.
Ciao
Stephan
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On Wed, Aug 05, 2015 at 11:28:39AM -0700, Victoria Milhoan wrote:
Since fields must be ORed in to operate correctly using any order of
operations, changed allocations of the combination of extended
descriptor structs + hardware scatterlists to use kzalloc() instead
of kmalloc(), so as to
There are a couple of uses of struct scatterlist that never go to
the dma_map_sg() helper and thus don't care about ARCH_HAS_SG_CHAIN
which indicates that we can map chained S/G list.
The most important one is the crypto code, which currently has
to open code a few helpers to always allow
From: Dan Williams dan.j.willi...@intel.com
Signed-off-by: Dan Williams dan.j.willi...@intel.com
[hch: split from a larger patch by Dan]
Signed-off-by: Christoph Hellwig h...@lst.de
---
block/blk-merge.c| 2 +-
drivers/mmc/card/queue.c | 4 ++--
2 files changed, 3 insertions(+), 3
The rd sg lists are never passed to hardware, so use S/G chaining
unonditionally.
Signed-off-by: Christoph Hellwig h...@lst.de
---
drivers/target/target_core_rd.c | 44 -
1 file changed, 44 deletions(-)
diff --git a/drivers/target/target_core_rd.c
Signed-off-by: Dan Williams dan.j.willi...@intel.com
[hch: split from a larger patch by Dan]
Signed-off-by: Christoph Hellwig h...@lst.de
---
drivers/crypto/omap-sham.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
This series contains various scatterlist cleanups. It makes the chained
scatterlist helpers generally available, even if a architecture doesn't
allow a DMA mapping for it, and changes two callers to make use of this
as well as cleans up various opencoded access to scatterlist internals.
A large
From: Dan Williams dan.j.willi...@intel.com
Coccinelle cleanup to replace open coded sg to physical address
translations. This is in preparation for introducing scatterlists that
reference __pfn_t.
// sg_phys.cocci: convert usage page_to_phys(sg_page(sg)) to sg_phys(sg)
// usage: make
Add code that enables SRIOV on dh895xcc devices.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/Makefile |1
drivers/crypto/qat/qat_common/adf_accel_devices.h | 37 ++
drivers/crypto/qat/qat_common/adf_aer.c|3
The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
QuickAssist Technology is prematurely terminated in hardware.
Workaround the issue by hard-coding the known expected next capability
pointer and saving the PCIE cap into internal buffer.
Patch generated against cryptodev-2.6
Add code specific for the dh895xcc virtual function.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/Kconfig | 11 +
drivers/crypto/qat/Makefile|1
drivers/crypto/qat/qat_dh895xccvf/Makefile |5
Adf admin and HW arbiter function can be used by dh895xcc specific code
well as the new dh895xccvf and future devices so moving them to
qat_common so that they can be shared.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/Makefile |2
The following series adds SRIOV support for qat dh895xcc HW accelerator.
First patch moves admin code and hw arbiter code that can be reused by PF
and VF to common code in qat/qat_common/
Second patch enables SRIOV support on dh895xcc PF.
Third patch adds dh895xcc VF specific code.
Fourth patch
Some VF drivers need FW const table, so the PF driver needs to load it.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/adf_admin.c | 107 +
1 file changed, 106 insertions(+), 1 deletion(-)
diff --git
From: Dan Williams dan.j.willi...@intel.com
Signed-off-by: Dan Williams dan.j.willi...@intel.com
[hch: split from a larger patch by Dan]
Signed-off-by: Christoph Hellwig h...@lst.de
---
crypto/algif_skcipher.c | 2 +-
crypto/ccm.c | 8
crypto/gcm.c
On Fri, Aug 7, 2015 at 9:15 AM, Christoph Hellwig h...@lst.de wrote:
From: Dan Williams dan.j.willi...@intel.com
Coccinelle cleanup to replace open coded sg to physical address
translations. This is in preparation for introducing scatterlists that
reference __pfn_t.
// sg_phys.cocci:
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