Re: [PATCH] crypto: cavium: fix Kconfig dependencies

On 02/14/17 09:09, David Daney wrote: > On 02/14/2017 09:07 AM, Arnd Bergmann wrote: >> The driver fails to build if MSI support is disabled: >> >> In file included from >> /git/arm-soc/drivers/crypto/cavium/cpt/cptpf_main.c:18:0: >> drivers/crypto/cavium/cpt/cptpf.h:57:20: error: array type has

[PATCH 1/1] crypto: brcm - Avoid double free in ahash_finup()

In Broadcom SPU driver, in case where incremental hash is done in software in ahash_finup(), tmpbuf was freed twice. Reported-by: Dan Carpenter Signed-off-by: Rob Rice --- drivers/crypto/bcm/cipher.c | 1 - 1 file changed, 1 deletion(-) diff

Re: [PATCH 1/2] crypto: arm/aes-neonbs - resolve fallback cipher at runtime

On 14 February 2017 at 10:03, Ard Biesheuvel wrote: > Currently, the bit sliced NEON AES code for ARM has a link time > dependency on the scalar ARM asm implementation, which it uses as a > fallback to perform CBC encryption and the encryption of the initial > XTS

Re: [PATCH] crypto: cavium: fix Kconfig dependencies

On 02/14/2017 10:26 AM, Randy Dunlap wrote: On 02/14/17 09:09, David Daney wrote: On 02/14/2017 09:07 AM, Arnd Bergmann wrote: The driver fails to build if MSI support is disabled: In file included from /git/arm-soc/drivers/crypto/cavium/cpt/cptpf_main.c:18:0:

[bug report] crypto: cavium - Add Support for Octeon-tx CPT Engine

Hello George Cherian, The patch 9e2c7d99941d: "crypto: cavium - Add Support for Octeon-tx CPT Engine" from Feb 7, 2017, leads to the following static checker warning: drivers/crypto/cavium/cpt/cptpf_mbox.c:70 cpt_bind_vq_to_grp() warn: signedness bug returning '(-22)'

[PATCH 1/2] crypto: arm/aes-neonbs - resolve fallback cipher at runtime

Currently, the bit sliced NEON AES code for ARM has a link time dependency on the scalar ARM asm implementation, which it uses as a fallback to perform CBC encryption and the encryption of the initial XTS tweak. The bit sliced NEON code is both fast and time invariant, which makes it a reasonable

[PATCH 2/2] crypto: algapi - annotate expected branch behavior in crypto_inc()

To prevent unnecessary branching, mark the exit condition of the primary loop as likely(), given that a carry in a 32-bit counter occurs very rarely. On arm64, the resulting code is emitted by GCC as 9a8: cmp w1, #0x3 9ac: add x3, x0, w1, uxtw 9b0: b.ls9e0

[PATCH] drivers: crypto: cpt: cpt_bind_vq_to_grp could return an error code

cpt_bind_vq_to_grp() could return an error code. However, it currently returns a u8. This produce the static checker warning. drivers/crypto/cavium/cpt/cptpf_mbox.c:70 cpt_bind_vq_to_grp() warn: signedness bug returning '(-22)' Reported-by: Dan Carpenter

Re: [PATCH] lz4: fix performance regressions

Hey Eric, On Sun, Feb 12, 2017 at 03:38:02PM -0800, Eric Biggers wrote: > Hi Sven, > > On Sun, Feb 12, 2017 at 12:16:18PM +0100, Sven Schmidt wrote: > > /*- > > * Reading and writing into memory > > **/ > > +typedef

[PATCH] crypto: cavium: fix Kconfig dependencies

The driver fails to build if MSI support is disabled: In file included from /git/arm-soc/drivers/crypto/cavium/cpt/cptpf_main.c:18:0: drivers/crypto/cavium/cpt/cptpf.h:57:20: error: array type has incomplete element type 'struct msix_entry' struct msix_entry msix_entries[CPT_PF_MSIX_VECTORS];

Re: [PATCH] crypto: cavium: fix Kconfig dependencies

On 02/14/2017 09:07 AM, Arnd Bergmann wrote: The driver fails to build if MSI support is disabled: In file included from /git/arm-soc/drivers/crypto/cavium/cpt/cptpf_main.c:18:0: drivers/crypto/cavium/cpt/cptpf.h:57:20: error: array type has incomplete element type 'struct msix_entry' struct

Re: [RFC PATCH v1 1/1] mm: zswap - Add crypto acomp/scomp framework support

On Tue, Feb 14, 2017 at 9:40 AM, Mahipal Challa wrote: > This adds the support for kernel's crypto new acomp/scomp framework > to zswap. > > Signed-off-by: Mahipal Challa > Signed-off-by: Vishnu Nair > --- >

[RFC PATCH v1 1/1] mm: zswap - Add crypto acomp/scomp framework support

This adds the support for kernel's crypto new acomp/scomp framework to zswap. Signed-off-by: Mahipal Challa Signed-off-by: Vishnu Nair --- mm/zswap.c | 129 +++-- 1 file changed, 99

[RFC PATCH v1 0/1] mm: zswap - crypto acomp/scomp support

Hi Seth, Herbert, This series adds support for kernel's new crypto acomp/scomp compression & decompression framework to zswap. We verified these changes using the kernel's crypto deflate-scomp, lzo-scomp modules and Cavium's ThunderX ZIP driver (We will post the Cavium's ThunderX ZIP driver v2

Re: [PATCH v4 3/4] dmaengine: Add Broadcom SBA RAID driver

On Mon, Feb 13, 2017 at 10:51 PM, Anup Patel wrote: > The Broadcom stream buffer accelerator (SBA) provides offloading > capabilities for RAID operations. This SBA offload engine is > accessible via Broadcom SoC specific ring manager. > > This patch adds Broadcom SBA RAID

Re: [PATCH v3] crypto: algapi - make crypto_xor() and crypto_inc() alignment agnostic

On 13 February 2017 at 21:55, Jason A. Donenfeld wrote: > On Sun, Feb 5, 2017 at 11:06 AM, Ard Biesheuvel > wrote: >> + if (IS_ENABLED(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) || >> + !((unsigned long)b & (__alignof__(*b) - 1))) > > Why

[PATCH 0/4] crypto: gf128mul cleanups

This patchset makes a few cleanups to the generic GF(2^128) multiplication code to make it slightly easier to understand and modify. No functional changes are intended. Eric Biggers (4): crypto: gf128mul - fix some comments crypto: gf128mul - remove xx() macro crypto: gf128mul - rename the

[PATCH 4/4] crypto: gf128mul - constify 4k and 64k multiplication tables

Constify the multiplication tables passed to the 4k and 64k multiplication functions, as they are not modified by these functions. Cc: Alex Cope Signed-off-by: Eric Biggers --- crypto/gf128mul.c | 6 +++--- include/crypto/gf128mul.h | 6 +++---

[PATCH 3/4] crypto: gf128mul - rename the byte overflow tables

Though the GF(2^128) byte overflow tables were named the "lle" and "bbe" tables, they are not actually tied to these element formats specifically, but rather to particular a "bit endianness". For example, the bbe table is actually used for both bbe and ble multiplication. Therefore, rename the

[PATCH v2 2/2] crypto: algapi - annotate expected branch behavior in crypto_inc()

To prevent unnecessary branching, mark the exit condition of the primary loop as likely(), given that a carry in a 32-bit counter occurs very rarely. On arm64, the resulting code is emitted by GCC as 9a8: cmp w1, #0x3 9ac: add x3, x0, w1, uxtw 9b0: b.ls9e0

[PATCH v2 1/2] crypto: arm/aes-neonbs - resolve fallback cipher at runtime

Currently, the bit sliced NEON AES code for ARM has a link time dependency on the scalar ARM asm implementation, which it uses as a fallback to perform CBC encryption and the encryption of the initial XTS tweak. The bit sliced NEON code is both fast and time invariant, which makes it a reasonable

[PATCH 2/4] crypto: gf128mul - remove xx() macro

The xx() macro serves no purpose and can be removed. Cc: Alex Cope Signed-off-by: Eric Biggers --- crypto/gf128mul.c | 18 -- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/crypto/gf128mul.c b/crypto/gf128mul.c index

[PATCH 1/4] crypto: gf128mul - fix some comments

Fix incorrect references to GF(128) instead of GF(2^128), as these are two entirely different fields, and fix a few other incorrect comments. Cc: Alex Cope Signed-off-by: Eric Biggers --- crypto/gf128mul.c | 13 +++--

Re: crypto: NULL deref in sha512_mb_mgr_get_comp_job_avx2

On Mon, Feb 13, 2017 at 09:20:48AM -0800, Tim Chen wrote: > > Megha is now able to create a test set up that produce > similar problem reported by Dmitry.  This patch did not > completely fix it.  So maybe you can hold off on merging > this patch to the mainline till we can develop a more >

Re: Qualcomm QCE driver: XTS setkey only allows 128 bit AES

Stephan Müller wrote: > Hi, > > The Qualcomm QCE driver implementation defines: > >.flags = QCE_ALG_AES | QCE_MODE_XTS, >.name = "xts(aes)", >.drv_name = "xts-aes-qce", >.blocksize

Re: [PATCH] crypto: ccp - Set the AES size field for all modes

On Wed, Feb 08, 2017 at 01:07:06PM -0600, Gary R Hook wrote: > Ensure that the size field is correctly populated for > all AES modes. > > Signed-off-by: Gary R Hook Patch applied. Thanks. -- Email: Herbert Xu Home Page:

Re: [PATCH v2 0/3] Minor CCP improvements and clean-up

On Thu, Feb 09, 2017 at 03:49:38PM -0600, Gary R Hook wrote: > The following series implements... > - Move verbose init messages to debug mode > - Update the queue pointers in the event of an error > - Simply buffer management and eliminate an unused option All applied. Thanks. -- Email:

Re: [PATCH next 0/2] crypto: atmel-sha: fix error management

On Thu, Feb 09, 2017 at 05:51:19PM +0100, Cyrille Pitchen wrote: > Hi all, > > this series is based on next-20170209. All applied. Thanks. -- Email: Herbert Xu Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

[PATCH 1/3] crypto: cavium: remove dead MSI-X related define

Signed-off-by: Christoph Hellwig --- drivers/crypto/cavium/cpt/cpt_common.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/crypto/cavium/cpt/cpt_common.h b/drivers/crypto/cavium/cpt/cpt_common.h index ede612f306d3..225078d03773 100644 ---

[PATCH 3/3] crypto: cavium/cptvf: switch to pci_alloc_irq_vectors

pci_enable_msix has been long deprecated, but this driver adds a new instance. Convert it to pci_alloc_irq_vectors and greatly simplify the code, and make sure the prope code properly unwinds. Signed-off-by: Christoph Hellwig --- drivers/crypto/cavium/cpt/cptvf.h | 3 -

crypto/cavium MSI-X fixups

Hi George, your commit "crypto: cavium - Add Support for Octeon-tx CPT Engine" add a new caller to pci_enable_msix. This API has long been deprecated so this series switches it to use pci_alloc_irq_vectors instead. Can you please test it and make sure it goes in before the end of the merge

[PATCH 2/3] crypto: cavium/cptpf: switch to pci_alloc_irq_vectors

pci_enable_msix has been long deprecated, but this driver adds a new instance. Convert it to pci_alloc_irq_vectors and greatly simplify the code. Signed-off-by: Christoph Hellwig --- drivers/crypto/cavium/cpt/cptpf.h | 5 --- drivers/crypto/cavium/cpt/cptpf_main.c | 58

Re: [PATCH v4 3/4] dmaengine: Add Broadcom SBA RAID driver

On Tue, Feb 14, 2017 at 11:03 PM, Anup Patel wrote: > On Wed, Feb 15, 2017 at 12:13 PM, Dan Williams > wrote: >> On Tue, Feb 14, 2017 at 10:25 PM, Anup Patel wrote: >>> On Tue, Feb 14, 2017 at 10:04 PM, Dan Williams

Re: [PATCH] hw_random: update help description for omap-rng

On Mon, Feb 13, 2017 at 12:04:08PM +, Russell King wrote: > omap-rng also supports Marvell Armada 7k/8k SoCs, but no mention of this > is made in the help text, despite the dependency being added. Explicitly > mention these SoCs in the help description so people know that it covers > more than

Re: [PATCH 1/1] crypto: brcm - Avoid double free in ahash_finup()

On Tue, Feb 14, 2017 at 12:45:52PM -0500, Rob Rice wrote: > In Broadcom SPU driver, in case where incremental hash > is done in software in ahash_finup(), tmpbuf was freed > twice. > > Reported-by: Dan Carpenter > Signed-off-by: Rob Rice Patch

Re: Qualcomm QCE driver: XTS setkey only allows 128 bit AES

Am Mittwoch, 15. Februar 2017, 12:02:43 CET schrieb Herbert Xu: Hi Herbert, > Stephan Müller wrote: > > Hi, > > > > The Qualcomm QCE driver implementation defines: > >.flags = QCE_ALG_AES | QCE_MODE_XTS, > >.name =

Re: [PATCH 2/2] crypto: ccm - drop unnecessary minimum 32-bit alignment

On Sat, Feb 11, 2017 at 07:25:22PM +, Ard Biesheuvel wrote: > The CCM driver forces 32-bit alignment even if the underlying ciphers > don't care about alignment. This is because crypto_xor() used to require > this, but since this is no longer the case, drop the hardcoded minimum > of 32 bits.

Re: [PATCH 1/2] crypto: ccm - honour alignmask of subordinate MAC cipher

On Sat, Feb 11, 2017 at 07:25:21PM +, Ard Biesheuvel wrote: > The CCM driver was recently updated to defer the MAC part of the algorithm > to a dedicated crypto transform, and a template for instantiating such > transforms was added at the same time. > > However, this new cbcmac template

Re: [PATCH] drivers: crypto: cpt: cpt_bind_vq_to_grp could return an error code

On Tue, Feb 14, 2017 at 09:23:17AM +, George Cherian wrote: > cpt_bind_vq_to_grp() could return an error code. However, it currently > returns a u8. This produce the static checker warning. > > drivers/crypto/cavium/cpt/cptpf_mbox.c:70 cpt_bind_vq_to_grp() warn: > signedness bug returning

Re: [PATCH] crypto: fix typo in doc

On Tue, Feb 14, 2017 at 08:21:45AM +0200, Gilad Ben-Yossef wrote: > Fix a single letter typo in api-skcipher.rst. > > Signed-off-by: Gilad Ben-Yossef Patch applied. Thanks. -- Email: Herbert Xu Home Page: http://gondor.apana.org.au/~herbert/

Re: [PATCH 00/12] crypto: caam - fixes

On Fri, Feb 10, 2017 at 02:07:13PM +0200, Horia Geantă wrote: > This batch consists mostly of DMA API related fixes and simplifications. > > Since no no arch calls: > dma_debug_add_bus(_bus_type); > DMA API debugging does not have the chance to report leaks when modules > are removed. > > I am

Re: [PATCH v4 3/4] dmaengine: Add Broadcom SBA RAID driver

On Tue, Feb 14, 2017 at 10:25 PM, Anup Patel wrote: > On Tue, Feb 14, 2017 at 10:04 PM, Dan Williams > wrote: >> On Mon, Feb 13, 2017 at 10:51 PM, Anup Patel wrote: >>> The Broadcom stream buffer accelerator (SBA)

Re: [PATCH v7 0/5] Update LZ4 compressor module

Hi Sven, On Mon, Feb 13, 2017 at 01:08:41PM +0100, Sven Schmidt wrote: > On Mon, Feb 13, 2017 at 09:03:24AM +0900, Minchan Kim wrote: > > Hi Sven, > > > > On Sun, Feb 12, 2017 at 12:16:17PM +0100, Sven Schmidt wrote: > > > > > > > > > > > > On 02/10/2017 01:13 AM, Minchan Kim wrote: > > > >

[RFC PATCH v2 1/3] crypto: zip - Add ThunderX ZIP driver core

Add a driver for the ZIP engine found on Cavium ThunderX SOCs. The ZIP engine supports hardware accelerated compression and decompression. It includes 2 independent ZIP cores and supports: - DEFLATE compression and decompression (RFC 1951) - LZS compression and decompression (RFC 2395 and ANSI

[RFC PATCH v2 3/3] crypto: zip - Add Compression/Decompression statistics

Add statistics for compression/decompression hardware offload under debugfs. Signed-off-by: Mahipal Challa Signed-off-by: Jan Glauber --- drivers/crypto/cavium/zip/zip_deflate.c | 10 ++ drivers/crypto/cavium/zip/zip_inflate.c | 12 ++

[RFC PATCH v2 2/3] crypto: zip - Wire-up Compression / decompression HW offload

This contains changes for adding compression/decompression h/w offload functionality for both DEFLATE and LZS. Signed-off-by: Mahipal Challa Signed-off-by: Jan Glauber --- drivers/crypto/cavium/zip/Makefile | 5 +-

[RFC PATCH v2 0/3] Cavium ThunderX ZIP driver

Hi Herbert, This series adds support for hardware accelerated compression & decompression as found on ThunderX (arm64) SOCs. As per your suggestion, we've switched to the new crypto acomp/scomp interface. To test the ZIP driver, we modified the kernel's ZSWAP to use acomp API's. Performance

Re: [PATCH v4 3/4] dmaengine: Add Broadcom SBA RAID driver

On Tue, Feb 14, 2017 at 10:04 PM, Dan Williams wrote: > On Mon, Feb 13, 2017 at 10:51 PM, Anup Patel wrote: >> The Broadcom stream buffer accelerator (SBA) provides offloading >> capabilities for RAID operations. This SBA offload engine is >>

Re: [PATCH v4 3/4] dmaengine: Add Broadcom SBA RAID driver

On Wed, Feb 15, 2017 at 12:13 PM, Dan Williams wrote: > On Tue, Feb 14, 2017 at 10:25 PM, Anup Patel wrote: >> On Tue, Feb 14, 2017 at 10:04 PM, Dan Williams >> wrote: >>> On Mon, Feb 13, 2017 at 10:51 PM, Anup Patel