Re: [PATCH v3 1/3] Documentation/bindings: Document the SafeXel cryptographic engine driver

Hello, On Mon, 22 May 2017 16:02:33 +0100, Marc Zyngier wrote: > > It also says: 87 => 34 En Lv 5, which is the IRQ I'm looking for. > > Ah, that one as well. So how is the interrupt routed? Via the ICU, and > then to the GIC (with several ICU sources mapped on a single SPI)? The crypto

Re: [PATCH v5 1/4] Documentation/bindings: Document the SafeXel cryptographic engine driver

Hello, On Mon, 22 May 2017 16:45:11 +0200, Antoine Tenart wrote: > + interrupts = IRQ_TYPE_LEVEL_HIGH)>, You already got the feedback previously that an interrupt that is both edge and level at the same time doesn't make sense. Could you fix this? Also, the DTs that have already

[PATCH v2 1/2] dt-bindings: timeriomem_rng: Add entropy quality property

Signed-off-by: Rick Altherr --- Changes in v2: None Documentation/devicetree/bindings/rng/timeriomem_rng.txt | 7 +++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/rng/timeriomem_rng.txt

[PATCH v2 2/2] hw_random: timeriomem_rng: Allow setting RNG quality from platform data

When a hw_random device's quality is non-zero, it will automatically be used to fill the kernel's entropy pool. Since timeriomem_rng is used by many different devices, the quality needs to be provided by platform data or device tree. Signed-off-by: Rick Altherr --- Changes

Re: [PATCH] crypto: stm32 - Add CRC32 support for STM32F4XX

On Wed, May 17, 2017 at 12:18:50AM +0300, Cosar Dindar wrote: > This patch series add hardware CRC32 ("Ethernet") calculation support > for STMicroelectronics STM32F4XX series devices. > > As an hardware limitation polynomial and key setting are not supported > as they are fixed as 0x4C11DB7

Re: [PATCH v1] crypto: img-hash - Handle return value of clk_prepare_enable

On Tue, May 16, 2017 at 01:57:41PM +0530, Arvind Yadav wrote: > Here, Clock enable can failed. So adding an error check for > clk_prepare_enable. > > Signed-off-by: Arvind Yadav Patch applied. Thanks. -- Email: Herbert Xu Home Page:

Re: [PATCH] crypto: x86/aes - Don't use %rbp as temporary register

On Tue, May 16, 2017 at 09:03:08PM -0700, Eric Biggers wrote: > From: Eric Biggers > > When using the "aes-asm" implementation of AES (*not* the AES-NI > implementation) on an x86_64, v4.12-rc1 kernel with lockdep enabled, the > following warning was reported, along with a

Crypto Fixes for 4.12

Hi Linus: This push fixes a regression in the skcipher interface that allows bogus key parameters to hit underlying implementations which can cause crashes. Please pull from git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git linus Herbert Xu (1): crypto: skcipher -

Re: ecdh: generation and retention of ecc privkey in kernel/hardware

On Thu, Apr 27, 2017 at 05:17:58PM +0300, Tudor Ambarus wrote: > Hi, Herbert, > > I'm working with a crypto accelerator that is capable of generating and > retaining ecc private keys in hardware and further use them for ecdh. > The private keys can not be read from the device. This is good

Re: [PATCH 6/8] crypto: dh - fix dh_max_size

On Fri, May 12, 2017 at 01:11:44PM +0300, Tudor Ambarus wrote: > The function should return minimum size for output buffer > or error code if key hasn't been set. > > Signed-off-by: Tudor Ambarus > --- > crypto/dh.c | 2 +- > 1 file changed, 1 insertion(+), 1

Re: [PATCH v2 04/11] crypto: dh - fix dh_max_size

On Wed, May 17, 2017 at 06:00:31PM +0300, Tudor Ambarus wrote: > The function should return minimum size for output buffer > or error code if key hasn't been set. > > Signed-off-by: Tudor Ambarus > --- > crypto/dh.c | 2 +- > 1 file changed, 1 insertion(+), 1

Re: [PATCH v2 08/11] crypto: testmgr - check err on akcipher maxsize

On Wed, May 17, 2017 at 06:00:35PM +0300, Tudor Ambarus wrote: > crypto_akcipher_maxsize() returns minimum length for output buffer > or error code if key hasn't been set. > > Signed-off-by: Tudor Ambarus > --- > crypto/testmgr.c | 5 + > 1 file changed, 5

Re: [PATCH] crypto: qat: use pcie_flr instead of duplicating it

On Tue, May 16, 2017 at 04:21:05PM +0200, Christoph Hellwig wrote: > Signed-off-by: Christoph Hellwig Patch applied. Thanks. -- Email: Herbert Xu Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Re: [PATCH v1] hw_random : omap3-rom-rng:- Handle return value of clk_prepare_enable

On Mon, May 15, 2017 at 01:52:03PM +0530, Arvind Yadav wrote: > Here, Clock enable can failed. So adding an error check for > clk_prepare_enable. > > Signed-off-by: Arvind Yadav Patch applied. Thanks. -- Email: Herbert Xu Home Page:

Re: [PATCH v2 0/4] crypto: async crypto op fixes

On Thu, May 18, 2017 at 04:29:22PM +0300, Gilad Ben-Yossef wrote: > This patch set fixes various usage and documentation errors > in waiting for async crypto op to complete which can result > in data corruption. > > Note: these were discovered in the process of working on a > patch set that

Re: [PATCH v2 0/9] crypto: add HMAC IPAD/OPAD constant

On Fri, May 19, 2017 at 08:53:22AM +0200, Corentin Labbe wrote: > Hello > > Many HMAC users directly use directly 0x36/0x5c values. > It's better with crypto to use a name instead of directly some crypto > constant. > > Changes since v1: > - Moved constant to include/crypto/hmac.h > - Added to

[PATCH v5 2/4] crypto: inside-secure: add SafeXcel EIP197 crypto engine driver

Add support for Inside Secure SafeXcel EIP197 cryptographic engine, which can be found on Marvell Armada 7k and 8k boards. This driver currently implements: ecb(aes), cbc(aes), sha1, sha224, sha256 and hmac(sah1) algorithms. Two firmwares are needed for this engine to work. Their are mostly used

[PATCH v5 1/4] Documentation/bindings: Document the SafeXel cryptographic engine driver

The Inside Secure Safexcel cryptographic engine is found on some Marvell SoCs (7k/8k). Document the bindings used by its driver. Signed-off-by: Antoine Tenart --- .../bindings/crypto/inside-secure-safexcel.txt | 29 ++ 1 file changed,

[PATCH v3 0/5] Add support for the STM32F4 CRC32

This patch series add hardware CRC32 ("Ethernet") calculation support for STMicroelectronics STM32F429. Polynomial and key setting are not supported, key is fixed as 0x4C11DB7 and poly is 0x. Module is tested on STM32F429-disco board with crypto testmgr using cases within the key

Re: [PATCH v3 1/3] Documentation/bindings: Document the SafeXel cryptographic engine driver

Hi Antoine, On 22/05/17 15:30, Antoine Tenart wrote: > Hi Marc, > > On Wed, May 03, 2017 at 05:36:38PM +0100, Marc Zyngier wrote: >> On 24/04/17 08:54, Antoine Tenart wrote: >>> + >>> + crypto: crypto@80 { >>> + compatible = "inside-secure,safexcel-eip197"; >>> + reg =

Re: [PATCH v3 1/3] Documentation/bindings: Document the SafeXel cryptographic engine driver

On Mon, May 22, 2017 at 03:48:30PM +0100, Marc Zyngier wrote: > On 22/05/17 15:30, Antoine Tenart wrote: > > On Wed, May 03, 2017 at 05:36:38PM +0100, Marc Zyngier wrote: > >> On 24/04/17 08:54, Antoine Tenart wrote: > >>> + > >>> + crypto: crypto@80 { > >>> + compatible =

Re: [PATCH v3 1/3] Documentation/bindings: Document the SafeXel cryptographic engine driver

Hi Marc, On Wed, May 03, 2017 at 05:36:38PM +0100, Marc Zyngier wrote: > On 24/04/17 08:54, Antoine Tenart wrote: > > + > > + crypto: crypto@80 { > > + compatible = "inside-secure,safexcel-eip197"; > > + reg = <0x80 0x20>; > > + interrupts = >

[PATCH v3 1/5] dt-bindings : Document the STM32F4 CRC32 binding

Add device tree binding for STM32F4. Signed-off-by: Cosar Dindar --- Documentation/devicetree/bindings/crypto/st,stm32-crc.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt

[PATCH v3 2/5] crypto : stm32 - Add STM32F4 CRC32 support

This patch adds CRC (CRC32 Crypto) support for STM32F4 series. As an hardware limitation polynomial and key setting are not supported. They are fixed as 0x4C11DB7 (poly) and 0x (key). CRC32C Castagnoli algorithm is not used. Signed-off-by: Cosar Dindar ---

[PATCH v5 0/4] arm64: marvell: add cryptographic engine support for 7k/8k

Hi all, This series adds support for the Inside Secure SafeXcel EIP197 cryptographic engine which can be found on Marvell Armada 7k and 8k boards. A new cryptographic engine driver is added, as well as the relevant device tree definition for the Armada 7040 DB and 8040 DB boards. This driver

[PATCH v5 3/4] MAINTAINERS: add a maintainer for the Inside Secure crypto driver

A new cryptographic engine driver was added in drivers/crypto/inside-secure. Add myself as a maintainer for this driver. Signed-off-by: Antoine Tenart --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index

[PATCH] crypto: rng: Remove unused function __crypto_rng_cast()

This fixes the following warning when building with clang: crypto/rng.c:35:34: error: unused function '__crypto_rng_cast' [-Werror,-Wunused-function] Signed-off-by: Matthias Kaehlcke --- crypto/rng.c | 5 - 1 file changed, 5 deletions(-) diff --git a/crypto/rng.c