This patch converts the i2c-cores driver to use devres routines for
resource allocation.
Signed-off-by: Jonas Bonn jo...@southpole.se
---
drivers/i2c/busses/i2c-ocores.c | 46 +-
1 files changed, 11 insertions(+), 35 deletions(-)
diff --git
Here are a couple of patches that fix up the initialization path of
the i2c-cores driver:
i) Support for device tree configuration of i2c devices
ii) Use devres routines in the resource reservation paths for device
initialization
This has been tested on an OpenRISC 1200 board; the OpenRISC
This patch adapts the i2c-ocores driver for being defined and configured via
a device tree description.
The device tree bits need to be protected by CONFIG_OF guards as this is
still an optional feature.
Signed-off-by: Jonas Bonn jo...@southpole.se
---
drivers/i2c/busses/i2c-ocores.c | 63
Hi,
quick review (hopefully not too quick)...
On Wed, Nov 24, 2010 at 03:09:48PM +0100, Jonas Bonn wrote:
This patch adapts the i2c-ocores driver for being defined and configured via
a device tree description.
The device tree bits need to be protected by CONFIG_OF guards as this is
still
From: Catalin Popescu catalinx.pope...@intel.com
The error messages printed from mrst_i2c_abort() didn't give slave address info.
But I2C device driver developers always need this to check which slave device
has the problem.
This patch enhances the error message format by adding slave address
From: Bin Yang bin.y...@intel.com
The old solution for i2c xfer timeout was to set timeout value to one second
for all i2c xfers. That's not reasonable for all of the various speed modes
and data lengths.
This patch sets the xfer_read timeout value based on both bus speed and data
length.
On Wed, Nov 24, 2010 at 7:09 AM, Jonas Bonn jo...@southpole.se wrote:
This patch adapts the i2c-ocores driver for being defined and configured via
a device tree description.
The device tree bits need to be protected by CONFIG_OF guards as this is
still an optional feature.
Signed-off-by:
On Wed, 2010-11-24 at 15:58 +0100, Wolfram Sang wrote:
Hi,
quick review (hopefully not too quick)...
Thanks... see my comments below.
+ val = (int*) of_get_property(pdev-dev.of_node, regstep, NULL);
+ if (!val) {
+ dev_err(pdev-dev, Missing required paramter 'regstep');
While I agree that these parameters need documentation, I haven't seen
that there is an agreed upon place to put such documentation as of yet.
I followed your link but didn't find the corresponding document in the
kernel tree.
Because it has not been applied yet; that was the template patch
This puts some documentation for the device tree configuration at the head
of the driver file. Hopefully this can get moved to a common area for this
type of documentation at a later date; unfortunately, there isn't really
such a place in the kernel tree at this time.
Furthermore, the regstep
Version 2 of patch series incorporating initial feedback from review.
/Jonas
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This patch converts the i2c-cores driver to use devres routines for
resource allocation.
Signed-off-by: Jonas Bonn jo...@southpole.se
---
drivers/i2c/busses/i2c-ocores.c | 46 +-
1 files changed, 11 insertions(+), 35 deletions(-)
diff --git
This patch adapts the i2c-ocores driver for being defined and configured via
a device tree description.
The device tree bits need to be protected by CONFIG_OF guards as this is
still an optional feature.
Signed-off-by: Jonas Bonn jo...@southpole.se
---
drivers/i2c/busses/i2c-ocores.c | 64
The reset functions sets writes the slave address even in not slave
mode. I don't see any reason in writting it if slave mode is not
enabled.
I have here a PXA-I2C variant where this register is not availbale and
as such can not be touched.
Signed-off-by: Sebastian Andrzej Siewior
The Sodaville I2C controller is almost the same as found on PXA2xx. The
difference:
- the register are at a different spot
- no slave support
The PCI probe code adds three platform devices which are probed then by
the platform code.
The X86 part also adds dummy clock defines because we don't have
Sodaville has three of them on a single IRQ. IRQF_DISABLED is removed
because it is a NOP allready and scheduled for removal.
Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
Signed-off-by: Dirk Brandewie dirk.brande...@gmail.com
---
drivers/i2c/busses/i2c-pxa.c | 10 --
I haven't seen this (yet) during a normal transfer but starting
i2cdetect seems to hang the bus. On my Sodaville board, i2cdetect runs
fine on bus zero and runs into timeouts on bus one and two. The chip
never recovers from this condition. The following transfers hang as
well. The ISR_UB never
This patch moves the register definitions into include/asm so it can be
accessed from X86 the same way as on ARM. This move also alters the
unused register offset definitins (IBMR, ...) and uses them in the
calculation macros (_IBMR,...).
The header file from plat-pxa is moved the include/linux
the of_node will auto-publish devices which are added to the device
tree.
Cc: grant.lik...@secretlab.ca
Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
Signed-off-by: Dirk Brandewie dirk.brande...@gmail.com
---
drivers/i2c/busses/i2c-pxa.c |3 +++
1 files changed, 3
Right now i2c adapter 5 becomes minor 5 allocated. This is fine as long
as no adapter becomes a number 256 allocated.
The Sodavile PCI driver uses (devfn 3 | pci_bar) to come up with an
unique adapter number. So the first i2c adapter has the number 720.
This patch introduces dynamic minor
Hi Sebastian,
On Wed, 24 Nov 2010 22:23:08 +0100, Sebastian Andrzej Siewior wrote:
Right now i2c adapter 5 becomes minor 5 allocated. This is fine as long
as no adapter becomes a number 256 allocated.
Why would it be a problem to have a minor number 256 (or more likely
you meant 255)?
On Thu, Nov 25, 2010 at 5:20 AM, Sebastian Andrzej Siewior
bige...@linutronix.de wrote:
Sodaville has three of them on a single IRQ. IRQF_DISABLED is removed
because it is a NOP allready and scheduled for removal.
Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
Signed-off-by:
On Thu, Nov 25, 2010 at 5:20 AM, Sebastian Andrzej Siewior
bige...@linutronix.de wrote:
I haven't seen this (yet) during a normal transfer but starting
i2cdetect seems to hang the bus. On my Sodaville board, i2cdetect runs
fine on bus zero and runs into timeouts on bus one and two. The chip
On Thu, Nov 25, 2010 at 2:43 PM, Igor Grinberg grinb...@compulab.co.il wrote:
Hi,
On 11/25/10 04:49, Haojian Zhuang wrote:
On Thu, Nov 25, 2010 at 10:30 AM, Haojian Zhuang
haojian.zhu...@gmail.com wrote:
On Thu, Nov 25, 2010 at 5:20 AM, Sebastian Andrzej Siewior
bige...@linutronix.de
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