Tony == Luck, Tony [EMAIL PROTECTED] writes:
Anyway, it seems that lcrash at least only accesses the memory
using read() and write()? which means it is relatively easy to
using a struct page flag to do uncached vs cached access on the
fly. mmap on the other hand would be a bit of a nightmare
David == David Mosberger [EMAIL PROTECTED] writes:
On Mon, 14 Feb 2005 11:12:54 -0800, Luck, Tony [EMAIL PROTECTED] said:
Tony If so, the PG_arch_1 might have to be the solution
David Note that PG_arch_1 is already being used as a i-cache
David coherent flag.
Ahh, so not totally off. It's
On Tue, 15 Feb 2005, Christoph Hellwig wrote:
I tried to do that, for some reason the first patch (0/1) didn't make it
to the mailing list.Is it important to separate the #include lines
as well as the actual file moves?
In general we prefer to have separate patches for just moving
On Tue, Feb 15, 2005 at 03:43:10AM -0500, Jes Sorensen wrote:
None of the ones I know well have this problem, but I have little
knowledge about this level of stuff on most architectures. The ones
that could have issues would probably be like PPC, PARISC and maybe
Alpha .
With parisc 2.0
On 15 Feb 2005 03:44:26 -0500, Jes Sorensen [EMAIL PROTECTED] said:
Jes Ahh, so not totally off. It's also used for internal debugging
Jes in reiser4, but I'll happily ignore that while waving the
Jes 'friends don't let friends run reiser4' flag ;)
What are they smoking? Which part of
On Tue, 15 Feb 2005 06:02:13 -0600, Robin Holt [EMAIL PROTECTED] said:
Robin For the 4-level case with 64k pages, what about just using
Robin 16k page tables? That leaves us with 60 bits of addressable
Robin space which is fairly close to the full space.
You're kidding, right? If
Robin For the 4-level case with 64k pages, what about just using
Robin 16k page tables? That leaves us with 60 bits of addressable
Robin space which is fairly close to the full space.
David You're kidding, right? If getting fairly close to 64 bits was good
David enough, there would be no point
On Tue, Feb 15, 2005 at 10:04:49AM -0800, David Mosberger wrote:
On 15 Feb 2005 03:43:10 -0500, Jes Sorensen [EMAIL PROTECTED] said:
Tony == Luck, Tony [EMAIL PROTECTED] writes:
Tony Is ia64 the only architecture that has uncached vs. cached
Tony access issues? If so, the PG_arch_1
On Tue, 15 Feb 2005 13:11:20 -0600, Robin Holt [EMAIL PROTECTED] said:
Robin We saw many silent data corruptions. The SN2 hardware will
Robin give an MCA if both types of references are made by the cpu
Robin at about the same time, but that depends on both transactions
Robin being on the
On Tue, Feb 15, 2005 at 12:03:22PM -0800, David Mosberger wrote:
On Tue, 15 Feb 2005 13:59:45 -0600, Robin Holt [EMAIL PROTECTED] said:
I certainly don't want to switch my machines to 4-levels. There
is zero need for that on the machines I use, so why pay the
overhead of an extra
On Tue, Feb 15, 2005 at 03:02:01PM -0500, Jes Sorensen wrote:
Robin == Robin Holt [EMAIL PROTECTED] writes:
Robin Would anybody have a concern with marking those cache lines as
Robin processor uncached only? Would there ever be a time that we
Robin would expect _ANY_ type of cached
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