When hot-adding/removing memory, sync_global_pgds() is called for
synchronizing PGD to PGD entries of all processes MM. But when
hot-removing memory, sync_global_pgds() does not work correctly.
At first, sync_global_pgds() checks whether target PGD is none or not.
And if PGD is none, the PGD is
We need to allocate boot_params early and clear it before copy
setup_header to it.
So kernel will not call sanitize_boot_params() to overwrite new
added parameter like ext_ramdisk_image, ext_ramdisk_size...
We should modify boot_params later instead of touch temp buf too early.
Signed-off-by:
When hot-adding memory after hot-removing memory, following call traces
are shown:
kernel BUG at arch/x86/mm/init_64.c:206!
...
[] kernel_physical_mapping_init+0x1b2/0x1d2
[] init_memory_mapping+0x1d4/0x380
[] arch_add_memory+0x3d/0xd0
[] add_memory+0xb9/0x1b0
[]
We could load it high if it is more than 2G when kernel support
LOAD_ABOVE_4G.
Signed-off-by: Yinghai Lu
---
loaders/bzimage/bzimage.c |9 -
loaders/bzimage/bzimage.h |8 ++--
2 files changed, 14 insertions(+), 3 deletions(-)
Index: efilinux/loaders/bzimage/bzimage.c
On Wed, Jun 11, 2014 at 02:51:20AM +0800, Murali Karicheri wrote:
> v3.65 version of the designware h/w, requires application space
> registers to be configured to access the remote EP config space.
> To support this, add rd[wr]_other_conf API in the pcie_host_opts
>
> Signed-off-by: Murali
remove_pagetable() gets start argument and passes the argument to
sync_global_pgds(). In this case, the argument must not be modified.
If the argument is modified and passed to sync_global_pgds(),
sync_global_pgds() does not correctly synchronize PGD to PGD entries
of all processes MM since
From: Zhang Yanmin
ChangeLog V4: Explain the patch sceanrio clearly
ChangeLog V3: Keep rsp pointing to pt_regs before sysexit.
ChangeLog V2: Before sysexit, perf NMI might arrive. There is
still a race. Here we change rsp to keep it pointing
to
On 06/17/2014 05:18 PM, Paul E. McKenney wrote:
> So if I understand correctly, a goodly part of the regression is due not
> to the overhead added to cond_resched(), but rather because grace periods
> are now happening faster, thus incurring more overhead. Is that correct?
Yes, that's the theory
On Wed, Jun 18, 2014 at 09:29:35AM +0900, Joonsoo Kim wrote:
> commit 'b1cb098: change the management method of free objects of the slab'
> introduces bug on slab leak detector('/proc/slab_allocators'). This
> detector works like as following decription.
>
> 1. traverse all objects on all the
This series adds support for XHCI on NVIDIA Tegra SoCs. This includes:
- extending the XUSB pad controller driver to support the USB PHY
types (UTMI, HSIC, and USB3),
- adding a driver for the mailbox used to communicate with the XHCI
controller's firmware, and
- adding a XHCI
Add device-tree binding documentation for the XHCI controller present
on Tegra124 and later SoCs.
Signed-off-by: Andrew Bresticker
---
.../bindings/usb/nvidia,tegra124-xhci.txt | 76 ++
1 file changed, 76 insertions(+)
create mode 100644
Add device-tree bindings for the Tegra XUSB mailbox which will be used
for communication between the Tegra XHCI controller and the host.
Signed-off-by: Andrew Bresticker
---
.../bindings/mailbox/nvidia,tegra124-xusb-mbox.txt | 25 ++
1 file changed, 25 insertions(+)
create
Hi Naveen,
On 06/18/2014 03:12 PM, Naveen Krishna Ch wrote:
> Hello Chanwoo,
>
> On 18 June 2014 07:51, Chanwoo Choi wrote:
>> This patch add DT binding documentation for Exynos3250 ADC IP. Exynos3250 has
>> special clock ('sclk_tsadc') for ADC which provide clock to internal ADC.
>>
>>
On 06/18/2014 11:42 AM, Guenter Roeck wrote:
On 06/17/2014 10:46 PM, Varka Bhadram wrote:
Hi,
On 06/18/2014 11:07 AM, Heiko Schocher wrote:
Driver for the TI TMP103.
The TI TMP103 is similar to the TMP102. It differs from the TMP102
by having only 8 bit registers.
Signed-off-by: Heiko
From: Sam Ravnborg
Date: Sun, 15 Jun 2014 20:56:35 +0200
> This is a regression so we should either revert the above commit
> or review and fix the remaining drivers.
I plan to review and integrate the sparc serial driver fixes
soon.
--
To unsubscribe from this list: send the line "unsubscribe
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is mapped to one of the three UTMI ports.
Signed-off-by: Andrew Bresticker
---
drivers/pinctrl/pinctrl-tegra-xusb.c | 1106
Add support for the on-chip XHCI host controller present on Tegra SoCs.
The driver is currently very basic: it loads the controller with its
firmware, starts the controller, and is able to service messages sent
by the controller's firmware. The hardware supports device mode as
well as runtime
Add nodes for the Tegra XUSB mailbox and Tegra XHCI controller.
Update the XUSB pad controller node with a phandle to the XUSB
mailbox.
Signed-off-by: Andrew Bresticker
---
arch/arm/boot/dts/tegra124.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git
Assign USB ports previously owned by the EHCI controllers to the XHCI
controller. There is a mini-PCIe USB port (UTMI port 1) and a USB A
connector (UTMI port 2, USB3 port 0). PCIe lane 0 is used for USB3
port 0.
Signed-off-by: Andrew Bresticker
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts |
The Tegra XHCI controller communicates requests to the host through
a mailbox interface. Host drivers which can handle these requests,
such as the Tegra XUSB pad controller driver and upcoming Tegra XHCI
host controller driver, can send messages and register to be notified
of incoming messages.
Hello Varka,
Am 18.06.2014 07:46, schrieb Varka Bhadram:
Hi,
On 06/18/2014 11:07 AM, Heiko Schocher wrote:
Driver for the TI TMP103.
The TI TMP103 is similar to the TMP102. It differs from the TMP102
by having only 8 bit registers.
Signed-off-by: Heiko Schocher
---
Cc: Jean Delvare
Cc:
Assign ports previously owned by the EHCI controllers to the XHCI
controller. There are two external USB ports (UTMI ports 0/2 and
USB3 ports 0/1) and an internal USB port (UTMI port 1). PCIe lanes
0 and 1 are used by the USB3 ports.
Signed-off-by: Andrew Bresticker
---
Add new bindings used for USB support by the Tegra XUSB pad controller.
This includes additional PHY types, USB-specific pinconfig properties, etc.
Signed-off-by: Andrew Bresticker
---
.../pinctrl/nvidia,tegra124-xusb-padctl.txt| 53 --
On 06/17/2014 10:37 PM, Heiko Schocher wrote:
Driver for the TI TMP103.
The TI TMP103 is similar to the TMP102. It differs from the TMP102
by having only 8 bit registers.
Signed-off-by: Heiko Schocher
Looks pretty good now. Applied.
Thanks,
Guenter
--
To unsubscribe from this list: send
Hello Chanwoo,
On 18 June 2014 07:51, Chanwoo Choi wrote:
> This patch add DT binding documentation for Exynos3250 ADC IP. Exynos3250 has
> special clock ('sclk_tsadc') for ADC which provide clock to internal ADC.
>
> Signed-off-by: Chanwoo Choi
> Acked-by: Kyungmin Park
Changes look good to
On Wed, Jun 18, 2014 at 01:50:00PM +0800, Tang Chen wrote:
> [Questions]
> And by the way, would you guys please answer the following questions for me ?
>
> 1. What's the ept identity pagetable for ? Only one page is enough ?
>
> 2. Is the ept identity pagetable only used in realmode ?
>Can
On 06/17/2014 10:46 PM, Varka Bhadram wrote:
Hi,
On 06/18/2014 11:07 AM, Heiko Schocher wrote:
Driver for the TI TMP103.
The TI TMP103 is similar to the TMP102. It differs from the TMP102
by having only 8 bit registers.
Signed-off-by: Heiko Schocher
---
Cc: Jean Delvare
Cc: Guenter
On 06/17/2014 10:46 PM, Varka Bhadram wrote:
Hi,
On 06/18/2014 11:07 AM, Heiko Schocher wrote:
Driver for the TI TMP103.
The TI TMP103 is similar to the TMP102. It differs from the TMP102
by having only 8 bit registers.
Signed-off-by: Heiko Schocher h...@denx.de
---
Cc: Jean Delvare
On Wed, Jun 18, 2014 at 01:50:00PM +0800, Tang Chen wrote:
[Questions]
And by the way, would you guys please answer the following questions for me ?
1. What's the ept identity pagetable for ? Only one page is enough ?
2. Is the ept identity pagetable only used in realmode ?
Can we
Hello Chanwoo,
On 18 June 2014 07:51, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch add DT binding documentation for Exynos3250 ADC IP. Exynos3250 has
special clock ('sclk_tsadc') for ADC which provide clock to internal ADC.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by:
On 06/17/2014 10:37 PM, Heiko Schocher wrote:
Driver for the TI TMP103.
The TI TMP103 is similar to the TMP102. It differs from the TMP102
by having only 8 bit registers.
Signed-off-by: Heiko Schocher h...@denx.de
Looks pretty good now. Applied.
Thanks,
Guenter
--
To unsubscribe from
Add new bindings used for USB support by the Tegra XUSB pad controller.
This includes additional PHY types, USB-specific pinconfig properties, etc.
Signed-off-by: Andrew Bresticker abres...@chromium.org
---
.../pinctrl/nvidia,tegra124-xusb-padctl.txt| 53 --
Assign ports previously owned by the EHCI controllers to the XHCI
controller. There are two external USB ports (UTMI ports 0/2 and
USB3 ports 0/1) and an internal USB port (UTMI port 1). PCIe lanes
0 and 1 are used by the USB3 ports.
Signed-off-by: Andrew Bresticker abres...@chromium.org
---
Hello Varka,
Am 18.06.2014 07:46, schrieb Varka Bhadram:
Hi,
On 06/18/2014 11:07 AM, Heiko Schocher wrote:
Driver for the TI TMP103.
The TI TMP103 is similar to the TMP102. It differs from the TMP102
by having only 8 bit registers.
Signed-off-by: Heiko Schocher h...@denx.de
---
Cc: Jean
Assign USB ports previously owned by the EHCI controllers to the XHCI
controller. There is a mini-PCIe USB port (UTMI port 1) and a USB A
connector (UTMI port 2, USB3 port 0). PCIe lane 0 is used for USB3
port 0.
Signed-off-by: Andrew Bresticker abres...@chromium.org
---
The Tegra XHCI controller communicates requests to the host through
a mailbox interface. Host drivers which can handle these requests,
such as the Tegra XUSB pad controller driver and upcoming Tegra XHCI
host controller driver, can send messages and register to be notified
of incoming messages.
Add nodes for the Tegra XUSB mailbox and Tegra XHCI controller.
Update the XUSB pad controller node with a phandle to the XUSB
mailbox.
Signed-off-by: Andrew Bresticker abres...@chromium.org
---
arch/arm/boot/dts/tegra124.dtsi | 31 +++
1 file changed, 31
Add support for the on-chip XHCI host controller present on Tegra SoCs.
The driver is currently very basic: it loads the controller with its
firmware, starts the controller, and is able to service messages sent
by the controller's firmware. The hardware supports device mode as
well as runtime
From: Sam Ravnborg s...@ravnborg.org
Date: Sun, 15 Jun 2014 20:56:35 +0200
This is a regression so we should either revert the above commit
or review and fix the remaining drivers.
I plan to review and integrate the sparc serial driver fixes
soon.
--
To unsubscribe from this list: send the
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is mapped to one of the three UTMI ports.
Signed-off-by: Andrew Bresticker abres...@chromium.org
---
On 06/18/2014 11:42 AM, Guenter Roeck wrote:
On 06/17/2014 10:46 PM, Varka Bhadram wrote:
Hi,
On 06/18/2014 11:07 AM, Heiko Schocher wrote:
Driver for the TI TMP103.
The TI TMP103 is similar to the TMP102. It differs from the TMP102
by having only 8 bit registers.
Signed-off-by: Heiko
Hi Naveen,
On 06/18/2014 03:12 PM, Naveen Krishna Ch wrote:
Hello Chanwoo,
On 18 June 2014 07:51, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch add DT binding documentation for Exynos3250 ADC IP. Exynos3250 has
special clock ('sclk_tsadc') for ADC which provide clock to internal ADC.
Add device-tree bindings for the Tegra XUSB mailbox which will be used
for communication between the Tegra XHCI controller and the host.
Signed-off-by: Andrew Bresticker abres...@chromium.org
---
.../bindings/mailbox/nvidia,tegra124-xusb-mbox.txt | 25 ++
1 file changed, 25
Add device-tree binding documentation for the XHCI controller present
on Tegra124 and later SoCs.
Signed-off-by: Andrew Bresticker abres...@chromium.org
---
.../bindings/usb/nvidia,tegra124-xhci.txt | 76 ++
1 file changed, 76 insertions(+)
create mode 100644
This series adds support for XHCI on NVIDIA Tegra SoCs. This includes:
- extending the XUSB pad controller driver to support the USB PHY
types (UTMI, HSIC, and USB3),
- adding a driver for the mailbox used to communicate with the XHCI
controller's firmware, and
- adding a XHCI
On Wed, Jun 18, 2014 at 09:29:35AM +0900, Joonsoo Kim wrote:
commit 'b1cb098: change the management method of free objects of the slab'
introduces bug on slab leak detector('/proc/slab_allocators'). This
detector works like as following decription.
1. traverse all objects on all the slabs.
On 06/17/2014 05:18 PM, Paul E. McKenney wrote:
So if I understand correctly, a goodly part of the regression is due not
to the overhead added to cond_resched(), but rather because grace periods
are now happening faster, thus incurring more overhead. Is that correct?
Yes, that's the theory at
From: Zhang Yanmin yanmin.zh...@intel.com
ChangeLog V4: Explain the patch sceanrio clearly
ChangeLog V3: Keep rsp pointing to pt_regs before sysexit.
ChangeLog V2: Before sysexit, perf NMI might arrive. There is
still a race. Here we change rsp to keep it pointing
remove_pagetable() gets start argument and passes the argument to
sync_global_pgds(). In this case, the argument must not be modified.
If the argument is modified and passed to sync_global_pgds(),
sync_global_pgds() does not correctly synchronize PGD to PGD entries
of all processes MM since
On Wed, Jun 11, 2014 at 02:51:20AM +0800, Murali Karicheri wrote:
v3.65 version of the designware h/w, requires application space
registers to be configured to access the remote EP config space.
To support this, add rd[wr]_other_conf API in the pcie_host_opts
Signed-off-by: Murali Karicheri
We need to allocate boot_params early and clear it before copy
setup_header to it.
So kernel will not call sanitize_boot_params() to overwrite new
added parameter like ext_ramdisk_image, ext_ramdisk_size...
We should modify boot_params later instead of touch temp buf too early.
Signed-off-by:
When hot-adding memory after hot-removing memory, following call traces
are shown:
kernel BUG at arch/x86/mm/init_64.c:206!
...
[815e0c80] kernel_physical_mapping_init+0x1b2/0x1d2
[815ced94] init_memory_mapping+0x1d4/0x380
[8104aebd] arch_add_memory+0x3d/0xd0
We could load it high if it is more than 2G when kernel support
LOAD_ABOVE_4G.
Signed-off-by: Yinghai Lu ying...@kernel.org
---
loaders/bzimage/bzimage.c |9 -
loaders/bzimage/bzimage.h |8 ++--
2 files changed, 14 insertions(+), 3 deletions(-)
Index:
When hot-adding/removing memory, sync_global_pgds() is called for
synchronizing PGD to PGD entries of all processes MM. But when
hot-removing memory, sync_global_pgds() does not work correctly.
At first, sync_global_pgds() checks whether target PGD is none or not.
And if PGD is none, the PGD is
On 06/17/2014 11:18 PM, Varka Bhadram wrote:
ti,tmp102Low Power Digital Temperature Sensor with SMBUS/Two Wire
Serial Interface
+ti,tmp103Low Power Digital Temperature Sensor with SMBUS/Two Wire
Serial Interface
May i know about this binding compatible property ?
At some
Hi Gleb,
Thanks for the quick reply. Please see below.
On 06/18/2014 02:12 PM, Gleb Natapov wrote:
On Wed, Jun 18, 2014 at 01:50:00PM +0800, Tang Chen wrote:
[Questions]
And by the way, would you guys please answer the following questions for me ?
1. What's the ept identity pagetable for ?
On 06/18/2014 11:46 AM, Heiko Schocher wrote:
Hello Varka,
Am 18.06.2014 07:46, schrieb Varka Bhadram:
Hi,
On 06/18/2014 11:07 AM, Heiko Schocher wrote:
Driver for the TI TMP103.
The TI TMP103 is similar to the TMP102. It differs from the TMP102
by having only 8 bit registers.
On 2014/6/17 16:01, Luca Abeni wrote:
Hi,
On 06/17/2014 04:43 AM, xiaofeng.yan wrote:
[...]
The basic ideas are (warning! This is an over-simplification of the
algorithm! :)
- You assign runtime and period to each SCHED_DEADLINE task as usual
- Each task is guaranteed to receive its runtime
Hi Murali,
On Wed, Jun 11, 2014 at 02:51:21AM +0800, Murali Karicheri wrote:
Current DW PCI host init code has code specific to newer hw such as
ATU port specific resource parsing and map. v3.65 DW PCI host has
OK, Older version did not had standard viewport implementation, so patch 1
of this
On 06/18/2014 11:46 AM, Heiko Schocher wrote:
Hello Varka,
Am 18.06.2014 07:46, schrieb Varka Bhadram:
Hi,
On 06/18/2014 11:07 AM, Heiko Schocher wrote:
Driver for the TI TMP103.
The TI TMP103 is similar to the TMP102. It differs from the TMP102
by having only 8 bit registers.
On 06/18/14 05:44, Jens Axboe wrote:
Thanks for posting these numbers, Bart. The CPU utilization and IOPS
speak a very clear message. The only mystery is why the singe threaded
performance is down. That we need to get sort, but it's not a show
stopper for inclusion.
If you run the single
On 17/06/2014 22:44, Maxime Ripard wrote:
On Tue, Jun 17, 2014 at 09:38:40AM +0200, Boris BREZILLON wrote:
The init_data and of_node fields of the axp2xx_matches tables are filled
at each device probe by the axp20x_regulator_parse_dt function (which then
calls the of_regulator_match
On 17/06/2014 22:46, Maxime Ripard wrote:
On Tue, Jun 17, 2014 at 09:38:42AM +0200, Boris BREZILLON wrote:
Make use of the devm_regulator_set_register instead of registering each
regulator provided by the PMIC.
This also solves a self dependency issue where one regulator of the PMIC
is used
Hello Murali,
-Original Message-
From: Murali Karicheri [mailto:m-kariche...@ti.com]
Sent: Wednesday, June 11, 2014 12:21 AM
To: linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux-
d...@vger.kernel.org
Hello Murali,
-Original Message-
From: Murali Karicheri [mailto:m-kariche...@ti.com]
Sent: Wednesday, June 11, 2014 12:21 AM
To: linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux-
d...@vger.kernel.org
On 18/6/2014 5:11 πμ, Jens Axboe wrote:
On 2014-06-17 14:35, Konstantinos Skarlatos wrote:
Hi all,
with 3.16-rc1 rsync stops writing to my btrfs filesystem and stays at a
D+ state.
git bisect showed that the problematic commit is:
762380ad9322951cea4ce9d24864265f9c66a916 is the first bad
Add palmas_pmic_driver_data structure.
Signed-off-by: Keerthy j-keer...@ti.com
---
include/linux/mfd/palmas.h | 25 +
1 file changed, 25 insertions(+)
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index 8d68452..70f0695 100644
---
Hello,
On 17/06/2014 18:41, Alexandre Belloni wrote:
Hi,
This patch set fixes more issues with the clocks on AT91:
The first patch define the slow crystal on the at91sam9261ek board
The next patchs are moving all the clocks that were under the root under a
clocks node to be consistent
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
When communicating with the EC, the cmd_xfer() function should return the
number of bytes it received from the EC, or negative on error.
Signed-off-by: Bill Richardson wfric...@chromium.org
On Tue, 17 Jun 2014, Doug Anderson wrote:
Simon,
On Tue, Jun 17, 2014 at 8:43 PM, Simon Glass s...@chromium.org wrote:
diff --git a/drivers/mfd/cros_ec_spi.c b/drivers/mfd/cros_ec_spi.c
index 09ca789..4d34f1c 100644
--- a/drivers/mfd/cros_ec_spi.c
+++ b/drivers/mfd/cros_ec_spi.c
@@
On Tue, Jun 17, 2014 at 07:41:44PM +0300, Janne Kanniainen wrote:
This driver adds support for USB controlled led panels that exists in
MSI GT683R laptop
Changes in v2:
- sorted headers to alphabetic order
- using devm_kzalloc
- using BIT(n)
- using usb_control_msg
On 18 June 2014 03:17, micky micky_ch...@realsil.com.cn wrote:
On 06/17/2014 03:45 PM, Ulf Hansson wrote:
On 17 June 2014 03:04, micky micky_ch...@realsil.com.cn wrote:
On 06/16/2014 08:40 PM, Ulf Hansson wrote:
On 16 June 2014 11:09, micky micky_ch...@realsil.com.cn wrote:
On 06/16/2014
diff --git a/drivers/input/keyboard/cros_ec_keyb.c
b/drivers/input/keyboard/cros_ec_keyb.c
index 4083796..dc37b6b 100644
--- a/drivers/input/keyboard/cros_ec_keyb.c
+++ b/drivers/input/keyboard/cros_ec_keyb.c
@@ -191,8 +191,18 @@ static void cros_ec_keyb_close(struct input_dev *dev)
On 18 June 2014 05:42, Aaron Plattner aplatt...@nvidia.com wrote:
Commit bd0fa9bb455d introduced a failure path to cpufreq_update_policy() if
cpufreq_driver-get(cpu) returns NULL. However, it jumps to the 'no_policy'
label, which exits without unlocking any of the locks the function acquired
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
struct cros_ec_device has a superfluous name field. We can get all the
debugging info we need from the existing ec_name and phys_name fields, so
let's take out the extra field.
Signed-off-by: Bill
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
This is some internal structure reorganization / renaming to prepare
for future patches that will add a userspace API to cros_ec. There
should be no visible changes.
Signed-off-by: Bill Richardson
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Simon Glass s...@chromium.org
Some commands take a while to execute. Use -EAGAIN to signal this to the
caller.
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/mfd/cros_ec_spi.c
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
The members of struct cros_ec_device were improperly commented, and
intermixed the private and public sections. This is just cleanup to make it
more obvious what goes with what.
[dianders: left lock in
On Tue, Jun 17, 2014 at 6:47 AM, Alexei Starovoitov
alexei.starovoi...@gmail.com wrote:
On Mon, Jun 16, 2014 at 7:18 AM, Michal Marek mma...@suse.cz wrote:
When $srctree or $objtree are relative paths, we cannot change directory
and refer to them in the same subshell. Do the redirection outside
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
The lower-level driver may want to provide its own buffers. If so,
there's no need to allocate new ones. This already happens to work
just fine (since we check for size of 0 and use devm allocation), but
Hi Chanwoo,
On 18.06.2014 04:20, Chanwoo Choi wrote:
This patchset add 'exynos_adc_ops' structure which includes some functions
to control ADC operation according to ADC version (v1 or v2).
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
Preparing the way for the LPC device, which is just a plaform_device without
interrupts.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Doug Anderson diand...@chromium.org
---
On Fri, 2014-06-06 at 15:38 +0900, Masami Hiramatsu wrote:
Ping?
I guess this should go to 3.16 branch, shouldn't it?
diff --git a/arch/powerpc/include/asm/types.h
b/arch/powerpc/include/asm/types.h
index bfb6ded..8b89d65 100644
--- a/arch/powerpc/include/asm/types.h
+++
On Mon, 16 Jun 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
This comment was incorrect, so update it.
Signed-off-by: Bill Richardson wfric...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
How many people did it take to write this patch? ;)
Acked-by:
On 06/06/2014 06:44 PM, Alexey Kardashevskiy wrote:
Here is what I got for powernv in order to support variable page size
in iommu_table.
I am very uncertain about Patch #4 Add @it_owner to iommu_table struct
and wonder if there any better way to get PE from iommu_table.
Please comment.
+ Rajendra, Nishant and Kevin.
as you were mentioned in the discussion.
cheers,
-roger
On 06/15/2014 06:33 AM, Paul Walmsley wrote:
On Fri, 13 Jun 2014, Paul Walmsley wrote:
Hi Roger,
On Wed, 23 Apr 2014, Roger Quadros wrote:
From: Nikhil Devshatwar nikhil...@ti.com
Add hwmods for
On Wed, 18 Jun 2014, Alexander Shiyan wrote:
Tue, 17 Jun 2014 21:04:59 +0100 от Lee Jones lee.jo...@linaro.org:
On Sat, 07 Jun 2014, Alexander Shiyan wrote:
This patch convert mc13xxx MFD driver to use regmap irq framework
for interrupt registration.
Signed-off-by: Alexander
Hi Chanwoo,
On 18.06.2014 04:20, Chanwoo Choi wrote:
This patch control special clock for ADC in Exynos series's FSYS block.
If special clock of ADC is registerd on clock list of common clk framework,
Exynos ADC drvier have to control this clock.
Exynos3250/Exynos4/Exynos5 has 'adc' clock
Hi,
On Tue, Jun 17, 2014 at 9:36 PM, Fabian Frederick f...@skynet.be wrote:
Fix checkpatch warning:
WARNING: kfree(NULL) is safe this check is probably not required
Thanks Fabian.
This should go through the wireless tree I guess, mind to send to
linux-wirel...@vger.kernel.org?
Helmut
Cc: Ivo
On Mon, 16 Jun 2014, Ulf Hansson wrote:
On 16 June 2014 14:20, Lee Jones lee.jo...@linaro.org wrote:
From: Micky Ching micky_ch...@realsil.com.cn
rtsx driver using a single function for transfer data, dma map/unmap are
placed in one fix function. We need map/unmap dma in different
On 04/23/2014 08:35 PM, Roger Quadros wrote:
From: Nikhil Devshatwar nikhil...@ti.com
Add hwmods for ocp2scp3 and sata modules.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
CC: Paul Walmsley p...@pwsan.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Nikhil
it should go
through James Morris' tree. CCed.
http://lkml.kernel.org/r/20131112182746.ga22...@gondor.apana.org.au
Unless akpm picks it up first. Also CCed.
This oneliner is neither part of v3.16-rc1 nor part of linux-next. It
applies cleanly to next-20140618. Should I hope that Jiri Kosina wants
The existing CFQ default target_latency results in very poor performance
for larger numbers of threads doing sequential reads. While this can be
easily described as a tuning problem for users, it is one that is tricky
to detect. This patch the default on the assumption that people with access
to
IO performance since 3.0 has been a mixed bag. In many respects we are
better and in some we are worse and one of those places is sequential read
performance, particularly for higher numbers of threads. This is visible
in a number of benchmarks but tiobench has been the one I looked at the
closest
When allocating a page cache page for writing the allocator makes an attempt
to proportionally distribute dirty pages between populated zones. The call
to zone_dirty_ok is more expensive than expected because of the number of
vmstats it examines. This patch caches some of that information to
From: Anil Belur ask...@gmail.com
fixed WARNING: labels should not be indented
Signed-off-by: Anil Belur ask...@gmail.com
---
drivers/staging/lustre/lustre/lclient/glimpse.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/lustre/lustre/lclient/glimpse.c
reworked patch 8/8 7/8 and 3/8, fixed changes recomemded by
andreas.dil...@intel.com
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From: Anil Belur ask...@gmail.com
fixed warning:
* WARNING: min() should probably be min_t(__u32, desc.ld_tgt_count,
LOV_MAX_STRIPE_COUNT)
Signed-off-by: Anil Belur ask...@gmail.com
---
drivers/staging/lustre/lustre/lclient/lcommon_misc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Anil Belur ask...@gmail.com
Fixed ERROR: need consistent spacing around '+' (ctx:WxV)
Signed-off-by: Anil Belur ask...@gmail.com
---
drivers/staging/lustre/lustre/lclient/glimpse.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Anil Belur ask...@gmail.com
fixed: WARNING: suspect code indent for conditional statements (32, 32)
Signed-off-by: Anil Belur ask...@gmail.com
---
drivers/staging/lustre/lustre/lclient/lcommon_cl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
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