On 2/11/16, Christophe Leroy wrote:
> This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture.
> PPC32 doesn't have the PACA structure, so we use the task_info
> structure to store the accounting data.
>
> In order to reuse on PPC32 the PPC64 functions, all u64 data has
> been replaced by
On Wed, 2016-02-10 at 17:25 +0100, Torsten Duwe wrote:
snip
> diff --git a/arch/powerpc/gcc-mprofile-kernel-notrace.sh
> b/arch/powerpc/gcc-mprofile-kernel-notrace.sh
> new file mode 100755
> index 000..68d6482
> --- /dev/null
> +++ b/arch/powerpc/gcc-mprofile-kernel-notrace.sh
> @@ -0,0
Daniel,
I do confirm that this hacky patch:
https://lkml.org/lkml/2016/1/19/637
works around my issue. I understand that this is improper fix, so let me
know how could I debug my issue further.
Thanks.
09.02.2016 12:11, Daniel Vetter wrote:
Can you please retest with latest -rc? There's
From: Joonsoo Kim
Current implementation of pfmemalloc handling in SLAB has some problems.
1) pfmemalloc_active is set to true when there is just one or more
pfmemalloc slabs in the system, but it is cleared when there is
no pfmemalloc slab in one arbitrary kmem_cache. So, pfmemalloc_active
I recently noticed with 4.4 based kernel's Android's userspace wasn't
able to properly detect micro-SD cards when they were inserted.
This is due to vold not being able to access
/sys/module/mmcblk/parameters/perdev_minors
See: http://androidxref.com/6.0.1_r10/xref/system/vold/Disk.cpp#49
This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture.
PPC32 doesn't have the PACA structure, so we use the task_info
structure to store the accounting data.
In order to reuse on PPC32 the PPC64 functions, all u64 data has
been replaced by 'unsigned long' so that it is u32 on PPC32 and
u64
On 02/10/2016 10:01 PM, Arnd Bergmann wrote:
> On Tuesday 09 February 2016 09:42:26 Andrzej Hajda wrote:
>> +cc Rasmus Villemoes, I forgot to add him earlier.
>>
>> On 02/08/2016 01:01 PM, Arnd Bergmann wrote:
>>> On Monday 08 February 2016 09:45:55 Andrzej Hajda wrote:
On 02/05/2016 11:52
Hi Guenter,
On Tue, Feb 09, 2016 at 07:08:59AM -0800, Guenter Roeck wrote:
> IS_ERR_VALUE() assumes that its parameter is an unsigned long.
> It can not be used to check if an unsigned int reflects an error.
> Doing so can result in the following build warning.
>
>
On 02/11/2016 04:38 AM, Guenter Roeck wrote:
> On 02/10/2016 07:21 AM, Arnd Bergmann wrote:
>> On Tuesday 09 February 2016 18:37:46 Guenter Roeck wrote:
>>> On 02/09/2016 07:26 AM, Arnd Bergmann wrote:
On Tuesday 09 February 2016 07:08:59 Guenter Roeck wrote:
> IS_ERR_VALUE() assumes that
On 02/10/2016 07:10 PM, Anton Protopopov wrote:
> The iwl_trans_pcie_start_fw() function may return the positive value EIO
> instead of -EIO in case of error.
>
> Signed-off-by: Anton Protopopov
> ---
> drivers/net/wireless/intel/iwlwifi/pcie/trans.c | 2 +-
> 1 file changed, 1 insertion(+), 1
> xilinx_pcie_init_port clears the pending interrupts in the interrupt decode
> register, but does not clear the interrupt FIFO. This would lead to spurious
> interrupts if any were present in the FIFO at probe time.
> Clear the interrupt FIFO prior to the interrupt decode register in order to
>
thanks for your reply.
It works as expected.
is it going to be submitted?
Thanks,
Soohoon.
From: Arnd Bergmann
Sent: Wednesday, February 10, 2016 4:55 PM
To: Soohoon Lee
Cc: Mark Lord; linux-...@vger.kernel.org; Tejun Heo;
linux-kernel@vger.kernel.org
On Wed, 2016-02-10 at 18:29 +0100, Torsten Duwe wrote:
> Changes since V7:
> * drop "notrace" attribute for MMU-aiding functions
> and their callees.
> * merge "-mprofile-kernel"-stripping patches into one.
>
> Changes since v6:
> * include Petr's patch, on popular demand ;)
> * move
On 02/10/2016 03:11 PM, Doug Smythies wrote:
On 2016.02.10 07:17 Rafael J. Wysocki wrote:
On Friday, January 29, 2016 11:52:15 PM Rafael J. Wysocki wrote:
The following patch series introduces a mechanism allowing the cpufreq core
and "setpolicy" drivers to provide utilization update
> > Subject: [PATCH v3 2/6] PCI: xilinx: Unify INTx & MSI interrupt FIFO
> > decode
> >
> > When decoding either an INTx or MSI interrupt, the driver has no way
> > to know which it will pull out of the interrupt FIFO. If both were
> > pending then this would lead to either the interrupt being
Hi Linus,
Just two small fixes for the 4.5-rc cycle.
Thanks,
Darren Hart
Intel Open Source Technology Center
The following changes since commit 92e963f50fc74041b5e9e744c330dca48e04f08d:
Linux 4.5-rc1 (2016-01-24 13:06:47 -0800)
are available in the git repository at:
Hi all,
Changes since 20160210:
The net-next tree gained a conflict against the net tree.
The drm-misc tree lost its build failure.
The trivial tree gained a build fix from the akpm tree.
The aio tree still had a build failure so I used the version from
next-20160111.
The akpm tree lost
> Subject: [PATCH v3 2/6] PCI: xilinx: Unify INTx & MSI interrupt FIFO decode
>
> When decoding either an INTx or MSI interrupt, the driver has no way to
> know which it will pull out of the interrupt FIFO. If both were pending then
> this would lead to either the interrupt being handled
> Subject: Re: [PATCH V3 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver
> to work on both Zynq and Microblaze
>
> On Wednesday 10 February 2016 09:27:07 Paul Burton wrote:
> > On Wed, Feb 10, 2016 at 05:55:51AM +, Bharat Kumar Gogada wrote:
> > > > On Tue, Feb 09, 2016 at 04:11:56PM
On 02/10/2016 01:06 AM, Mark Brown wrote:
> On Fri, Dec 11, 2015 at 09:39:58AM +0530, Vignesh R wrote:
>
>> +if (spi_flash_read_supported(spi)) {
>> +struct spi_flash_read_message msg;
>> +int ret;
>> +
>> +msg.buf = buf;
>> +msg.from = from;
Modify ppa driver to use the new parallel port device model.
Signed-off-by: Sudip Mukherjee
---
Resending as there was no review or ACK for this change.
This has exactly same changes as done in scsi/imm.c which has already
been accepted.
drivers/scsi/ppa.c | 46
Hi Jassi,
On 02/10/2016 10:23 PM, Jassi Brar wrote:
[...]
Thanks for taking the time and checking the TRM, I apologize that the
actual details of the hardware block which was supposed to be in
sections 8.1.3 and 8.1.4 has unfortunately been dropped since the last
time I reviewed in the spec Vs
We are getting build warning about:
"Section mismatch in reference from the variable sim710_eisa_driver to
the function .init.text:sim710_eisa_probe()
The variable sim710_eisa_driver references the function __init
sim710_eisa_probe()"
sim710_eisa_probe() was having __init but that was being
Fix below build warning:
CC [M] drivers/regulator/qcom_saw-regulator.o
drivers/regulator/qcom_saw-regulator.c: In function 'qcom_saw_regulator_probe':
drivers/regulator/qcom_saw-regulator.c:154:5: warning: 'found' is used
uninitialized in this function [-Wuninitialized]
Signed-off-by: Axel Lin
---
drivers/regulator/qcom_saw-regulator.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/regulator/qcom_saw-regulator.c
b/drivers/regulator/qcom_saw-regulator.c
index c800f16..c00f0df 100644
--- a/drivers/regulator/qcom_saw-regulator.c
Hi Ricky,
On 02/01/2016 09:10 AM, Ricky Liang wrote:
>> +static int cpufreq_sched_policy_init(struct cpufreq_policy *policy)
>> > +{
>> > + struct gov_data *gd;
>> > + int cpu;
>> > +
>> > + for_each_cpu(cpu, policy->cpus)
>> > +
On Tue, Feb 9, 2016 at 11:40 PM, Nishanth Menon wrote:
> On 09:43-20160209, Nishanth Menon wrote:
>> On Tue, Feb 9, 2016 at 8:54 AM, Jassi Brar wrote:
> [..]
>> Let me prototype this as part of of_xlate and see if I can pull the
>> qinst data back out.. obviously one negative will be that I will
From: Joonsoo Kim
We can disable debug_pagealloc processing even if the code is compiled
with CONFIG_DEBUG_PAGEALLOC. This patch changes the code to query
whether it is enabled or not in runtime.
Acked-by: Chris Metcalf
Signed-off-by: Joonsoo Kim
---
arch/tile/mm/init.c | 11 +++
1
From: Joonsoo Kim
We can disable debug_pagealloc processing even if the code is compiled
with CONFIG_DEBUG_PAGEALLOC. This patch changes the code to query
whether it is enabled or not in runtime.
v2: clean up code, per Christian.
Signed-off-by: Joonsoo Kim
---
mm/slub.c | 7 +++
1 file
From: Joonsoo Kim
We can disable debug_pagealloc processing even if the code is compiled
with CONFIG_DEBUG_PAGEALLOC. This patch changes the code to query
whether it is enabled or not in runtime.
v2: export _debug_pagealloc_enabled to modules, per Andrew.
Acked-by: David Rientjes
Acked-by:
From: Joonsoo Kim
We can disable debug_pagealloc processing even if the code is compiled
with CONFIG_DEBUG_PAGEALLOC. This patch changes the code to query
whether it is enabled or not in runtime.
v2: fix build failure
Acked-by: David Rientjes
Signed-off-by: Joonsoo Kim
---
From: Joonsoo Kim
We can disable debug_pagealloc processing even if the code is compiled
with CONFIG_DEBUG_PAGEALLOC. This patch changes the code to query
whether it is enabled or not in runtime.
v2: update comment, per David.
adjust comment to use 80 cols, per Andrew.
Reviewed-by: Christian
From: Joonsoo Kim
v2) Changes
o fix powerpc build failure (basic build test done)
o export symbol for module build
o change comment and clean up code
As CONFIG_DEBUG_PAGEALLOC can be enabled/disabled via kernel
parameters we can optimize some cases by checking the enablement
state.
This is
From: Suravee Suthikulpanit
Add new i2c1 device node, and fix the incorrect clock frequency.
Signed-off-by: Tom Lendacky
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git
From: Brijesh Singh
Add KCS device node to support IPMI solution on Overdrive
system.
Signed-off-by: Brijesh Singh
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git
From: Suravee Suthikulpanit
Add new GPIO device nodes and fix clock on gpio0.
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 49 +---
1 file changed, 45 insertions(+), 4 deletions(-)
diff --git
From: Suravee Suthikulpanit
This patch series contains several updates for the AMD Seattle SOC DTS files.
It also adds new board files for newer Overdrive and Linaro 96boards (Husky)
platforms.
Olof,
You mentioned that you have already applied the V2 of the series
to next/dt64. Do you think we
From: Suravee Suthikulpanit
Add device tree files for AMD Overdrive boards which comes with
AMD Seattle Revision B0 and B1 SOCs.
Signed-off-by: Tom Lendacky
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/Makefile | 3 +-
From: Brijesh Singh
This patch fixes incorrect sizes of the GICv2 device tree node.
This has triggered error message when booting Xen hypervisor.
Signed-off-by: Brijesh Singh
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 4 ++--
1 file changed, 2
From: Suravee Suthikulpanit
Remove invalid entry in the SPI device nodes.
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
From: Suravee Suthikulpanit
Adding maintainers for AMD Seattle device tree.
Signed-off-by: Brijesh Singh
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Tom Lendacky
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
From: Suravee Suthikulpanit
Add new SATA1 device node, and fix the register range size of SATA0.
Signed-off-by: Tom Lendacky
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git
From: Suravee Suthikulpanit
Add PERF CCN-504 device tree node.
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
From: Suravee Suthikulpanit
Add device tree file for AMD/Linaro 96Boards Enterprise Edition Server
(Husky) Board. This is based on the AMD Seattle Rev.B0 system
Signed-off-by: Leo Duran
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/Makefile | 3 +-
From: Tom Lendacky
Add AMD XGBE device tree file, which is available in AMD Seattle RevB.
Signed-off-by: Tom Lendacky
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi | 117
2 files changed, 118 insertions(+)
From: Suravee Suthikulpanit
Since GICv2m MSI frame is also considered DMA-able, we should also
include this range in the dma-range DT property as well. Therefore,
this patch fixes the smb0 and pcie0 dma-range properties.
Signed-off-by: Suravee Suthikulpanit
---
Good day,
I need a foreign partner for a proposed mutual business, which refers to the
transfer of a large sum of money to an account abroad, as the beneficiary of
the funds. Everything about this operation, will be legally done without any
bridge financial authority, both in my country and
Trying to cc the GNU parted and linux-block mailing lists.
On 9 February 2016 at 13:02, Jens Rosenboom wrote:
> While trying to reproduce some performance issues I have been seeing
> with Ceph, I have come across a strange behaviour which is seemingly
> affected only by the end point (and
On 02/10/2016 08:19 PM, Ken Moffat wrote:
> On Wed, Feb 10, 2016 at 05:56:16PM -0800, Randy Dunlap wrote:
>> [add Jan Kara]
>>
>> On 02/10/16 13:29, Steve Kenton wrote:
>>> Is anyone maintaining these or am I about to volunteer for another job?
I guess I should have said "developing" rather than
On 02/10/2016 07:21 AM, Arnd Bergmann wrote:
On Tuesday 09 February 2016 18:37:46 Guenter Roeck wrote:
On 02/09/2016 07:26 AM, Arnd Bergmann wrote:
On Tuesday 09 February 2016 07:08:59 Guenter Roeck wrote:
IS_ERR_VALUE() assumes that its parameter is an unsigned long.
It can not be used to
On Wed, 2016-02-10 at 10:22 +0100, Alessio Igor Bogani wrote:
> Signed-off-by: Alessio Igor Bogani
> ---
> arch/powerpc/Makefile| 10 +
> arch/powerpc/configs/86xx-32bit.config | 4 +
> arch/powerpc/configs/86xx-hw.config | 106 +
>
On 2/10/2016 1:03 PM, Will Deacon wrote:
> On Fri, Feb 05, 2016 at 12:13:28PM -0700, Tyler Baicar wrote:
>> +#else /* CONFIG_HAVE_ACPI_APEI_SEA */
>> +static inline int ghes_sea_add(struct ghes *ghes)
>> +{
>> +pr_err(GHES_PFX "ID: %d, trying to add SEA notification which is not
>>
Hi,
I noticed that the use of the function -- unreachable() -- inside of
the BUG() macro in arch/x86/include/asm/bug.h causes compiler output
to be suspect based on review of assembly output for quite a few
areas.
if as a test, you remove the call to unreachable() in the BUG() macro,
it seems to
From: Noam Camus
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by:
From: Noam Camus
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Rob Herring
Cc: Thomas Gleixner
Cc:
From: Noam Camus
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus
---
include/soc/nps/common.h | 150 ++
1
From: Noam Camus
Change Log--
v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using
clocksoure mmio driver
v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to
On 2/10/2016 1:02 PM, Will Deacon wrote:
> On Fri, Feb 05, 2016 at 12:13:27PM -0700, Tyler Baicar wrote:
>> Add a handler for instruction aborts at the current EL
>> (ESR_ELx_EC_IABT_CUR) so they are no longer handled in el1_inv.
>> This allows firmware first handling for possible SEA
>>
Is there any reason keeping this statement on the code?
-8<-
>From d8a387efb8199b69b6464970d6f9fc57cbcf0ab0 Mon Sep 17 00:00:00 2001
From: Byungchul Park
Date: Thu, 11 Feb 2016 11:50:53 +0900
Subject: [PATCH] sched: remove an unnecessary memory access, rq->cpu in
__schedule()
Remove an
Ok I think this about covers it. The line length issues remain, but the script
repors them as warnings so I'm not to worried about it. Patch follows:
---
Input: BYD: Added proper touch support
Implemented absolute position and touch reporting. Now BYD touchpads will use
the synaptics/libinput
Le 10/02/2016 16:32, David Daney a écrit :
> On 02/10/2016 03:49 PM, Aaro Koskinen wrote:
>> Hi,
>>
>> On Wed, Feb 10, 2016 at 10:02:23AM -0800, David Daney wrote:
>>> On 02/10/2016 09:36 AM, Matt Redfearn wrote:
+pr_warn(FW_WARN "%s: Legacy property '%s'. Please remove\n",
+
On 2/10/2016 10:18 PM, Dan Williams wrote:
The pfn_t type uses an unsigned long to store a pfn + flags value. On a
64-bit platform the upper 12 bits of an unsigned long are never used for
storing the value of a pfn. However, this is not true on highmem
platforms, all 32-bits of a pfn value are
> On Feb 11, 2016, at 01:38, Anton Protopopov wrote:
>
> A negative value rc compared to the positive value ENOENT in the
> finish_read() function.
>
> Signed-off-by: Anton Protopopov
> ---
> fs/ceph/addr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On Wed, Feb 10, 2016 at 6:51 AM, Borislav Petkov wrote:
> On Wed, Feb 10, 2016 at 02:48:02PM +0100, Michael Matz wrote:
>> Hi,
>>
>> On Wed, 10 Feb 2016, Borislav Petkov wrote:
>>
>> > --- a/arch/x86/include/asm/tlbflush.h
>> > +++ b/arch/x86/include/asm/tlbflush.h
>> > @@ -23,7 +23,7 @@ static
DAX doesn't deposit pgtables when it maps huge pages: nothing to
withdraw. It can lead to crash.
Signed-off-by: Kirill A. Shutemov
---
mm/huge_memory.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/mm/huge_memory.c b/mm/huge_memory.c
index 5404f7534366..ca7f21516c3a
On 2/10/2016 1:03 PM, Will Deacon wrote:
> On Fri, Feb 05, 2016 at 12:13:26PM -0700, Tyler Baicar wrote:
>> +static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs
>> *regs)
>> +{
>> +struct siginfo info;
>> +
>> +atomic_notifier_call_chain(_handler_chain, 0, NULL);
>>
Hello,
I am Mr. LAURENT EYADEMA from Republic of Togo.please read the attached
proposal.
Thanks in anticipation of your urgent response,
LAURENT EYADEMA
proposal.docx
Description: Binary data
Enable configuration options useful for Vybrid:
- NFC NAND driver
- USB dual-role controller (and Chipidea Gadget support)
- Built-in EDMA DMA driver (to be available at LPUART probe)
- Vybrid ADC driver
- IIO hwmon support (used in i.MX 23/28, patch pending for Vybrid)
Signed-off-by: Stefan
The pfn_t type uses an unsigned long to store a pfn + flags value. On a
64-bit platform the upper 12 bits of an unsigned long are never used for
storing the value of a pfn. However, this is not true on highmem
platforms, all 32-bits of a pfn value are used to address a 44-bit
physical address
On Wed, Feb 10, 2016 at 05:56:16PM -0800, Randy Dunlap wrote:
> [add Jan Kara]
>
> On 02/10/16 13:29, Steve Kenton wrote:
> > Is anyone maintaining these or am I about to volunteer for another job?
>
> CUrrent MAINTAINERS file says:
>
> UDF FILESYSTEM
> M:Jan Kara
> S:Maintained
> F:
Enable configuration options useful for Vybrid:
- NFC NAND driver
- USB dual-role controller support
- FTM PWM driver
- DSPI SPI driver
- Colibri VF50 Touchscreen support.
Beside that, enable useful configurations such as IIO hwmon support
(used in i.MX 23/28, patch pending for Vybrid), PWM LED
2016-02-11 3:58 GMT+09:00 Andrew Morton :
> On Wed, 10 Feb 2016 14:42:57 +0100 Vlastimil Babka wrote:
>
>> > --- a/mm/memory_hotplug.c
>> > +++ b/mm/memory_hotplug.c
>> > @@ -509,6 +509,8 @@ int __ref __add_pages(int nid, struct zone *zone,
>> > unsigned long phys_start_pfn,
>> > int
[add Jan Kara]
On 02/10/16 13:29, Steve Kenton wrote:
> Is anyone maintaining these or am I about to volunteer for another job?
CUrrent MAINTAINERS file says:
UDF FILESYSTEM
M: Jan Kara
S: Maintained
F: Documentation/filesystems/udf.txt
F: fs/udf/
and that Doc. file says:
> "Yaniv" == Yaniv Gardi writes:
Yaniv> V7: updated patch 0001 according to a comment also, removed patch
Yaniv> 07/15 from V6, so now there are only 14 patches
Applied to 4.6/scsi-queue.
--
Martin K. Petersen Oracle Linux Engineering
Hello,
I am Mr. LAURENT EYADEMA from Republic of Togo.please read the attached
proposal.
Thanks in anticipation of your urgent response,
LAURENT EYADEMA
proposal.docx
Description: Binary data
The enum values for VIOSRP_LINUX_FORMAT and VIOSRP_INLINE_FORMAT are
off by one. They are currently defined as 0x06 and 0x07 respetively.
These values are defined in PAPR correctly as 0x05 and 0x06. This
inconsistency has gone unnoticed as neither enum is currently used.
The possible future
A VIOSRP_HOST_CONFIG_TYPE management datagram (MAD) has existed in
the code for some time. From what information I've gathered from
Brian King this was likely implemented on the host side in a SLES 9
based VIOS, which is no longer supported anywhere. Further, it is
not defined in PAPR or supported
The root node of the OF device tree is exported as of_root. No need
to look up the root by path name. Instead just get a reference
directly via of_root.
Signed-off-by: Tyrel Datwyler
Reviewed-by: Johannes Thumshirn
---
drivers/scsi/ibmvscsi/ibmvscsi.c | 14 ++
1 file changed, 6
Add defines for mad version and mad os_type, and replace the magic
numbers in set_adapter_info() accordingly.
Signed-off-by: Tyrel Datwyler
---
drivers/scsi/ibmvscsi/ibmvscsi.c | 8
drivers/scsi/ibmvscsi/viosrp.h | 3 +++
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git
In a couple places the magic value of 2 is used to check the return
code of hypercalls. This translates to H_CLOSED.
Signed-off-by: Tyrel Datwyler
---
drivers/scsi/ibmvscsi/ibmvscsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ibmvscsi/ibmvscsi.c
The PAPR defines four valid header values for the first byte of a
CRQ message. Namely, an unused/empty message (0x00), a valid
command/response entry (0x80), a valid initialization entry (0xC0),
and a valid transport event (0xFF). Further, initialization responses
have two formats namely
Fixed up a couple spots that were out of line with the PAPR in regards
to its defined VSCSI protocol. Did away with some magic numbers directly
in the code. Fixed a minor endian issue.
--
v2 changes:
-Renamed CRQ header enums and added enums for INIT formats
-Check that crq->valid !=
The values returned by the show functions for the host os_type,
mad_version, and partition_number attributes get their values
directly from the madapter_info struct whose associated fields are
__be32 typed. Added endian conversion to ensure these values are
sane on LE platforms.
Signed-off-by:
> "Charles" == Charles Chiou writes:
Charles,
Charles> Pegasus is a high performace hardware RAID solution designed to
Charles> unleash the raw power of Thunderbolt technology.
Please address Oliver's concerns about power management.
Also, I was going to merge the first two patches in the
On Wed, 10 Feb 2016 19:49:11 -0500
Justin Keller wrote:
> I am new to submitting patches, so sorry if I am doing it wrong. My idea was
> to change line 147 in drivers/isdn/pcbit/callbacks.c from
> if (cbdata->data.setup.CallingPN == NULL) {
>
> to
>
> if (cbdata->data.setup.CallingPN == NULL
From: Rafael J. Wysocki
The show() and store() routines in the cpufreq core don't need to
acquire all of the locks to check if the struct freq_attr they want
to use really provides the callbacks they need as expected, so change
them to avoid doing that.
Signed-off-by: Rafael J. Wysocki
---
On Wed, 2016-02-10 at 20:08 -0500, r...@redhat.com wrote:
> Change the indentation in __acct_update_integrals to make the function
> a little easier to read.
trivia:
> diff --git a/kernel/tsacct.c b/kernel/tsacct.c
[]
> @@ -125,31 +125,32 @@ void xacct_add_tsk(struct taskstats *stats, struct
>
On Thu, Feb 11, 2016 at 1:59 AM, Rafael J. Wysocki wrote:
> On Tue, Feb 9, 2016 at 4:46 AM, Viresh Kumar wrote:
>> The offline routine was separated into two halves earlier by
>> 'commit 1aee40ac9c86 ("cpufreq: Invoke __cpufreq_remove_dev_finish()
>> after releasing cpu_hotplug.lock");.
>>
>>
Currently cqm(cache quality of service monitoring) is grouping all
events belonging to same PID to use one RMID. However its not counting
all of these different events. Hence we end up with a count of zero for
all events other than the group leader. The patch tries to address the
issue by keeping
RMID could be allocated or deallocated as part of RMID recycling.
When an RMID is allocated for mbm event, the mbm counter needs to be
initialized because next time we read the counter we need the previous
value to account for total bytes that went to the memory controller.
Similarly, when RMID is
This patch adds a per package timer which periodically updates the
Memory bandwidth counters for the events that are currently active.
Current patch has a periodic timer every 1s since the SDM guarantees
that the counter will not overflow in 1s but this time can be definitely
improved by
The MBM init patch enumerates the Intel (Memory b/w monitoring)MBM and
initializes the perf events and datastructures for monitoring the memory
b/w. Its based on original patch series by Kanaka Juvva.
Memory bandwidth monitoring(MBM) provides OS/VMM a way to monitor
bandwidth from one level of
From: Rik van Riel
Change the indentation in __acct_update_integrals to make the function
a little easier to read.
Suggested-by: Peter Zijlstra
Signed-off-by: Rik van Riel
Acked-by: Frederic Weisbecker
---
kernel/tsacct.c | 51 ++-
1 file
* Tony Lindgren [160209 09:26]:
> * Pavel Machek [160207 13:24]:
>
> > ffdffebd 48004a20 (fa004a20) cm_idlest1_core blocking bits: 00200042
> > 000d 48004a28 (fa004a28) cm_idlest3_core
>
> Bit 21 in cm_idlest1_core is for MCSPI4 so WLAN. Does that go
> down if do sleep 5; cat
From: Rik van Riel
After removing __acct_update_integrals from the profile,
native_sched_clock remains as the top CPU user. This can be
reduced by moving VIRT_CPU_ACCOUNTING_GEN to jiffy
granularity.
This will reduce timing accuracy on nohz_full CPUs to jiffy
based sampling, just like on normal
From: Rik van Riel
When running a microbenchmark calling an invalid syscall number
in a loop, on a nohz_full CPU, we spend a full 9% of our CPU
time in __acct_update_integrals.
This function converts cputime_t to jiffies, to a timeval, only to
convert the timeval back to microseconds before
The V4 version of MBM is almost a complete rewrite of the prior
versions. It tries to address all of Thomas earlier
comments.
The patch series has one preparatory patch for cqm and then 4 MBM
patches. *Patches apply on 4.5-rc1*.
Memory bandwitdh monitoring(MBM) provides OS/VMM a way to monitor
From: Tony Luck
Includes all the core infrastructure to measure the total_bytes and
bandwidth.
We have per socket counters for both total system wide L3 external bytes
and local socket memory-controller bytes. The current b/w is calculated
for a minimum diff time(time since it was last counted)
(v6: make VIRT_CPU_ACCOUNTING_GEN jiffy granularity)
Running with nohz_full introduces a fair amount of overhead.
Specifically, various things that are usually done from the
timer interrupt are now done at syscall, irq, and guest
entry and exit times.
However, some of the code that is called
From: Rik van Riel
It looks like all the call paths that lead to __acct_update_integrals
already have irqs disabled, and __acct_update_integrals does not need
to disable irqs itself.
This is very convenient since about half the CPU time left in this
function was spent in local_irq_save alone.
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