Re: [PATCH v5 0/6] Introduce ZONE_CMA

Joonsoo Kim writes: > On Tue, Aug 30, 2016 at 04:09:37PM +0530, Aneesh Kumar K.V wrote: >> Joonsoo Kim writes: >> >> > 2016-08-29 18:27 GMT+09:00 Aneesh Kumar K.V >> > : >> >> js1...@gmail.com writes: >> >> >> >>>

Re: [PATCH v5 0/6] Introduce ZONE_CMA

Joonsoo Kim writes: > On Tue, Aug 30, 2016 at 04:09:37PM +0530, Aneesh Kumar K.V wrote: >> Joonsoo Kim writes: >> >> > 2016-08-29 18:27 GMT+09:00 Aneesh Kumar K.V >> > : >> >> js1...@gmail.com writes: >> >> >> >>> From: Joonsoo Kim >> >>> >> >>> Hello, >> >>> >> >>> Changes from v4 >> >>> o

RE: [PATCH v3 kernel 0/7] Extend virtio-balloon for fast (de)inflating & fast live migration

> Subject: Re: [PATCH v3 kernel 0/7] Extend virtio-balloon for fast > (de)inflating > & fast live migration > > 2016-08-08 14:35 GMT+08:00 Liang Li : > > This patch set contains two parts of changes to the virtio-balloon. > > > > One is the change for speeding up the

RE: [PATCH v3 kernel 0/7] Extend virtio-balloon for fast (de)inflating & fast live migration

> Subject: Re: [PATCH v3 kernel 0/7] Extend virtio-balloon for fast > (de)inflating > & fast live migration > > 2016-08-08 14:35 GMT+08:00 Liang Li : > > This patch set contains two parts of changes to the virtio-balloon. > > > > One is the change for speeding up the inflating & deflating

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You are a recipient to Mrs Julie Leach Donation of $3 million USD. Contact (julieleac...@gmail.com) for claims.

Re: [PATCH V4] leds: trigger: Introduce an USB port trigger

On 31 August 2016 at 21:00, Rafał Miłecki wrote: > On 31 August 2016 at 20:23, Alan Stern wrote: >> On Tue, 30 Aug 2016, Rafał Miłecki wrote: >>> Not really as it won't cover some pretty common use cases. Many home >>> routers have few USB ports (2-5)

Re: [PATCH V4] leds: trigger: Introduce an USB port trigger

On 31 August 2016 at 21:00, Rafał Miłecki wrote: > On 31 August 2016 at 20:23, Alan Stern wrote: >> On Tue, 30 Aug 2016, Rafał Miłecki wrote: >>> Not really as it won't cover some pretty common use cases. Many home >>> routers have few USB ports (2-5) and only 1 USB LED. It has to be >>>

RE: [PATCH 3/3] PCI: Xilinx NWL PCIe: Fix Error for multi function device for legacy interrupts.

> Hi Bharat, > > @@ -561,7 +561,7 @@ static int nwl_pcie_init_irq_domain(struct > > nwl_pcie > *pcie) > > } > > > > pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, > > - INTX_NUM, > >

RE: [PATCH 3/3] PCI: Xilinx NWL PCIe: Fix Error for multi function device for legacy interrupts.

> Hi Bharat, > > @@ -561,7 +561,7 @@ static int nwl_pcie_init_irq_domain(struct > > nwl_pcie > *pcie) > > } > > > > pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, > > - INTX_NUM, > >

Re: [PATCH 1/4] kernel: add a helper to get an owning user namespace for a namespace

On Wed, Aug 31, 2016 at 01:38:35PM -0700, Andrey Vagin wrote: > On Tue, Aug 30, 2016 at 7:56 PM, Serge E. Hallyn wrote: > > On Fri, Aug 26, 2016 at 04:08:08PM -0700, Andrei Vagin wrote: > >> +struct ns_common *ns_get_owner(struct ns_common *ns) > >> +{ > >> + struct

Re: [PATCH 1/4] kernel: add a helper to get an owning user namespace for a namespace

On Wed, Aug 31, 2016 at 01:38:35PM -0700, Andrey Vagin wrote: > On Tue, Aug 30, 2016 at 7:56 PM, Serge E. Hallyn wrote: > > On Fri, Aug 26, 2016 at 04:08:08PM -0700, Andrei Vagin wrote: > >> +struct ns_common *ns_get_owner(struct ns_common *ns) > >> +{ > >> + struct user_namespace *my_user_ns

Re: [PATCH v5 2/2] phy: add a driver for the Rockchip SoC internal PCIe PHY

On Wednesday 31 August 2016 07:38 PM, Heiko Stübner wrote: > Hi, > > Am Samstag, 20. August 2016, 10:53:37 schrieb Shawn Lin: >> This patch to add a generic PHY driver for rockchip PCIe PHY. >> Access the PHY via registers provided by GRF (general register >> files) module. >> >> Signed-off-by:

Re: [PATCH v5 2/2] phy: add a driver for the Rockchip SoC internal PCIe PHY

On Wednesday 31 August 2016 07:38 PM, Heiko Stübner wrote: > Hi, > > Am Samstag, 20. August 2016, 10:53:37 schrieb Shawn Lin: >> This patch to add a generic PHY driver for rockchip PCIe PHY. >> Access the PHY via registers provided by GRF (general register >> files) module. >> >> Signed-off-by:

Re: [PATCH v2] arm64: defconfig: enable common modules for power management

Hi Catalin, Will, On Thu, Sep 01, 2016 at 12:51:09PM +0800, Leo Yan wrote: > Enable common modules for power management; one is to enable > CPUFREQ_DT driver; the driver is used by many platforms by passing OPP > table from device tree. > > Also enables thermal related drivers. Firstly we need

Re: [PATCH v2] arm64: defconfig: enable common modules for power management

Hi Catalin, Will, On Thu, Sep 01, 2016 at 12:51:09PM +0800, Leo Yan wrote: > Enable common modules for power management; one is to enable > CPUFREQ_DT driver; the driver is used by many platforms by passing OPP > table from device tree. > > Also enables thermal related drivers. Firstly we need

[PATCH v2] arm64: defconfig: enable common modules for power management

Enable common modules for power management; one is to enable CPUFREQ_DT driver; the driver is used by many platforms by passing OPP table from device tree. Also enables thermal related drivers. Firstly we need enable configuration CPU_THERMAL for CPU cooling device driver, this will bind thermal

[PATCH v2] arm64: defconfig: enable common modules for power management

Enable common modules for power management; one is to enable CPUFREQ_DT driver; the driver is used by many platforms by passing OPP table from device tree. Also enables thermal related drivers. Firstly we need enable configuration CPU_THERMAL for CPU cooling device driver, this will bind thermal

Re: [PATCH v3 kernel 0/7] Extend virtio-balloon for fast (de)inflating & fast live migration

2016-08-08 14:35 GMT+08:00 Liang Li : > This patch set contains two parts of changes to the virtio-balloon. > > One is the change for speeding up the inflating & deflating process, > the main idea of this optimization is to use bitmap to send the page > information to host

Re: [PATCH v3 kernel 0/7] Extend virtio-balloon for fast (de)inflating & fast live migration

2016-08-08 14:35 GMT+08:00 Liang Li : > This patch set contains two parts of changes to the virtio-balloon. > > One is the change for speeding up the inflating & deflating process, > the main idea of this optimization is to use bitmap to send the page > information to host instead of the PFNs, to

Re: [PATCH 2/2] arm64: dts: rockchip: add eMMC's power domain support for rk3399

Hi, On Wed, Aug 31, 2016 at 7:29 PM, Ziyuan Xu wrote: >> This is fine to pick up _only_ if you don't care about suspend/resume. >> If you care about suspend/resume then someone needs to first write a >> patch that will re-init all "corecfg" values after power is turned on.

Re: [PATCH 2/2] arm64: dts: rockchip: add eMMC's power domain support for rk3399

Hi, On Wed, Aug 31, 2016 at 7:29 PM, Ziyuan Xu wrote: >> This is fine to pick up _only_ if you don't care about suspend/resume. >> If you care about suspend/resume then someone needs to first write a >> patch that will re-init all "corecfg" values after power is turned on. > > > Do you mean

Re: [v10,2/2] PCI: Rockchip: Add Rockchip PCIe controller support

On 08/31/2016 08:39 PM, Shawn Lin wrote: Hi Guenter, Thanks for your review, and I think it still not too late for nitpicking as it isn't merged to next branch. :) We have amend the code a bit, so probably we fixed some of the minor issues against V10. But some of them are really personal

Re: [v10,2/2] PCI: Rockchip: Add Rockchip PCIe controller support

On 08/31/2016 08:39 PM, Shawn Lin wrote: Hi Guenter, Thanks for your review, and I think it still not too late for nitpicking as it isn't merged to next branch. :) We have amend the code a bit, so probably we fixed some of the minor issues against V10. But some of them are really personal

Re: [patch v3.18+ regression fix] sched: Further improve spurious CPU_IDLE active migrations

On Wed, 2016-08-31 at 17:52 +0200, Vincent Guittot wrote: > On 31 August 2016 at 12:36, Mike Galbraith wrote: > > On Wed, 2016-08-31 at 12:18 +0200, Mike Galbraith wrote: > > > On Wed, 2016-08-31 at 12:01 +0200, Peter Zijlstra wrote: > > > > > > So 43f4d66637bc ("sched:

Re: [patch v3.18+ regression fix] sched: Further improve spurious CPU_IDLE active migrations

On Wed, 2016-08-31 at 17:52 +0200, Vincent Guittot wrote: > On 31 August 2016 at 12:36, Mike Galbraith wrote: > > On Wed, 2016-08-31 at 12:18 +0200, Mike Galbraith wrote: > > > On Wed, 2016-08-31 at 12:01 +0200, Peter Zijlstra wrote: > > > > > > So 43f4d66637bc ("sched: Improve sysbench

Re: [PATCH v3 0/5] net/usb: asix driver improvements

From: robert.f...@collabora.com Date: Mon, 29 Aug 2016 09:32:14 -0400 > This is a resubmission of v3, since the netdev > mailinlist was not sent the previous submission. > > This series improves power management of the asix driver. ... Series applied, thanks.

Re: [PATCH v3 0/5] net/usb: asix driver improvements

From: robert.f...@collabora.com Date: Mon, 29 Aug 2016 09:32:14 -0400 > This is a resubmission of v3, since the netdev > mailinlist was not sent the previous submission. > > This series improves power management of the asix driver. ... Series applied, thanks.

Re: [PATCH] mISDN: mark symbols static where possible

Three different patches all with the same Subject line, so I can't apply this stuff. You must make the subject lines unique so that someone reading the "git shortlog" can tell what is different in each change.

Re: [PATCH] mISDN: mark symbols static where possible

Three different patches all with the same Subject line, so I can't apply this stuff. You must make the subject lines unique so that someone reading the "git shortlog" can tell what is different in each change.

[PATCH 1/1] ARM: dts: sun8i: Add dts file for the NanoPi NEO SBC

From: James Pettigrew The NanoPi NEO is a minimal H3 based SBC. It comes with 256/512M RAM, a micro SD slot, 10/100Mbit ethernet and a single USB-A port. Signed-off-by: James Pettigrew --- arch/arm/boot/dts/Makefile| 1 +

[PATCH 1/1] ARM: dts: sun8i: Add dts file for the NanoPi NEO SBC

From: James Pettigrew The NanoPi NEO is a minimal H3 based SBC. It comes with 256/512M RAM, a micro SD slot, 10/100Mbit ethernet and a single USB-A port. Signed-off-by: James Pettigrew --- arch/arm/boot/dts/Makefile| 1 + arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 126

Re: [PATCH 2/8] writeback: add wbc_to_write_flags()

On 08/31/2016 05:32 PM, Omar Sandoval wrote: On Wed, Aug 31, 2016 at 11:05:45AM -0600, Jens Axboe wrote: Add wbc_to_write_flags(), which returns the write modifier flags to use, based on a struct writeback_control. No functional changes in this patch, but it prepares us for factoring other wbc

Re: [PATCH 2/8] writeback: add wbc_to_write_flags()

On 08/31/2016 05:32 PM, Omar Sandoval wrote: On Wed, Aug 31, 2016 at 11:05:45AM -0600, Jens Axboe wrote: Add wbc_to_write_flags(), which returns the write modifier flags to use, based on a struct writeback_control. No functional changes in this patch, but it prepares us for factoring other wbc

Re: [PATCH 2/4] cpu: expose pm_qos_resume_latency for each cpu

Few commits and patch changed according to Greg's comments. Regards Alex >From 186c534b0b8b9649fbfce05b0b4f90f764c571a4 Mon Sep 17 00:00:00 2001 From: Alex Shi Date: Tue, 16 Aug 2016 15:29:01 +0800 Subject: [PATCH 2/4] cpu: expose pm_qos_resume_latency for each cpu

Re: [PATCH 2/4] cpu: expose pm_qos_resume_latency for each cpu

Few commits and patch changed according to Greg's comments. Regards Alex >From 186c534b0b8b9649fbfce05b0b4f90f764c571a4 Mon Sep 17 00:00:00 2001 From: Alex Shi Date: Tue, 16 Aug 2016 15:29:01 +0800 Subject: [PATCH 2/4] cpu: expose pm_qos_resume_latency for each cpu Adding

Re: [PATCH 5/5] net: axienet: constify ethtool_ops structures

From: Julia Lawall Date: Thu, 1 Sep 2016 00:21:23 +0200 > Check for ethtool_ops structures that are only stored in the ethtool_ops > field of a net_device structure or passed as the second argument to > netdev_set_default_ethtool_ops. These contexts are declared const, so

Re: [PATCH 5/5] net: axienet: constify ethtool_ops structures

From: Julia Lawall Date: Thu, 1 Sep 2016 00:21:23 +0200 > Check for ethtool_ops structures that are only stored in the ethtool_ops > field of a net_device structure or passed as the second argument to > netdev_set_default_ethtool_ops. These contexts are declared const, so > ethtool_ops

Re: [PATCH 1/5] net: mediatek: constify ethtool_ops structures

From: Julia Lawall Date: Thu, 1 Sep 2016 00:21:19 +0200 > Check for ethtool_ops structures that are only stored in the ethtool_ops > field of a net_device structure or passed as the second argument to > netdev_set_default_ethtool_ops. These contexts are declared const, so

Re: [PATCH 1/5] net: mediatek: constify ethtool_ops structures

From: Julia Lawall Date: Thu, 1 Sep 2016 00:21:19 +0200 > Check for ethtool_ops structures that are only stored in the ethtool_ops > field of a net_device structure or passed as the second argument to > netdev_set_default_ethtool_ops. These contexts are declared const, so > ethtool_ops

Re: [PATCH 4/5] r8152: constify ethtool_ops structures

From: Julia Lawall Date: Thu, 1 Sep 2016 00:21:22 +0200 > Check for ethtool_ops structures that are only stored in the ethtool_ops > field of a net_device structure or passed as the second argument to > netdev_set_default_ethtool_ops. These contexts are declared const, so

Re: [PATCH 4/5] r8152: constify ethtool_ops structures

From: Julia Lawall Date: Thu, 1 Sep 2016 00:21:22 +0200 > Check for ethtool_ops structures that are only stored in the ethtool_ops > field of a net_device structure or passed as the second argument to > netdev_set_default_ethtool_ops. These contexts are declared const, so > ethtool_ops

Re: [PATCH 2/4] cpu: expose pm_qos_resume_latency for each cpu

On 09/01/2016 11:39 AM, Alex Shi wrote: > User can set values on each of cpu, like limit 100ms on cpu0, that means > the cpu0 response time should be in 100ms in possible idle. It similar > with DMA_LATENCY, but that request is for all cpu. This is just for > particular cpu, like a interrupt

Re: [PATCH 2/4] cpu: expose pm_qos_resume_latency for each cpu

On 09/01/2016 11:39 AM, Alex Shi wrote: > User can set values on each of cpu, like limit 100ms on cpu0, that means > the cpu0 response time should be in 100ms in possible idle. It similar > with DMA_LATENCY, but that request is for all cpu. This is just for > particular cpu, like a interrupt

Re: [PATCH 04/13] perf/core: Extend perf_output_sample_regs() to include perf_arch_regs

On Tuesday 30 August 2016 09:41 PM, Nilay Vaish wrote: On 28 August 2016 at 16:00, Madhavan Srinivasan wrote: diff --git a/kernel/events/core.c b/kernel/events/core.c index 274288819829..e16bf4d057d1 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@

Re: [PATCH 04/13] perf/core: Extend perf_output_sample_regs() to include perf_arch_regs

On Tuesday 30 August 2016 09:41 PM, Nilay Vaish wrote: On 28 August 2016 at 16:00, Madhavan Srinivasan wrote: diff --git a/kernel/events/core.c b/kernel/events/core.c index 274288819829..e16bf4d057d1 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -5371,16 +5371,24 @@ u64

[PATCH 6/7] serial: 8250_fintek: Add F81866 Support

Fintek F81866 is a LPC to 6 UARTs SuperIO. It has fully functional UARTs likes F81216H. It's also need check the IRQ mode with system assigned, but the configuration is not the same with F81216 series. F81866 IRQ Mode setting: 0xf0 Bit1: IRQ_MODE0 Bit0:

[PATCH 6/7] serial: 8250_fintek: Add F81866 Support

Fintek F81866 is a LPC to 6 UARTs SuperIO. It has fully functional UARTs likes F81216H. It's also need check the IRQ mode with system assigned, but the configuration is not the same with F81216 series. F81866 IRQ Mode setting: 0xf0 Bit1: IRQ_MODE0 Bit0:

[PATCH 7/7] serial: 8250_fintek: Add F81865 Support

Fintek F81865 is a LPC to 6 UARTs SuperIO. It has less functional UARTs likes F81866. It's also need check the IRQ mode with system assigned, but the configuration is not the same with F81216 series. F81865 IRQ Mode setting: 0xf0 Bit1: IRQ_MODE0 Bit0: Share mode

[PATCH 1/7] serial: 8250_fintek: Refactoring read/write method

If we need to access SuperIO registers, It should write register offset to base_addr and read/write value to base_addr + 1 to perform read/write. We can make it more simply with write/read functions. This patch add sio_read_reg()/sio_write_reg()/sio_write_mask_reg() to reduce SuperIO register

[PATCH 2/7] serial: 8250_fintek: Set IRQ Mode when port probed

Set IRQ Mode when port probed in find_base_port() It should hold the IO port premission via fintek_8250_enter_key() and release via fintek_8250_exit_key() when we configure the SuperIO. This patch will move all SuperIO configure operations to find_base_port() to reduce

[PATCH 4/7] serial: 8250_fintek: Rearrange function

We change the position of fintek_8250_set_irq_mode() above the find_base_port() to eliminate the prototype define. Signed-off-by: Ji-Ze Hong (Peter Hong) --- drivers/tty/serial/8250/8250_fintek.c | 19 --- 1 file changed, 8 insertions(+), 11

[PATCH 5/7] serial: 8250_fintek: Add F81216 Support

Fintek F81216 is a LPC to 4 UARTs device. It's the F81216 series but support less functional than F81216AD/F81216H The following list is brief descriptions of F81216 series: F81216H (0105) 9Bit/High baud rate(not implements with mainline) RS485, 128Bytes FIFO (implemented)

[PATCH 7/7] serial: 8250_fintek: Add F81865 Support

Fintek F81865 is a LPC to 6 UARTs SuperIO. It has less functional UARTs likes F81866. It's also need check the IRQ mode with system assigned, but the configuration is not the same with F81216 series. F81865 IRQ Mode setting: 0xf0 Bit1: IRQ_MODE0 Bit0: Share mode

[PATCH 1/7] serial: 8250_fintek: Refactoring read/write method

If we need to access SuperIO registers, It should write register offset to base_addr and read/write value to base_addr + 1 to perform read/write. We can make it more simply with write/read functions. This patch add sio_read_reg()/sio_write_reg()/sio_write_mask_reg() to reduce SuperIO register

[PATCH 2/7] serial: 8250_fintek: Set IRQ Mode when port probed

Set IRQ Mode when port probed in find_base_port() It should hold the IO port premission via fintek_8250_enter_key() and release via fintek_8250_exit_key() when we configure the SuperIO. This patch will move all SuperIO configure operations to find_base_port() to reduce

[PATCH 4/7] serial: 8250_fintek: Rearrange function

We change the position of fintek_8250_set_irq_mode() above the find_base_port() to eliminate the prototype define. Signed-off-by: Ji-Ze Hong (Peter Hong) --- drivers/tty/serial/8250/8250_fintek.c | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git

[PATCH 5/7] serial: 8250_fintek: Add F81216 Support

Fintek F81216 is a LPC to 4 UARTs device. It's the F81216 series but support less functional than F81216AD/F81216H The following list is brief descriptions of F81216 series: F81216H (0105) 9Bit/High baud rate(not implements with mainline) RS485, 128Bytes FIFO (implemented)

Re: [v10,2/2] PCI: Rockchip: Add Rockchip PCIe controller support

Hi Guenter, Thanks for your review, and I think it still not too late for nitpicking as it isn't merged to next branch. :) We have amend the code a bit, so probably we fixed some of the minor issues against V10. But some of them are really personal taste, if you still insist on that, I will be

[PATCH 3/7] serial: 8250_fintek: Set maximum FIFO of F81216H

The Fintek F81216H had maximum 128Bytes FIFO, but some BIOS configurated as normal 16Bytes FIFO. This patch will set 128Bytes FIFO and trigger level multiplier as 4x when F81216H detected. Default 16550A trigger level is 8Bytes. When this patch applied, the trigger level will change to 8Byte x 4

[PATCH 0/7] serial: 8250_fintek: Fix the IRQ mode and code refactoring

The following patches will fix the Fintek LPC to UARTs IRQ mode mismatch issue, code refactoring and this series patches should follow by patch rename IRQ_MODE macro on 'commit 87a713c8ffca ("8250/fintek: rename IRQ_MODE macro")'. with tty-linus branch. Some BIOS only use _OSI("Linux") to

Re: [v10,2/2] PCI: Rockchip: Add Rockchip PCIe controller support

Hi Guenter, Thanks for your review, and I think it still not too late for nitpicking as it isn't merged to next branch. :) We have amend the code a bit, so probably we fixed some of the minor issues against V10. But some of them are really personal taste, if you still insist on that, I will be

[PATCH 3/7] serial: 8250_fintek: Set maximum FIFO of F81216H

The Fintek F81216H had maximum 128Bytes FIFO, but some BIOS configurated as normal 16Bytes FIFO. This patch will set 128Bytes FIFO and trigger level multiplier as 4x when F81216H detected. Default 16550A trigger level is 8Bytes. When this patch applied, the trigger level will change to 8Byte x 4

[PATCH 0/7] serial: 8250_fintek: Fix the IRQ mode and code refactoring

The following patches will fix the Fintek LPC to UARTs IRQ mode mismatch issue, code refactoring and this series patches should follow by patch rename IRQ_MODE macro on 'commit 87a713c8ffca ("8250/fintek: rename IRQ_MODE macro")'. with tty-linus branch. Some BIOS only use _OSI("Linux") to

Re: [PATCH 2/4] cpu: expose pm_qos_resume_latency for each cpu

>> @@ -376,6 +377,8 @@ int register_cpu(struct cpu *cpu, int num) >> >> per_cpu(cpu_sys_devices, num) = >dev; >> register_cpu_under_node(num, cpu_to_node(num)); >> +if (dev_pm_qos_expose_latency_limit(>dev, 0)) >> +pr_debug("CPU%d: add resume latency failed\n", num); >

Re: [PATCH 2/4] cpu: expose pm_qos_resume_latency for each cpu

>> @@ -376,6 +377,8 @@ int register_cpu(struct cpu *cpu, int num) >> >> per_cpu(cpu_sys_devices, num) = >dev; >> register_cpu_under_node(num, cpu_to_node(num)); >> +if (dev_pm_qos_expose_latency_limit(>dev, 0)) >> +pr_debug("CPU%d: add resume latency failed\n", num); >

Re: [RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

在 2016/9/1 6:56, Rafael J. Wysocki 写道: On Wednesday, August 31, 2016 07:48:14 PM Dongdong Liu wrote: Add specific quirks for PCI config space accessors.This involves: 1. New initialization call hisi_pcie_acpi_init() to get RC config resource with hardcoded range address and setup ecam mapping.

Re: [RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

在 2016/9/1 6:56, Rafael J. Wysocki 写道: On Wednesday, August 31, 2016 07:48:14 PM Dongdong Liu wrote: Add specific quirks for PCI config space accessors.This involves: 1. New initialization call hisi_pcie_acpi_init() to get RC config resource with hardcoded range address and setup ecam mapping.

Re: [PATCH 2/2] arm64: dts: rockchip: add eMMC's power domain support for rk3399

在 2016/9/1 10:29, Ziyuan Xu 写道: Hi, On 2016年09月01日 01:42, Doug Anderson wrote: Hi, On Sun, Aug 28, 2016 at 8:25 PM, Shawn Lin wrote: On 2016/8/29 10:50, Elaine Zhang wrote: On 08/27/2016 11:05 PM, Shawn Lin wrote: On 2016/8/27 21:41, Ziyuan Xu wrote: Control

Re: [PATCH 2/2] arm64: dts: rockchip: add eMMC's power domain support for rk3399

在 2016/9/1 10:29, Ziyuan Xu 写道: Hi, On 2016年09月01日 01:42, Doug Anderson wrote: Hi, On Sun, Aug 28, 2016 at 8:25 PM, Shawn Lin wrote: On 2016/8/29 10:50, Elaine Zhang wrote: On 08/27/2016 11:05 PM, Shawn Lin wrote: On 2016/8/27 21:41, Ziyuan Xu wrote: Control power domain for eMMC via

Re: [PATCH 00/13] Add support for perf_arch_regs

On Tuesday 30 August 2016 09:31 PM, Nilay Vaish wrote: On 28 August 2016 at 16:00, Madhavan Srinivasan wrote: Patchset to extend PERF_SAMPLE_REGS_INTR to include platform specific PMU registers. Patchset applies cleanly on tip:perf/core branch It's a perennial

Re: [PATCH 00/13] Add support for perf_arch_regs

On Tuesday 30 August 2016 09:31 PM, Nilay Vaish wrote: On 28 August 2016 at 16:00, Madhavan Srinivasan wrote: Patchset to extend PERF_SAMPLE_REGS_INTR to include platform specific PMU registers. Patchset applies cleanly on tip:perf/core branch It's a perennial request from hardware folks

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Re: [PATCH v2 2/7] dts: sun8i-h3: add pinmux definitions for i2c0/i2c1

On Thu, Sep 1, 2016 at 3:30 AM, wrote: > From: Jorik Jonker > > This adds proper pinmux definitions for i2c0 and i2c1. Although H3 has a third > i2c controller, these are not exposed on my boards. If someone actually has a > H3 board with an exposed

Re: [PATCH v2 2/7] dts: sun8i-h3: add pinmux definitions for i2c0/i2c1

On Thu, Sep 1, 2016 at 3:30 AM, wrote: > From: Jorik Jonker > > This adds proper pinmux definitions for i2c0 and i2c1. Although H3 has a third > i2c controller, these are not exposed on my boards. If someone actually has a > H3 board with an exposed i2c2, they could add the third. > >

[PATCH] ftrace: Handle TRACE_BPUTS in print_graph_comment

It missed to handle TRACE_BPUTS so messages recorded by trace_bputs() will be shown with symbol info unnecessarily. You can see it with the trace_printk sample code: # cd /sys/kernel/tracing/ # echo sys_sync > set_graph_function # echo 1 > options/sym-offset # echo function_graph >

[PATCH] ftrace: Handle TRACE_BPUTS in print_graph_comment

It missed to handle TRACE_BPUTS so messages recorded by trace_bputs() will be shown with symbol info unnecessarily. You can see it with the trace_printk sample code: # cd /sys/kernel/tracing/ # echo sys_sync > set_graph_function # echo 1 > options/sym-offset # echo function_graph >

Re: [PATCH v2 3/7] dts: sun8i-h3: add i2c0/i2c1 SoC peripherals

On Thu, Sep 1, 2016 at 3:30 AM, wrote: > From: Jorik Jonker > > This enables the i2c0/i2c1 peripherals of the SoC. There is actually a third > controller, but I do not have a board on hands on which i2c2 is exposed in > such > a way that I can verify

Re: [PATCH v2 3/7] dts: sun8i-h3: add i2c0/i2c1 SoC peripherals

On Thu, Sep 1, 2016 at 3:30 AM, wrote: > From: Jorik Jonker > > This enables the i2c0/i2c1 peripherals of the SoC. There is actually a third > controller, but I do not have a board on hands on which i2c2 is exposed in > such > a way that I can verify that it works. If they are listed in the

Re: [PATCH] arm64: Improve kprobes test for atomic sequence

Hi Dave, On Wed, 31 Aug 2016 16:52:22 -0400 David Long wrote: > From: "David A. Long" > > Kprobes searches backwards a finite number of instructions to determine if > there is an attempt to probe a load/store exclusive sequence. It stops when > it

Re: [PATCH] arm64: Improve kprobes test for atomic sequence

Hi Dave, On Wed, 31 Aug 2016 16:52:22 -0400 David Long wrote: > From: "David A. Long" > > Kprobes searches backwards a finite number of instructions to determine if > there is an attempt to probe a load/store exclusive sequence. It stops when > it hits the maximum number of instructions or a

Re: [PATCH 2/2] arm64: dts: rockchip: add eMMC's power domain support for rk3399

Hi, On 2016年09月01日 01:42, Doug Anderson wrote: Hi, On Sun, Aug 28, 2016 at 8:25 PM, Shawn Lin wrote: On 2016/8/29 10:50, Elaine Zhang wrote: On 08/27/2016 11:05 PM, Shawn Lin wrote: On 2016/8/27 21:41, Ziyuan Xu wrote: Control power domain for eMMC via genpd

Re: [PATCH 2/2] arm64: dts: rockchip: add eMMC's power domain support for rk3399

Hi, On 2016年09月01日 01:42, Doug Anderson wrote: Hi, On Sun, Aug 28, 2016 at 8:25 PM, Shawn Lin wrote: On 2016/8/29 10:50, Elaine Zhang wrote: On 08/27/2016 11:05 PM, Shawn Lin wrote: On 2016/8/27 21:41, Ziyuan Xu wrote: Control power domain for eMMC via genpd to reduce power

[PATCH v2] serial: 8250_dw: Use an unified new dev variable in probe

Use an unified new dev variable instead of >dev and p->dev in probe function. Reviewed-by: Heikki Krogerus Signed-off-by: Kefeng Wang --- Hi Greg, updated, based on tty-testing branch :) v1->v2: 1) Add Heikki's reviewed-by 2) Rebase

[PATCH v2] serial: 8250_dw: Use an unified new dev variable in probe

Use an unified new dev variable instead of >dev and p->dev in probe function. Reviewed-by: Heikki Krogerus Signed-off-by: Kefeng Wang --- Hi Greg, updated, based on tty-testing branch :) v1->v2: 1) Add Heikki's reviewed-by 2) Rebase on tty-testing branch of

Re: [PATCH] serial: 8250_dw: Use an unified new dev variable in probe

Sorry, please ignore, send wrong patch. On 2016/9/1 9:34, Kefeng Wang wrote: > Use an unified new dev variable instead of >dev and p->dev > in probe function. > > Signed-off-by: Kefeng Wang > --- > drivers/tty/serial/8250/8250_dw.c | 45 >

Re: [PATCH] serial: 8250_dw: Use an unified new dev variable in probe

Sorry, please ignore, send wrong patch. On 2016/9/1 9:34, Kefeng Wang wrote: > Use an unified new dev variable instead of >dev and p->dev > in probe function. > > Signed-off-by: Kefeng Wang > --- > drivers/tty/serial/8250/8250_dw.c | 45 > --- > 1 file

Re: [PATCH 2/2] drivers/perf: arm_pmu: Fix NULL pointer dereference during probe

Will Deacon writes: > On Sat, Aug 27, 2016 at 04:19:50PM +, Stefan Wahren wrote: >> Patch 7f1d642fbb5c ("drivers/perf: arm-pmu: Fix handling of SPI lacking >> interrupt-affinity property") unintended also fixes perf_event support >> for bcm2835 which doesn't have PMU

Re: [PATCH 2/2] drivers/perf: arm_pmu: Fix NULL pointer dereference during probe

Will Deacon writes: > On Sat, Aug 27, 2016 at 04:19:50PM +, Stefan Wahren wrote: >> Patch 7f1d642fbb5c ("drivers/perf: arm-pmu: Fix handling of SPI lacking >> interrupt-affinity property") unintended also fixes perf_event support >> for bcm2835 which doesn't have PMU interrupts.

Re: [RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

在 2016/8/31 19:48, Arnd Bergmann 写道: On Wednesday, August 31, 2016 7:48:14 PM CEST Dongdong Liu wrote: +static struct hisi_rc_res rc_res[] = { + { + HIP05, + { + DEFINE_RES_MEM(0xb007, SZ_4K), +

Re: [RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

在 2016/8/31 19:48, Arnd Bergmann 写道: On Wednesday, August 31, 2016 7:48:14 PM CEST Dongdong Liu wrote: +static struct hisi_rc_res rc_res[] = { + { + HIP05, + { + DEFINE_RES_MEM(0xb007, SZ_4K), +

Re: [PATCH] i2c: rk3x: Restore clock settings at resume time

Hi Doug, Last replied email HTML HEAD error, resend it. 在 2016/8/30 5:22, Douglas Anderson 写道: Depending on a number of factors including: - Which exact Rockchip SoC we're working with - How deep we suspend - Which i2c port we're on We might lose the state of the i2c registers at suspend

Re: [PATCH] i2c: rk3x: Restore clock settings at resume time

Hi Doug, Last replied email HTML HEAD error, resend it. 在 2016/8/30 5:22, Douglas Anderson 写道: Depending on a number of factors including: - Which exact Rockchip SoC we're working with - How deep we suspend - Which i2c port we're on We might lose the state of the i2c registers at suspend

Re: [PATCH v2 00/11] staging: octeon: multi rx group (queue) support

On 8/31/16 13:57, Aaro Koskinen wrote: > This series implements multiple RX group support that should improve > the networking performance on multi-core OCTEONs. Basically we register > IRQ and NAPI for each group, and ask the HW to select the group for > the incoming packets based on hash. > >

Re: [PATCH v2 00/11] staging: octeon: multi rx group (queue) support

On 8/31/16 13:57, Aaro Koskinen wrote: > This series implements multiple RX group support that should improve > the networking performance on multi-core OCTEONs. Basically we register > IRQ and NAPI for each group, and ask the HW to select the group for > the incoming packets based on hash. > >

Re: [RFC PATCH V2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI

在 2016/8/31 19:45, Arnd Bergmann 写道: On Wednesday, August 31, 2016 7:48:12 PM CEST Dongdong Liu wrote: + +/* HipXX PCIe host only supports 32-bit config access */ +int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size, + u32 *val) +{ + u32

Re: [RFC PATCH V2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI

在 2016/8/31 19:45, Arnd Bergmann 写道: On Wednesday, August 31, 2016 7:48:12 PM CEST Dongdong Liu wrote: + +/* HipXX PCIe host only supports 32-bit config access */ +int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size, + u32 *val) +{ + u32

Re: [PATCH 2/2] staging: lustre: hide unused variable

> After a code cleanup, we get a harmless warning about a variable > that is unused when CONFIG_FS_POSIX_ACL is disabled: > > drivers/staging/lustre/lustre/llite/xattr.c: In function > 'll_xattr_get_common': > drivers/staging/lustre/lustre/llite/xattr.c:312:24: error: unused variable > 'lli'

Re: [PATCH 2/2] staging: lustre: hide unused variable

> After a code cleanup, we get a harmless warning about a variable > that is unused when CONFIG_FS_POSIX_ACL is disabled: > > drivers/staging/lustre/lustre/llite/xattr.c: In function > 'll_xattr_get_common': > drivers/staging/lustre/lustre/llite/xattr.c:312:24: error: unused variable > 'lli'

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