This patchset is for updating the LZ4 compression module to a version based
on LZ4 v1.7.3 allowing to use the fast compression algorithm aka LZ4 fast
which provides an "acceleration" parameter as a tradeoff between
high compression ratio and high compression speed.
We want to use LZ4 fast in
This patch updates the unlz4 wrapper to work with the
updated LZ4 kernel module version.
Signed-off-by: Sven Schmidt <4ssch...@informatik.uni-hamburg.de>
---
lib/decompress_unlz4.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/lib/decompress_unlz4.c
On Tue, Jan 24, 2017 at 03:05:23PM +0800, zhichang.yuan wrote:
> There are some special ISA/LPC devices that work on a specific I/O range where
> it is not correct to specify a 'ranges' property in DTS parent node as cpu
> addresses translated from DTS node are only for memory space on some
>
On Tue, Jan 24, 2017 at 03:05:23PM +0800, zhichang.yuan wrote:
> There are some special ISA/LPC devices that work on a specific I/O range where
> it is not correct to specify a 'ranges' property in DTS parent node as cpu
> addresses translated from DTS node are only for memory space on some
>
This patch add a new memory migration helpers, which migrate memory
backing a range of virtual address of a process to different memory
(which can be allocated through special allocator). It differs from
numa migration by working on a range of virtual address and thus by
doing migration in chunk
This patch add a new memory migration helpers, which migrate memory
backing a range of virtual address of a process to different memory
(which can be allocated through special allocator). It differs from
numa migration by working on a range of virtual address and thus by
doing migration in chunk
Hi!
> > > Can I get the copy of the patch?
> > >
> > > http://www.spinics.net/lists/linux-usb/msg152542.html
> > >
> > > ...but it is html mangled with no obvious way to unmangle it.
>
> Bounced it to you. FYI, patchwork.kernel.org should have it too, the
> "mbox" option there works the best.
Hi!
> > > Can I get the copy of the patch?
> > >
> > > http://www.spinics.net/lists/linux-usb/msg152542.html
> > >
> > > ...but it is html mangled with no obvious way to unmangle it.
>
> Bounced it to you. FYI, patchwork.kernel.org should have it too, the
> "mbox" option there works the best.
This is derived from the downstream tree's build system, but with just
a single Kconfig option.
For now the driver only builds on 32-bit arm -- the aarch64 build
breaks due to the driver using arm-specific cache flushing functions.
Signed-off-by: Eric Anholt
---
This is derived from the downstream tree's build system, but with just
a single Kconfig option.
For now the driver only builds on 32-bit arm -- the aarch64 build
breaks due to the driver using arm-specific cache flushing functions.
Signed-off-by: Eric Anholt
---
drivers/staging/media/Kconfig
Signed-off-by: Eric Anholt
---
drivers/staging/media/platform/bcm2835/TODO | 39 +
1 file changed, 39 insertions(+)
create mode 100644 drivers/staging/media/platform/bcm2835/TODO
diff --git a/drivers/staging/media/platform/bcm2835/TODO
Signed-off-by: Eric Anholt
---
drivers/staging/media/platform/bcm2835/TODO | 39 +
1 file changed, 39 insertions(+)
create mode 100644 drivers/staging/media/platform/bcm2835/TODO
diff --git a/drivers/staging/media/platform/bcm2835/TODO
Here's my first pass at importing the camera driver. There's a bunch
of TODO left to it, most of which is documented, and the rest being
standard checkpatch fare.
Unfortunately, when I try modprobing it on my pi3, the USB network
device dies, consistently. I'm not sure what's going on here yet,
Here's my first pass at importing the camera driver. There's a bunch
of TODO left to it, most of which is documented, and the rest being
standard checkpatch fare.
Unfortunately, when I try modprobing it on my pi3, the USB network
device dies, consistently. I'm not sure what's going on here yet,
49bec49fd7f2 ("staging: vc04_services: remove vchiq_copy_from_user")
removed the flags/msg_handle arguments, which were unused, and pushed
the implementation of copying using memcpy vs copy_from_user to the
caller.
Signed-off-by: Eric Anholt
---
49bec49fd7f2 ("staging: vc04_services: remove vchiq_copy_from_user")
removed the flags/msg_handle arguments, which were unused, and pushed
the implementation of copying using memcpy vs copy_from_user to the
caller.
Signed-off-by: Eric Anholt
---
Generated with checkpatch.pl --fix-inplace and git add -p out of the
results.
Signed-off-by: Eric Anholt
---
drivers/staging/media/platform/bcm2835/bcm2835-camera.c | 6 +++---
drivers/staging/media/platform/bcm2835/mmal-vchiq.c | 12 ++--
2 files changed, 9
Generated with checkpatch.pl --fix-inplace and git add -p out of the
results.
Signed-off-by: Eric Anholt
---
drivers/staging/media/platform/bcm2835/bcm2835-camera.c | 6 +++---
drivers/staging/media/platform/bcm2835/mmal-vchiq.c | 12 ++--
2 files changed, 9 insertions(+), 9
This handle page fault on behalf of device driver, unlike handle_mm_fault()
it does not trigger migration back to system memory for device memory.
Signed-off-by: Jérôme Glisse
Signed-off-by: Evgeny Baskakov
Signed-off-by: John Hubbard
This handle page fault on behalf of device driver, unlike handle_mm_fault()
it does not trigger migration back to system memory for device memory.
Signed-off-by: Jérôme Glisse
Signed-off-by: Evgeny Baskakov
Signed-off-by: John Hubbard
Signed-off-by: Mark Hairgrove
Signed-off-by: Sherry Cheung
Common case for migration of virtual address range is page are map
only once inside the vma in which migration is taking place. Because
we already walk the CPU page table for that range we can directly do
the unmap there and setup special migration swap entry.
Signed-off-by: Jérôme Glisse
Allow migration without copy in case destination page already have
source page content. This is usefull for new dma capable migration
where use device dma engine to copy pages.
This feature need carefull audit of filesystem code to make sure
that no one can write to the source page while it is
Common case for migration of virtual address range is page are map
only once inside the vma in which migration is taking place. Because
we already walk the CPU page table for that range we can directly do
the unmap there and setup special migration swap entry.
Signed-off-by: Jérôme Glisse
Allow migration without copy in case destination page already have
source page content. This is usefull for new dma capable migration
where use device dma engine to copy pages.
This feature need carefull audit of filesystem code to make sure
that no one can write to the source page while it is
HMM provides 3 separate functionality :
- Mirroring: synchronize CPU page table and device page table
- Device memory: allocating struct page for device memory
- Migration: migrating regular memory to device memory
This patch introduces some common helpers and definitions to all of
This add support for un-addressable device memory. Such memory is hotpluged
only so we can have struct page but we should never map them as such memory
can not be accessed by CPU. For that reason it uses a special swap entry for
CPU page table entry.
This patch implement all the logic from
HMM provides 3 separate functionality :
- Mirroring: synchronize CPU page table and device page table
- Device memory: allocating struct page for device memory
- Migration: migrating regular memory to device memory
This patch introduces some common helpers and definitions to all of
This add support for un-addressable device memory. Such memory is hotpluged
only so we can have struct page but we should never map them as such memory
can not be accessed by CPU. For that reason it uses a special swap entry for
CPU page table entry.
This patch implement all the logic from
pcie_bus_configure_settings() needs to be called on each of the root
ports to allow for the MPS to be configured for all of the children
devices.
Signed-off-by: Jon Mason
---
drivers/pci/host/pcie-iproc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
pcie_bus_configure_settings() needs to be called on each of the root
ports to allow for the MPS to be configured for all of the children
devices.
Signed-off-by: Jon Mason
---
drivers/pci/host/pcie-iproc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
The Broadcom Northstar2 SoC has a number of quirks for the PAXC
(internal/fake) PCI bus. Specifically, the PCI config space is shared
between the root port and the first PF (ie., PF0), and a number of
fields are tied to zero (thus preventing them from being set). These
cannot be "fixed" in
The Broadcom Northstar2 SoC has a number of quirks for the PAXC
(internal/fake) PCI bus. Specifically, the PCI config space is shared
between the root port and the first PF (ie., PF0), and a number of
fields are tied to zero (thus preventing them from being set). These
cannot be "fixed" in
Experience have shown that the using the autocalibration could severely
degrade the performances of the MMC bus.
Allwinner is using in its BSP a delay set to 0 for all the modes but HS400.
Remove the calibration code for now, and add comments to document our
findings.
Reviewed-by: Andre
Experience have shown that the using the autocalibration could severely
degrade the performances of the MMC bus.
Allwinner is using in its BSP a delay set to 0 for all the modes but HS400.
Remove the calibration code for now, and add comments to document our
findings.
Reviewed-by: Andre
The MMC2 controller on the A64 is kind of a special beast.
While the general controller design is the same than the other MMC
controllers in the SoC, it also has a bunch of features and changes that
prevent it to be driven in the same way.
It has for example a different bus width limit, a
The MMC2 controller on the A64 is kind of a special beast.
While the general controller design is the same than the other MMC
controllers in the SoC, it also has a bunch of features and changes that
prevent it to be driven in the same way.
It has for example a different bus width limit, a
The MMC core assumes that the code will gate the clock when the bus
frequency is set to 0, which we've been ignoring so far.
Handle that.
Signed-off-by: Maxime Ripard
Tested-by: Florian Vaussard
---
drivers/mmc/host/sunxi-mmc.c |
The A64 only has a single set of pins for each MMC controller. Since we
already have boards that require all of them, let's add them to the DTSI.
Reviewed-by: Andre Przywara
Signed-off-by: Maxime Ripard
Tested-by: Florian Vaussard
The MMC core assumes that the code will gate the clock when the bus
frequency is set to 0, which we've been ignoring so far.
Handle that.
Signed-off-by: Maxime Ripard
Tested-by: Florian Vaussard
---
drivers/mmc/host/sunxi-mmc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
The A64 only has a single set of pins for each MMC controller. Since we
already have boards that require all of them, let's add them to the DTSI.
Reviewed-by: Andre Przywara
Signed-off-by: Maxime Ripard
Tested-by: Florian Vaussard
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25
From: Andre Przywara
The Banana Pi M64 board is a typical single board computer based on the
Allwinner A64 SoC. Aside from the usual peripherals it features eMMC
storage, which is connected to the 8-bit capable SDHC2 controller.
Also it has a soldered WiFi/Bluetooth chip,
The A64 MMC controllers need to set a "new timings" bit when a new rate is
set.
The actual meaning of that bit is not clear yet, but not setting it leads
to some corner-case issues, like the CMD53 failing, which is used to
implement SDIO packet aggregation.
Signed-off-by: Maxime Ripard
Add a bit more debug messages that can be helpful when debugging the clock
setup.
Also fill the actual_clock field in struct mmc_host to report properly the
current frequency in debugfs.
Signed-off-by: Maxime Ripard
Tested-by: Florian Vaussard
From: Andre Przywara
The Banana Pi M64 board is a typical single board computer based on the
Allwinner A64 SoC. Aside from the usual peripherals it features eMMC
storage, which is connected to the 8-bit capable SDHC2 controller.
Also it has a soldered WiFi/Bluetooth chip, so we enable UART1 and
The A64 MMC controllers need to set a "new timings" bit when a new rate is
set.
The actual meaning of that bit is not clear yet, but not setting it leads
to some corner-case issues, like the CMD53 failing, which is used to
implement SDIO packet aggregation.
Signed-off-by: Maxime Ripard
Add a bit more debug messages that can be helpful when debugging the clock
setup.
Also fill the actual_clock field in struct mmc_host to report properly the
current frequency in debugfs.
Signed-off-by: Maxime Ripard
Tested-by: Florian Vaussard
---
drivers/mmc/host/sunxi-mmc.c | 23
From: Andre Przywara
The A64 has 3 MMC controllers, one of them being especially targeted to
eMMC. Among other things, it has a data strobe signal and a 8 bits data
width.
The two other are more usual controllers that will have a 4 bits width at
most and no data strobe
From: Andre Przywara
The A64 has 3 MMC controllers, one of them being especially targeted to
eMMC. Among other things, it has a data strobe signal and a 8 bits data
width.
The two other are more usual controllers that will have a 4 bits width at
most and no data strobe signal, which limits it
Hi Mark,
On 01/27/2017 09:38 AM, Mark Rutland wrote:
> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
>> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries
>> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum
>> is
Hi Mark,
On 01/27/2017 09:38 AM, Mark Rutland wrote:
> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
>> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries
>> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum
>> is
This introduce a simple struct and associated helpers for device driver
to use when hotpluging un-addressable device memory as ZONE_DEVICE. It
will find a unuse physical address range and trigger memory hotplug for
it which allocates and initialize struct page for the device memory.
This introduce a simple struct and associated helpers for device driver
to use when hotpluging un-addressable device memory as ZONE_DEVICE. It
will find a unuse physical address range and trigger memory hotplug for
it which allocates and initialize struct page for the device memory.
The A64 MMC controllers need DATA0 to be masked while updating the clock,
otherwise any subsequent command will result in a timeout.
It's not really clear at this point what DATA0 is exactly, but this
behaviour is present in Allwinner's tree, and has been suggested by
Allwinner engineers as fixes
The A64 MMC controllers need DATA0 to be masked while updating the clock,
otherwise any subsequent command will result in a timeout.
It's not really clear at this point what DATA0 is exactly, but this
behaviour is present in Allwinner's tree, and has been suggested by
Allwinner engineers as fixes
This does not use existing page table walker because we want to share
same code for our page fault handler.
Signed-off-by: Jérôme Glisse
Signed-off-by: Evgeny Baskakov
Signed-off-by: John Hubbard
Signed-off-by: Mark Hairgrove
This is a heterogeneous memory management (HMM) process address space
mirroring. In a nutshell this provide an API to mirror process address
space on a device. This boils down to keeping CPU and device page table
synchronize (we assume that both device and CPU are cache coherent like
PCIe device
This does not use existing page table walker because we want to share
same code for our page fault handler.
Signed-off-by: Jérôme Glisse
Signed-off-by: Evgeny Baskakov
Signed-off-by: John Hubbard
Signed-off-by: Mark Hairgrove
Signed-off-by: Sherry Cheung
Signed-off-by: Subhash Gutti
---
This is a heterogeneous memory management (HMM) process address space
mirroring. In a nutshell this provide an API to mirror process address
space on a device. This boils down to keeping CPU and device page table
synchronize (we assume that both device and CPU are cache coherent like
PCIe device
It does not need much, just skip populating kernel linear mapping
for range of un-addressable device memory (it is pick so that there
is no physical memory resource overlapping it). All the logic is in
share mm code.
Only support x86-64 as this feature doesn't make much sense with
constrained
It does not need much, just skip populating kernel linear mapping
for range of un-addressable device memory (it is pick so that there
is no physical memory resource overlapping it). All the logic is in
share mm code.
Only support x86-64 as this feature doesn't make much sense with
constrained
Allow to unmap and restore special swap entry of un-addressable
ZONE_DEVICE memory.
Signed-off-by: Jérôme Glisse
---
include/linux/migrate.h | 2 +
mm/migrate.c| 134 +---
mm/rmap.c | 47
Allow to unmap and restore special swap entry of un-addressable
ZONE_DEVICE memory.
Signed-off-by: Jérôme Glisse
---
include/linux/migrate.h | 2 +
mm/migrate.c| 134 +---
mm/rmap.c | 47 +
3 files changed,
This introduce a dummy HMM device class so device driver can use it to
create hmm_device for the sole purpose of registering device memory.
It is usefull to device driver that want to manage multiple physical
device memory under same struct device umbrella.
Changed since v1:
- Improve commit
This introduce a dummy HMM device class so device driver can use it to
create hmm_device for the sole purpose of registering device memory.
It is usefull to device driver that want to manage multiple physical
device memory under same struct device umbrella.
Changed since v1:
- Improve commit
When a ZONE_DEVICE page refcount reach 1 it means it is free and nobody
is holding a reference on it (only device to which the memory belong do).
Add a callback and call it when that happen so device driver can implement
their own free page management.
Changed since v1:
- Do not update
When hotpluging memory we want more informations on the type of memory and
its properties. Replace the device boolean flag by an int and define a set
of flags.
New property for device memory is an opt-in flag to allow page migration
from and to a ZONE_DEVICE. Existing user of ZONE_DEVICE are not
When a ZONE_DEVICE page refcount reach 1 it means it is free and nobody
is holding a reference on it (only device to which the memory belong do).
Add a callback and call it when that happen so device driver can implement
their own free page management.
Changed since v1:
- Do not update
When hotpluging memory we want more informations on the type of memory and
its properties. Replace the device boolean flag by an int and define a set
of flags.
New property for device memory is an opt-in flag to allow page migration
from and to a ZONE_DEVICE. Existing user of ZONE_DEVICE are not
Cliff note: HMM offers 2 things (each standing on its own). First
it allows to use device memory transparently inside any process
without any modifications to process program code. Second it allows
to mirror process address space on a device.
Change since v16:
- move HMM unaddressable device
Cliff note: HMM offers 2 things (each standing on its own). First
it allows to use device memory transparently inside any process
without any modifications to process program code. Second it allows
to mirror process address space on a device.
Change since v16:
- move HMM unaddressable device
On Tue, Jan 24, 2017 at 10:32:25AM +0800, Chen-Yu Tsai wrote:
> Add support for the USB clock controls found on the A80.
>
> Signed-off-by: Chen-Yu Tsai
> ---
> .../devicetree/bindings/clock/sun9i-usb.txt| 24
> drivers/clk/sunxi-ng/Makefile |
On Tue, Jan 24, 2017 at 10:32:25AM +0800, Chen-Yu Tsai wrote:
> Add support for the USB clock controls found on the A80.
>
> Signed-off-by: Chen-Yu Tsai
> ---
> .../devicetree/bindings/clock/sun9i-usb.txt| 24
> drivers/clk/sunxi-ng/Makefile | 1 +
>
On Wed, Jan 25, 2017 at 12:05 PM, Kees Cook wrote:
> On Tue, Jan 24, 2017 at 4:53 PM, Andrei Vagin wrote:
>> Hi,
>>
>> One of CRIU tests fails with this patch:
>> https://github.com/xemul/criu/blob/master/test/zdtm/static/seccomp_filter_tsync.c
>>
>>
On Wed, Jan 25, 2017 at 12:05 PM, Kees Cook wrote:
> On Tue, Jan 24, 2017 at 4:53 PM, Andrei Vagin wrote:
>> Hi,
>>
>> One of CRIU tests fails with this patch:
>> https://github.com/xemul/criu/blob/master/test/zdtm/static/seccomp_filter_tsync.c
>>
>> Before this patch only a thread which called
The entire patch set looks good to me. Thanks!
Acked-by: Ray Jui
On 1/27/2017 1:44 PM, Jon Mason wrote:
> A patch that corrects an issue where the MPS could not be set, and
> another that fixes some quirks in the PAXC
>
> Jon Mason (2):
> PCI: iproc: allow the MPS to be
The entire patch set looks good to me. Thanks!
Acked-by: Ray Jui
On 1/27/2017 1:44 PM, Jon Mason wrote:
> A patch that corrects an issue where the MPS could not be set, and
> another that fixes some quirks in the PAXC
>
> Jon Mason (2):
> PCI: iproc: allow the MPS to be set
> PCI: Add
From: Andre Przywara
On many boards UART1 connects to a Bluetooth chip, so add the pinctrl
nodes for the only pins providing access to that UART. That includes
those pins for hardware flow control (RTS/CTS).
Signed-off-by: Andre Przywara
From: Andre Przywara
All Pine64 boards connect an micro-SD card slot to the first MMC
controller.
Enable the respective DT node and specify the (always-on) regulator
and card-detect pin.
As a micro-SD slot does not feature a write-protect switch, we disable
this feature.
Hi,
Here is a new attempt at getting the MMC controllers running, following the
work done by Andre.
This has been tested on a board with one SDIO device (a Marvell WiFi chip)
and a Kingston eMMC with 1.8V IOs.
For SDIO, the HS DDR mode works just fine. That serie also enables the
SDR104 mode to
From: Andre Przywara
On many boards UART1 connects to a Bluetooth chip, so add the pinctrl
nodes for the only pins providing access to that UART. That includes
those pins for hardware flow control (RTS/CTS).
Signed-off-by: Andre Przywara
Signed-off-by: Maxime Ripard
---
From: Andre Przywara
All Pine64 boards connect an micro-SD card slot to the first MMC
controller.
Enable the respective DT node and specify the (always-on) regulator
and card-detect pin.
As a micro-SD slot does not feature a write-protect switch, we disable
this feature.
Signed-off-by: Andre
Hi,
Here is a new attempt at getting the MMC controllers running, following the
work done by Andre.
This has been tested on a board with one SDIO device (a Marvell WiFi chip)
and a Kingston eMMC with 1.8V IOs.
For SDIO, the HS DDR mode works just fine. That serie also enables the
SDR104 mode to
The SD specification documents that the clock frequency should only be
changed once gated (Section 3.2.3 - SD Clock Frequency Change Sequence).
The current code first modifies the parent clock, gates it and then
modifies the internal divider. This means that since the parent clock rate
might be
The SD specification documents that the clock frequency should only be
changed once gated (Section 3.2.3 - SD Clock Frequency Change Sequence).
The current code first modifies the parent clock, gates it and then
modifies the internal divider. This means that since the parent clock rate
might be
The eMMC controller seem to have a maximum frequency of 200MHz, while the
regular MMC controllers are capped at 150MHz.
Since older SoCs cannot go that high, we cannot change the default maximum
frequency, but fortunately for us we have a property for that in the DT.
This also has the side
The eMMC controller seem to have a maximum frequency of 200MHz, while the
regular MMC controllers are capped at 150MHz.
Since older SoCs cannot go that high, we cannot change the default maximum
frequency, but fortunately for us we have a property for that in the DT.
This also has the side
A patch that corrects an issue where the MPS could not be set, and
another that fixes some quirks in the PAXC
Jon Mason (2):
PCI: iproc: allow the MPS to be set
PCI: Add quirk entry for NS2 PAXC PCI
drivers/pci/host/pcie-iproc.c | 5 -
drivers/pci/quirks.c | 21
A patch that corrects an issue where the MPS could not be set, and
another that fixes some quirks in the PAXC
Jon Mason (2):
PCI: iproc: allow the MPS to be set
PCI: Add quirk entry for NS2 PAXC PCI
drivers/pci/host/pcie-iproc.c | 5 -
drivers/pci/quirks.c | 21
When a non-cooperative userfaultfd monitor copies pages in the background,
it may encounter regions that were already unmapped. Addition of
UFFD_EVENT_UNMAP allows the uffd monitor to track precisely changes in the
virtual memory layout.
Since there might be different uffd contexts for the
When a non-cooperative userfaultfd monitor copies pages in the background,
it may encounter regions that were already unmapped. Addition of
UFFD_EVENT_UNMAP allows the uffd monitor to track precisely changes in the
virtual memory layout.
Since there might be different uffd contexts for the
On 27 January 2017 at 05:31, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> On Thu, Jan 26, 2017 at 11:40:57AM +0200, Alexander Shishkin wrote:
>>> +if (!ifh->nr_file_filters)
>>> +return;
>>
>> Is this
On 27 January 2017 at 05:31, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> On Thu, Jan 26, 2017 at 11:40:57AM +0200, Alexander Shishkin wrote:
>>> +if (!ifh->nr_file_filters)
>>> +return;
>>
>> Is this mandatory or an optimisation to avoid circling through a list of
On Fri, Jan 27, 2017 at 12:53:38PM -0800, Linus Torvalds wrote:
> On Fri, Jan 27, 2017 at 10:23 AM, Luis R. Rodriguez wrote:
> >> So I'm really not seeing why you want to make these conversions that
> >> just make code worse.
> >
> > The real goal here was first to actually
On Fri, Jan 27, 2017 at 12:53:38PM -0800, Linus Torvalds wrote:
> On Fri, Jan 27, 2017 at 10:23 AM, Luis R. Rodriguez wrote:
> >> So I'm really not seeing why you want to make these conversions that
> >> just make code worse.
> >
> > The real goal here was first to actually provide a flexible API
Hi,
Please pull MD fixes. This pull fixes several corner cases for raid5 cache,
which is merged into this cycle.
Thanks,
Shaohua
The following changes since commit 557ed56cc75e0a33c15ba438734a280bac23bd32:
Merge tag 'sound-4.10-rc4' of
e system]
>
> url:
> https://github.com/0day-ci/linux/commits/Mika-Westerberg/pinctrl-intel-Add-support-for-hardware-debouncer/20170127-181144
> base:
> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
> for-next
> config: x86_64-randconfig-s5-0127185
Hi,
Please pull MD fixes. This pull fixes several corner cases for raid5 cache,
which is merged into this cycle.
Thanks,
Shaohua
The following changes since commit 557ed56cc75e0a33c15ba438734a280bac23bd32:
Merge tag 'sound-4.10-rc4' of
e system]
>
> url:
> https://github.com/0day-ci/linux/commits/Mika-Westerberg/pinctrl-intel-Add-support-for-hardware-debouncer/20170127-181144
> base:
> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
> for-next
> config: x86_64-randconfig-s5-0127185
On Fri, 2017-01-27 at 14:15 +0100, Christophe JAILLET wrote:
> This test looks reverted.
> We should log an error message only if 'ib_attach_mcast()' fails.
>
> Signed-off-by: Christophe JAILLET
> ---
> drivers/infiniband/core/cma.c | 2 +-
> 1 file changed, 1
On Fri, 2017-01-27 at 14:15 +0100, Christophe JAILLET wrote:
> This test looks reverted.
> We should log an error message only if 'ib_attach_mcast()' fails.
>
> Signed-off-by: Christophe JAILLET
> ---
> drivers/infiniband/core/cma.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
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