On Thu, Jun 08, 2017 at 11:13:56AM +0530, Varadarajan Narayanan wrote:
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for ipq8074.
>
> Signed-off-by: Manoharan Vijaya Raghavan
> Signed-off-by: Varadarajan Narayanan
On Thu, Jun 08, 2017 at 11:13:56AM +0530, Varadarajan Narayanan wrote:
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for ipq8074.
>
> Signed-off-by: Manoharan Vijaya Raghavan
> Signed-off-by: Varadarajan Narayanan
> ---
>
> So actually in this LSM it's not so much full paths that are trusted,
> rather it checks that the directory containing the program is only
> writable by root and that the program itself is only writable by root.
>
> For example, consider the following:
>
> /user/ with permissions drwxr-xr-x
Add a test to verify that the registers passed in pt_regs on kprobe
(trap), optprobe (jump) and kprobe_on_ftrace (ftrace_caller) are
accurate. The tests are exercized if KPROBES_SANITY_TEST is enabled.
Implemented for powerpc64. Other architectures will have to implement
the relevant arch_*
> So actually in this LSM it's not so much full paths that are trusted,
> rather it checks that the directory containing the program is only
> writable by root and that the program itself is only writable by root.
>
> For example, consider the following:
>
> /user/ with permissions drwxr-xr-x
Add a test to verify that the registers passed in pt_regs on kprobe
(trap), optprobe (jump) and kprobe_on_ftrace (ftrace_caller) are
accurate. The tests are exercized if KPROBES_SANITY_TEST is enabled.
Implemented for powerpc64. Other architectures will have to implement
the relevant arch_*
On Fri, Jun 02, 2017 at 04:03:06PM +0100, Richard Fitzgerald wrote:
> The Cirrus Logic Madera codecs are a family of related codecs with
> extensive digital and analogue I/O, digital mixing and routing,
> signal processing and programmable DSPs.
>
> Signed-off-by: Richard Fitzgerald
On Fri, Jun 02, 2017 at 04:03:06PM +0100, Richard Fitzgerald wrote:
> The Cirrus Logic Madera codecs are a family of related codecs with
> extensive digital and analogue I/O, digital mixing and routing,
> signal processing and programmable DSPs.
>
> Signed-off-by: Richard Fitzgerald
> ---
>
Am 08.06.2017 um 20:53 schrieb Logan Gunthorpe:
> Any thoughts on this? My patches for the other architectures are already
> in linux-next. um is the only one that remains.
IMHO an ifdef in scatterlist code does not hurt.
It is equally ugly than mocking ioremap for UML.
So, I'm puzzled.
Arnd,
Am 08.06.2017 um 20:53 schrieb Logan Gunthorpe:
> Any thoughts on this? My patches for the other architectures are already
> in linux-next. um is the only one that remains.
IMHO an ifdef in scatterlist code does not hurt.
It is equally ugly than mocking ioremap for UML.
So, I'm puzzled.
Arnd,
Hi Alex,
On Thu, Jun 08, 2017 at 08:44:35PM +0300, Alex A. Mihaylov wrote:
> 08.06.17 15:48, Sebastian Reichel wrote:
> > On Fri, Jun 02, 2017 at 10:06:29AM +0300, Alex A. Mihaylov wrote:
> > > diff --git a/drivers/power/supply/max1721x_battery.c
> > > b/drivers/power/supply/max1721x_battery.c
>
Hi Alex,
On Thu, Jun 08, 2017 at 08:44:35PM +0300, Alex A. Mihaylov wrote:
> 08.06.17 15:48, Sebastian Reichel wrote:
> > On Fri, Jun 02, 2017 at 10:06:29AM +0300, Alex A. Mihaylov wrote:
> > > diff --git a/drivers/power/supply/max1721x_battery.c
> > > b/drivers/power/supply/max1721x_battery.c
>
On Fri, Jun 02, 2017 at 04:03:03PM +0100, Richard Fitzgerald wrote:
> This is the binding description of the pinctrl driver for Cirru Logic
> Madera codecs. The binding uses the generic pinctrl binding so the main
> purpose here is to describe the device-specific names for groups and
> functions.
On Fri, Jun 02, 2017 at 04:03:03PM +0100, Richard Fitzgerald wrote:
> This is the binding description of the pinctrl driver for Cirru Logic
> Madera codecs. The binding uses the generic pinctrl binding so the main
> purpose here is to describe the device-specific names for groups and
> functions.
On Fri, Jun 02, 2017 at 04:02:55PM +0100, Richard Fitzgerald wrote:
> Specification of the bindings for the parent MFD driver component
> of the Cirrus Logic Madera codec drivers.
>
> Note that although the interrupt controller and GPIO are child
> drivers their required bindings are trivial,
On Fri, Jun 02, 2017 at 04:02:55PM +0100, Richard Fitzgerald wrote:
> Specification of the bindings for the parent MFD driver component
> of the Cirrus Logic Madera codec drivers.
>
> Note that although the interrupt controller and GPIO are child
> drivers their required bindings are trivial,
On Wed, Jun 07, 2017 at 09:36:45PM +, Levin, Alexander (Sasha Levin) wrote:
> On Wed, Jun 07, 2017 at 04:14:03PM +0200, Frederic Weisbecker wrote:
> > On Wed, Jun 07, 2017 at 04:17:41AM +, Levin, Alexander (Sasha Levin)
> > wrote:
> > > > Thanks Sasha!
> > > >
> > > > I couldn't
On Wed, Jun 07, 2017 at 09:36:45PM +, Levin, Alexander (Sasha Levin) wrote:
> On Wed, Jun 07, 2017 at 04:14:03PM +0200, Frederic Weisbecker wrote:
> > On Wed, Jun 07, 2017 at 04:17:41AM +, Levin, Alexander (Sasha Levin)
> > wrote:
> > > > Thanks Sasha!
> > > >
> > > > I couldn't
The mv88e6xxx driver accesses a port's netdev mostly for printing.
This is bad for 2 reasons: DSA and CPU ports do not have a netdev
pointer; it doesn't give us a correct picture of why a DSA driver might
need to access a port's netdev.
Introduce mv88e6xxx_{dbg,err,warn} macros to print messages
The mv88e6xxx driver accesses a port's netdev mostly for printing.
This is bad for 2 reasons: DSA and CPU ports do not have a netdev
pointer; it doesn't give us a correct picture of why a DSA driver might
need to access a port's netdev.
Introduce mv88e6xxx_{dbg,err,warn} macros to print messages
As for the frame mode, add a mv88e6xxx_egress_mode enumeration instead
of a 16-bit register mask.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/chip.c | 11 ++-
drivers/net/dsa/mv88e6xxx/chip.h | 7 +++
As for the frame mode, add a mv88e6xxx_egress_mode enumeration instead
of a 16-bit register mask.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/chip.c | 11 ++-
drivers/net/dsa/mv88e6xxx/chip.h | 7 +++
drivers/net/dsa/mv88e6xxx/port.c | 20 ++--
All Marvell chips supporting Pause frames limiting use 1-byte value for
input and output.
Old chips have both bytes adjacent in a 16-bit register. New ones have
an indirect table using 8-bit data.
The mv88e6xxx library functions (such as in port.c) must not contain
driver logic, but only generic
All Marvell chips supporting Pause frames limiting use 1-byte value for
input and output.
Old chips have both bytes adjacent in a 16-bit register. New ones have
an indirect table using 8-bit data.
The mv88e6xxx library functions (such as in port.c) must not contain
driver logic, but only generic
Marvell chips have a Jumbo Mode to set the maximum frame size (MTU).
The mv88e6xxx_ops structure is meant to contain generic functionalities,
no driver logic. Change port_jumbo_config to port_set_jumbo_size setting
the mode from a given maximum size value.
There is no functional changes since we
Marvell chips have a Jumbo Mode to set the maximum frame size (MTU).
The mv88e6xxx_ops structure is meant to contain generic functionalities,
no driver logic. Change port_jumbo_config to port_set_jumbo_size setting
the mode from a given maximum size value.
There is no functional changes since we
Prefix the PHY_* macros with a Marvell specific MV88E6XXX_ prefix.
There is no functional changes.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/phy.c | 11 ++-
drivers/net/dsa/mv88e6xxx/phy.h | 4 ++--
2 files changed, 8
Prefix the PHY_* macros with a Marvell specific MV88E6XXX_ prefix.
There is no functional changes.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/phy.c | 11 ++-
drivers/net/dsa/mv88e6xxx/phy.h | 4 ++--
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git
On 08/06/17 19:41, Alexei Starovoitov wrote:
> On Thu, Jun 08, 2017 at 06:12:39PM +0100, Edward Cree wrote:
>> On 08/06/17 17:50, Alexei Starovoitov wrote:
>>> On Thu, Jun 08, 2017 at 04:25:39PM +0100, Edward Cree wrote:
On 08/06/17 03:35, Alexei Starovoitov wrote:
> such large back and
On 08/06/17 19:41, Alexei Starovoitov wrote:
> On Thu, Jun 08, 2017 at 06:12:39PM +0100, Edward Cree wrote:
>> On 08/06/17 17:50, Alexei Starovoitov wrote:
>>> On Thu, Jun 08, 2017 at 04:25:39PM +0100, Edward Cree wrote:
On 08/06/17 03:35, Alexei Starovoitov wrote:
> such large back and
The mv88e6xxx_ops describe functionalities, regardless their locations
(which can be Global1, Global2, or whatever register set.)
Rename the g1_set_cpu_port and g1_set_egress_port ops to set_cpu_port
and set_egress_port. No functional changes.
Signed-off-by: Vivien Didelot
The mv88e6xxx_ops describe functionalities, regardless their locations
(which can be Global1, Global2, or whatever register set.)
Rename the g1_set_cpu_port and g1_set_egress_port ops to set_cpu_port
and set_egress_port. No functional changes.
Signed-off-by: Vivien Didelot
---
This patchset brings no functional changes. It is a first step in a
bigger cosmetics change to the driver. It provides macros and polishes
data types and chip operations.
The next patchs will only prefix and document the port registers macros.
Vivien Didelot (7):
net: dsa: mv88e6xxx: provide
This patchset brings no functional changes. It is a first step in a
bigger cosmetics change to the driver. It provides macros and polishes
data types and chip operations.
The next patchs will only prefix and document the port registers macros.
Vivien Didelot (7):
net: dsa: mv88e6xxx: provide
On Thu, Jun 8, 2017 at 11:09 AM, David Miller wrote:
> From: "Luis R. Rodriguez"
> Date: Thu, 8 Jun 2017 18:19:42 +0200
>
>> On Thu, Jun 08, 2017 at 02:53:22PM +0300, Kalle Valo wrote:
>>> "Luis R. Rodriguez" writes:
>>>
>>> > Dear vger
On Thu, Jun 8, 2017 at 11:09 AM, David Miller wrote:
> From: "Luis R. Rodriguez"
> Date: Thu, 8 Jun 2017 18:19:42 +0200
>
>> On Thu, Jun 08, 2017 at 02:53:22PM +0300, Kalle Valo wrote:
>>> "Luis R. Rodriguez" writes:
>>>
>>> > Dear vger postmaster,
>>> >
>>> > I think its time for a
Reuse the BR_STATE_* values to abstract a port STP state value.
This provides shorter names and better control over the DSA switch
operation call.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/chip.c | 23 ++-
Reuse the BR_STATE_* values to abstract a port STP state value.
This provides shorter names and better control over the DSA switch
operation call.
Signed-off-by: Vivien Didelot
---
drivers/net/dsa/mv88e6xxx/chip.c | 23 ++-
drivers/net/dsa/mv88e6xxx/port.c | 20
> -Original Message-
> From: Alan Cox [mailto:gno...@lxorguk.ukuu.org.uk]
> Sent: Thursday, June 8, 2017 11:23 AM
> To: Shaikh, Azhar
> Cc: jarkko.sakki...@linux.intel.com; jguntho...@obsidianresearch.com;
> tpmdd-de...@lists.sourceforge.net;
> -Original Message-
> From: Alan Cox [mailto:gno...@lxorguk.ukuu.org.uk]
> Sent: Thursday, June 8, 2017 11:23 AM
> To: Shaikh, Azhar
> Cc: jarkko.sakki...@linux.intel.com; jguntho...@obsidianresearch.com;
> tpmdd-de...@lists.sourceforge.net; linux-kernel@vger.kernel.org; linux-
>
On Sun, Jun 4, 2017 at 11:52 AM, Thomas Gleixner wrote:
> On Wed, 31 May 2017, John Stultz wrote:
>>
>> The one exception where this helper isn't necessary is for the
>> fast-timekepers which use their own locking and update logic
>> to the tkr structures.
>
> That's simply
On Sun, Jun 4, 2017 at 11:52 AM, Thomas Gleixner wrote:
> On Wed, 31 May 2017, John Stultz wrote:
>>
>> The one exception where this helper isn't necessary is for the
>> fast-timekepers which use their own locking and update logic
>> to the tkr structures.
>
> That's simply wrong. The fast time
Am 08.06.2017 um 08:26 schrieb Srinivas Kandagatla:
>
>
> On 07/06/17 22:55, Heiner Kallweit wrote:
>> Am 07.06.2017 um 18:19 schrieb Srinivas Kandagatla:
>>>
>>> On 04/06/17 12:06, Heiner Kallweit wrote:
Add a device-managed version of nvmem_register.
Signed-off-by: Heiner
Am 08.06.2017 um 08:26 schrieb Srinivas Kandagatla:
>
>
> On 07/06/17 22:55, Heiner Kallweit wrote:
>> Am 07.06.2017 um 18:19 schrieb Srinivas Kandagatla:
>>>
>>> On 04/06/17 12:06, Heiner Kallweit wrote:
Add a device-managed version of nvmem_register.
Signed-off-by: Heiner
On 6/8/17 2:37 PM, Alan Cox wrote:
>> http://phrack.org/issues/52/6.html#article
>>
>> | A trusted path is one that is inside a root owned directory that
>> | is not group or world writable. /bin, /usr/bin, /usr/local/bin, are
>> | (under normal circumstances) considered trusted. Any non-root
>>
On 6/8/17 2:37 PM, Alan Cox wrote:
>> http://phrack.org/issues/52/6.html#article
>>
>> | A trusted path is one that is inside a root owned directory that
>> | is not group or world writable. /bin, /usr/bin, /usr/local/bin, are
>> | (under normal circumstances) considered trusted. Any non-root
>>
On 06/08/2017 11:23 AM, Noam Camus wrote:
*> From:* Vineet Gupta
*> Sent:* Thursday, June 8, 2017 7:38 PM
>>
>> With simulator we just turn this configuration on, so we redirect the Legacy
>> Synopsys L2 ISR from nSIM into machine check.
>> This way we end up
On 06/08/2017 11:23 AM, Noam Camus wrote:
*> From:* Vineet Gupta
*> Sent:* Thursday, June 8, 2017 7:38 PM
>>
>> With simulator we just turn this configuration on, so we redirect the Legacy
>> Synopsys L2 ISR from nSIM into machine check.
>> This way we end up just like with silicon
>This
Any thoughts on this? My patches for the other architectures are already
in linux-next. um is the only one that remains.
Thanks,
Logan
On 27/05/17 12:15 PM, Logan Gunthorpe wrote:
> Hi,
>
> On 27/05/17 12:08 PM, Geert Uytterhoeven wrote:
>> Still, those code patch could be protected by #ifdef
Any thoughts on this? My patches for the other architectures are already
in linux-next. um is the only one that remains.
Thanks,
Logan
On 27/05/17 12:15 PM, Logan Gunthorpe wrote:
> Hi,
>
> On 27/05/17 12:08 PM, Geert Uytterhoeven wrote:
>> Still, those code patch could be protected by #ifdef
CPSW driver does not handle this interrupt, so there are no reasons to enable
it in hardware.
Signed-off-by: Grygorii Strashko
---
no changes, just resubmitting with proper subj line.
drivers/net/ethernet/ti/davinci_cpdma.c | 5 +
1 file changed, 1 insertion(+), 4
CPSW driver does not handle this interrupt, so there are no reasons to enable
it in hardware.
Signed-off-by: Grygorii Strashko
---
no changes, just resubmitting with proper subj line.
drivers/net/ethernet/ti/davinci_cpdma.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git
CPSW driver supports PTP v1 messages, but for unknown reasons this filter
is not advertised. As result,
./tools/testing/selftests/networking/timestamping/timestamping utility
can't be used for testing of CPSW RX timestamping with option
SOF_TIMESTAMPING_RX_HARDWARE, because it uses
CPSW driver supports PTP v1 messages, but for unknown reasons this filter
is not advertised. As result,
./tools/testing/selftests/networking/timestamping/timestamping utility
can't be used for testing of CPSW RX timestamping with option
SOF_TIMESTAMPING_RX_HARDWARE, because it uses
> For that purpose all that should be required is strong ordering of the
> outb relative to the other TPM commands at the LPC interface FIFO. I
> also think the wmb is not needed because outb is already defined to be
> strongly in order with respect to writel/readl ?
That's my assumption but
> For that purpose all that should be required is strong ordering of the
> outb relative to the other TPM commands at the LPC interface FIFO. I
> also think the wmb is not needed because outb is already defined to be
> strongly in order with respect to writel/readl ?
That's my assumption but
On Thu, Jun 8, 2017 at 9:41 PM, Alexandre Belloni
wrote:
> On 08/06/2017 at 20:57:05 +0300, Andy Shevchenko wrote:
>> On Thu, Jun 8, 2017 at 6:05 PM, Alexandre Belloni
>> wrote:
>> > I understand this may not fit your
On Thu, Jun 8, 2017 at 9:41 PM, Alexandre Belloni
wrote:
> On 08/06/2017 at 20:57:05 +0300, Andy Shevchenko wrote:
>> On Thu, Jun 8, 2017 at 6:05 PM, Alexandre Belloni
>> wrote:
>> > I understand this may not fit your debugging needs but what about pretty
>> > printing time64_t and using
Hi,
Got the following tip-bit about this patch performance impact.
Cheers,
Longman
Greeting,
FYI, we noticed a 125.4% improvement of will-it-scale.per_thread_ops due to
commit:
commit: a150752454e4aea37a44d7eb5baf5a538bcad6fc
Hi,
Got the following tip-bit about this patch performance impact.
Cheers,
Longman
Greeting,
FYI, we noticed a 125.4% improvement of will-it-scale.per_thread_ops due to
commit:
commit: a150752454e4aea37a44d7eb5baf5a538bcad6fc
On 08/06/2017 at 20:57:05 +0300, Andy Shevchenko wrote:
> On Thu, Jun 8, 2017 at 6:05 PM, Alexandre Belloni
> wrote:
> > On 08/06/2017 at 17:55:12 +0300, Andy Shevchenko wrote:
> >> On Thu, Jun 8, 2017 at 5:49 PM, Arnd Bergmann wrote:
> >> >
On 08/06/2017 at 20:57:05 +0300, Andy Shevchenko wrote:
> On Thu, Jun 8, 2017 at 6:05 PM, Alexandre Belloni
> wrote:
> > On 08/06/2017 at 17:55:12 +0300, Andy Shevchenko wrote:
> >> On Thu, Jun 8, 2017 at 5:49 PM, Arnd Bergmann wrote:
> >> > On Thu, Jun 8, 2017 at 3:47 PM, Andy Shevchenko
> >> >
On Thu, Jun 08, 2017 at 06:12:39PM +0100, Edward Cree wrote:
> On 08/06/17 17:50, Alexei Starovoitov wrote:
> > On Thu, Jun 08, 2017 at 04:25:39PM +0100, Edward Cree wrote:
> >> On 08/06/17 03:35, Alexei Starovoitov wrote:
> >>> such large back and forth move doesn't help reviewing.
> >>> may be
On Thu, Jun 08, 2017 at 06:12:39PM +0100, Edward Cree wrote:
> On 08/06/17 17:50, Alexei Starovoitov wrote:
> > On Thu, Jun 08, 2017 at 04:25:39PM +0100, Edward Cree wrote:
> >> On 08/06/17 03:35, Alexei Starovoitov wrote:
> >>> such large back and forth move doesn't help reviewing.
> >>> may be
On Thu, Jun 08, 2017 at 07:22:59PM +0100, Alan Cox wrote:
> > > > + outb(0x80, 0xCC);
> > > > +
> > > > + /* Make sure the above write is completed */
> > > > + wmb();
> > >
> > > Why the wmb(). It doesn't do what the comment says! Also this code is x86
> > > specific
> > >
>
On Thu, Jun 08, 2017 at 07:22:59PM +0100, Alan Cox wrote:
> > > > + outb(0x80, 0xCC);
> > > > +
> > > > + /* Make sure the above write is completed */
> > > > + wmb();
> > >
> > > Why the wmb(). It doesn't do what the comment says! Also this code is x86
> > > specific
> > >
>
On Fri, May 05, 2017 at 11:17:19AM -0700, Ricardo Neri wrote:
> The feature User-Mode Instruction Prevention present in recent Intel
> processor prevents a group of instructions from being executed with
> CPL > 0. Otherwise, a general protection fault is issued.
This is one of the best opening
On Fri, May 05, 2017 at 11:17:19AM -0700, Ricardo Neri wrote:
> The feature User-Mode Instruction Prevention present in recent Intel
> processor prevents a group of instructions from being executed with
> CPL > 0. Otherwise, a general protection fault is issued.
This is one of the best opening
On Thu, Jun 8, 2017 at 5:00 PM, Greg Kroah-Hartman
wrote:
> On Thu, Jun 08, 2017 at 04:47:52PM +0300, Andy Shevchenko wrote:
>> Use %pt instead of open coded variant to print content of
>> struct rtc_time in human readable format.
>>
>> Arnd Bergmann
>
On Thu, Jun 8, 2017 at 5:00 PM, Greg Kroah-Hartman
wrote:
> On Thu, Jun 08, 2017 at 04:47:52PM +0300, Andy Shevchenko wrote:
>> Use %pt instead of open coded variant to print content of
>> struct rtc_time in human readable format.
>>
>> Arnd Bergmann
>
> Cc: ?
Yep!
Fixed locally, will be in
ACPI 6.2 defines in section 9.20.7.2 that the OSPM may call a Start
ARS with Flags Bit [1] set upon receiving the 0x81 notification.
Upon receiving the notification, the OSPM may decide to issue
a Start ARS with Flags Bit [1] set to prepare for the retrieval
of existing records and issue
ACPI 6.2 defines a new ACPI notification value to NVDIMM Root Device.
This allows BIOS to inform the OS that new uncorrectable memory error
is detected during run-time.
This patch-set adds support of this notification, which starts ARS and
updates badblocks information to prevent the OS from
ACPI 6.2 defines in section 9.20.7.2 that the OSPM may call a Start
ARS with Flags Bit [1] set upon receiving the 0x81 notification.
Upon receiving the notification, the OSPM may decide to issue
a Start ARS with Flags Bit [1] set to prepare for the retrieval
of existing records and issue
ACPI 6.2 defines a new ACPI notification value to NVDIMM Root Device.
This allows BIOS to inform the OS that new uncorrectable memory error
is detected during run-time.
This patch-set adds support of this notification, which starts ARS and
updates badblocks information to prevent the OS from
ACPI 6.2 defines a new ACPI notification value to NVDIMM Root Device
in Table 5-169.
0x81 Unconsumed Uncorrectable Memory Error Detected
Used to pro-actively notify OSPM of uncorrectable memory errors
detected (for example a memory scrubbing engine that continuously
scans the
ACPI 6.2 defines a new ACPI notification value to NVDIMM Root Device
in Table 5-169.
0x81 Unconsumed Uncorrectable Memory Error Detected
Used to pro-actively notify OSPM of uncorrectable memory errors
detected (for example a memory scrubbing engine that continuously
scans the
> http://phrack.org/issues/52/6.html#article
>
> | A trusted path is one that is inside a root owned directory that
> | is not group or world writable. /bin, /usr/bin, /usr/local/bin, are
> | (under normal circumstances) considered trusted. Any non-root
> | users home directory is not trusted,
> http://phrack.org/issues/52/6.html#article
>
> | A trusted path is one that is inside a root owned directory that
> | is not group or world writable. /bin, /usr/bin, /usr/local/bin, are
> | (under normal circumstances) considered trusted. Any non-root
> | users home directory is not trusted,
On Thu, Jun 8, 2017 at 9:17 AM, Miroslav Lichvar wrote:
> On Fri, May 19, 2017 at 05:35:38PM -0700, John Stultz wrote:
>> >> On Wed, May 17, 2017 at 10:22 AM, Miroslav Lichvar
>> >> wrote:
>> >> > Is there a better way to run the timekeeping code in an
On Thu, Jun 8, 2017 at 9:17 AM, Miroslav Lichvar wrote:
> On Fri, May 19, 2017 at 05:35:38PM -0700, John Stultz wrote:
>> >> On Wed, May 17, 2017 at 10:22 AM, Miroslav Lichvar
>> >> wrote:
>> >> > Is there a better way to run the timekeeping code in an userspace
>> >> > application? I suspect
On Thu, Jun 08, 2017 at 06:56:14PM +0200, Felix Schnizlein wrote:
> A few entries have been omitted, due to already existing information in
> sysfs:
>
> - microcode -> /sys/devices/system/cpu/cpu*/microcode/version
> - cache -> /sys/devices/system/cpu/cpu*/cache/index*/size
> - core_id ->
On Thu, Jun 08, 2017 at 06:56:14PM +0200, Felix Schnizlein wrote:
> A few entries have been omitted, due to already existing information in
> sysfs:
>
> - microcode -> /sys/devices/system/cpu/cpu*/microcode/version
> - cache -> /sys/devices/system/cpu/cpu*/cache/index*/size
> - core_id ->
On Thu, Jun 08, 2017 at 06:56:13PM +0200, Felix Schnizlein wrote:
> Create a new sysfs attribute group called 'cpuinfo' for each
> online cpu. The cleaned up cpuinfo shows up in a sysfs
> subdirectory here: /sys/devices/system/cpu/cpu*/cpuinfo.
>
> Define preprocessor macros (CPUINFO_DEFINE_* and
On Thu, Jun 08, 2017 at 06:56:13PM +0200, Felix Schnizlein wrote:
> Create a new sysfs attribute group called 'cpuinfo' for each
> online cpu. The cleaned up cpuinfo shows up in a sysfs
> subdirectory here: /sys/devices/system/cpu/cpu*/cpuinfo.
>
> Define preprocessor macros (CPUINFO_DEFINE_* and
On Thu, 2017-06-08 at 11:37 -0600, Toshi Kani wrote:
> On Thu, 2017-06-08 at 10:34 -0700, Dan Williams wrote:
> > On Thu, Jun 8, 2017 at 10:30 AM, Linda Knippers > .c
> > om> wrote:
> > [..]
> > > Wasn't Dan concerned about how the OS can know whether the FW
> > > supports
On Thu, 2017-06-08 at 11:37 -0600, Toshi Kani wrote:
> On Thu, 2017-06-08 at 10:34 -0700, Dan Williams wrote:
> > On Thu, Jun 8, 2017 at 10:30 AM, Linda Knippers > .c
> > om> wrote:
> > [..]
> > > Wasn't Dan concerned about how the OS can know whether the FW
> > > supports that bit in the Start
On Thu, Jun 08, 2017 at 06:56:15PM +0200, Felix Schnizlein wrote:
> Enable deprecation warning if the kernel was compiled with sysfs cpuinfo.
>
> Signed-off-by: Thomas Renninger
> ---
> fs/proc/cpuinfo.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git
On Thu, Jun 08, 2017 at 06:56:15PM +0200, Felix Schnizlein wrote:
> Enable deprecation warning if the kernel was compiled with sysfs cpuinfo.
>
> Signed-off-by: Thomas Renninger
> ---
> fs/proc/cpuinfo.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/fs/proc/cpuinfo.c
On Thu, Jun 08, 2017 at 06:56:14PM +0200, Felix Schnizlein wrote:
> A few entries have been omitted, due to already existing information in
> sysfs:
>
> - microcode -> /sys/devices/system/cpu/cpu*/microcode/version
> - cache -> /sys/devices/system/cpu/cpu*/cache/index*/size
> - core_id ->
On Thu, Jun 08, 2017 at 06:56:14PM +0200, Felix Schnizlein wrote:
> A few entries have been omitted, due to already existing information in
> sysfs:
>
> - microcode -> /sys/devices/system/cpu/cpu*/microcode/version
> - cache -> /sys/devices/system/cpu/cpu*/cache/index*/size
> - core_id ->
On Thu, Jun 08, 2017 at 06:56:13PM +0200, Felix Schnizlein wrote:
> Create a new sysfs attribute group called 'cpuinfo' for each
> online cpu. The cleaned up cpuinfo shows up in a sysfs
> subdirectory here: /sys/devices/system/cpu/cpu*/cpuinfo.
>
> Define preprocessor macros (CPUINFO_DEFINE_* and
On Thu, Jun 08, 2017 at 06:56:13PM +0200, Felix Schnizlein wrote:
> Create a new sysfs attribute group called 'cpuinfo' for each
> online cpu. The cleaned up cpuinfo shows up in a sysfs
> subdirectory here: /sys/devices/system/cpu/cpu*/cpuinfo.
>
> Define preprocessor macros (CPUINFO_DEFINE_* and
On 3 June 2017 at 08:42, Leo Yan wrote:
> ### Introduction ###
Good day Leo,
>
> Embedded Trace Buffer (ETB) provides on-chip storage of trace data,
> usually has buffer size from 2KB to 8KB. These data has been used for
> profiling and this has been well implemented in
On 3 June 2017 at 08:42, Leo Yan wrote:
> ### Introduction ###
Good day Leo,
>
> Embedded Trace Buffer (ETB) provides on-chip storage of trace data,
> usually has buffer size from 2KB to 8KB. These data has been used for
> profiling and this has been well implemented in coresight driver.
>
>
> > > + outb(0x80, 0xCC);
> > > +
> > > + /* Make sure the above write is completed */
> > > + wmb();
> >
> > Why the wmb(). It doesn't do what the comment says! Also this code is x86
> > specific
> >
> >
>
> Memory barrier to enforce the order so that the outb() is completed, which
>
> > > + outb(0x80, 0xCC);
> > > +
> > > + /* Make sure the above write is completed */
> > > + wmb();
> >
> > Why the wmb(). It doesn't do what the comment says! Also this code is x86
> > specific
> >
> >
>
> Memory barrier to enforce the order so that the outb() is completed, which
>
On Thu, Jun 8, 2017 at 5:50 PM, joeyli wrote:
> On Tue, Jun 06, 2017 at 01:07:22PM -0700, João Paulo Rechi Vita wrote:
>> Signed-off-by: João Paulo Rechi Vita
>
> Please feel free to add:
> Reviewed-by: "Lee, Chun-Yi"
On Thu, Jun 8, 2017 at 5:50 PM, joeyli wrote:
> On Tue, Jun 06, 2017 at 01:07:22PM -0700, João Paulo Rechi Vita wrote:
>> Signed-off-by: João Paulo Rechi Vita
>
> Please feel free to add:
> Reviewed-by: "Lee, Chun-Yi"
Patchwork by some reason doesn't recognize this tag (presumably it
When adding or removing memory, the aa_index (affinity value) for the
memblock must also be converted to match the endianness of the rest
of the 'ibm,dynamic-memory' property. Otherwise, subsequent retrieval
of the attribute will likely lead to non-existent nodes, followed by
using the default
When adding or removing memory, the aa_index (affinity value) for the
memblock must also be converted to match the endianness of the rest
of the 'ibm,dynamic-memory' property. Otherwise, subsequent retrieval
of the attribute will likely lead to non-existent nodes, followed by
using the default
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