[PATCH v5 09/23] scsi: hisi_sas: add skeleton v3 hw driver

Add skeleton driver for v3 hw in hisi_sas_v3_hw.c File hisi_sas_v3_hw.c will serve 2 purposes: - probing and initialisation of the controller based on pci device - hw layer for v3-based controllers The controller design is quite similar to v2 hw in hip07. However key differences include: -All

[PATCH v5 04/23] scsi: hisi_sas: relocate get_ata_protocol()

From: Xiang Chen Relocate get_ata_protocol() to a common location, as future hw versions will require it. Also rename with "hisi_sas_" prefix for consistency. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 7

[PATCH v5 23/23] scsi: hisi_sas: modify internal abort dev flow for v3 hw

From: Xiang Chen There is a change for abort dev for v3 hw: add registers to configure unaborted iptt for a device, and then inform this to logic. Signed-off-by: Xiang Chen Signed-off-by: John Garry ---

[PATCH v5 23/23] scsi: hisi_sas: modify internal abort dev flow for v3 hw

From: Xiang Chen There is a change for abort dev for v3 hw: add registers to configure unaborted iptt for a device, and then inform this to logic. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 2 ++ drivers/scsi/hisi_sas/hisi_sas_main.c |

Re: [PATCH 3/3] Documentation: dt-bindings: Document deprecation of "vmmc_aux" and using "vqmmc"

On Wed, Jun 07, 2017 at 02:06:12PM +0530, Kishon Vijay Abraham I wrote: > Document deprecation of "vmmc_aux" for io regulator and use of generic > mmc binding "vqmmc" in omap-hsmmc. > > Signed-off-by: Kishon Vijay Abraham I > --- >

Re: [PATCH 3/3] Documentation: dt-bindings: Document deprecation of "vmmc_aux" and using "vqmmc"

On Wed, Jun 07, 2017 at 02:06:12PM +0530, Kishon Vijay Abraham I wrote: > Document deprecation of "vmmc_aux" for io regulator and use of generic > mmc binding "vqmmc" in omap-hsmmc. > > Signed-off-by: Kishon Vijay Abraham I > --- > Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt | 2 +-

[PATCH v5 20/23] scsi: hisi_sas: add get_wideport_bitmap_v3_hw()

From: Xiang Chen Add code for interface get_wideport_bitmap. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 13 + 1 file changed, 13 insertions(+) diff

[PATCH v5 20/23] scsi: hisi_sas: add get_wideport_bitmap_v3_hw()

From: Xiang Chen Add code for interface get_wideport_bitmap. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

Re: [PATCH tip/core/rcu 0/88] Commits for 4.13

On Thu, 25 May 2017 14:59:34 -0700 "Paul E. McKenney" wrote: > Hello! > > This rather long series mostly removes unused features, shrinks the > include/linux/rcupdate.h file's .i intermediate-output size, updates > rcutorture testing, and supplies miscellaneous

Re: [PATCH tip/core/rcu 0/88] Commits for 4.13

On Thu, 25 May 2017 14:59:34 -0700 "Paul E. McKenney" wrote: > Hello! > > This rather long series mostly removes unused features, shrinks the > include/linux/rcupdate.h file's .i intermediate-output size, updates > rcutorture testing, and supplies miscellaneous fixes. Branching proved >

[PATCH v5 19/23] scsi: hisi_sas: add v3 code to send internal abort command

From: Xiang Chen Add code to prepare internal abort command. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 38 ++ 1 file changed, 38

[PATCH v5 19/23] scsi: hisi_sas: add v3 code to send internal abort command

From: Xiang Chen Add code to prepare internal abort command. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 38 ++ 1 file changed, 38 insertions(+) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

Re: [PATCH 1/2] dt-bindings: ahci-fsl-qoriq: add ls1088a chip name to the list

On Wed, Jun 07, 2017 at 02:32:47PM +0800, Yuantian Tang wrote: > Signed-off-by: Tang Yuantian > --- > Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Rob Herring

Re: [PATCH 1/2] dt-bindings: ahci-fsl-qoriq: add ls1088a chip name to the list

On Wed, Jun 07, 2017 at 02:32:47PM +0800, Yuantian Tang wrote: > Signed-off-by: Tang Yuantian > --- > Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Rob Herring

[PATCH v5 16/23] scsi: hisi_sas: add v3 code to send SMP frame

From: Xiang Chen Add code to prepare SMP frame. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 74 ++ 1 file changed, 74

[PATCH v5 16/23] scsi: hisi_sas: add v3 code to send SMP frame

From: Xiang Chen Add code to prepare SMP frame. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 74 ++ 1 file changed, 74 insertions(+) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

On 09/06/17 14:41, YT Shen wrote: > On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote: >> On 31/05/17 12:39, YT Shen wrote: >>> This adds basic chip support for Mediatek 2712 >>> >>> Signed-off-by: YT Shen >>> --- >>> arch/arm64/boot/dts/mediatek/Makefile | 1 +

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

On 09/06/17 14:41, YT Shen wrote: > On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote: >> On 31/05/17 12:39, YT Shen wrote: >>> This adds basic chip support for Mediatek 2712 >>> >>> Signed-off-by: YT Shen >>> --- >>> arch/arm64/boot/dts/mediatek/Makefile | 1 + >>>

[PATCH v5 15/23] scsi: hisi_sas: add v3 code to send SSP frame

From: Xiang Chen Add code to prepare SSP frame and deliver it to hardware. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 208 + 1

[PATCH v5 15/23] scsi: hisi_sas: add v3 code to send SSP frame

From: Xiang Chen Add code to prepare SSP frame and deliver it to hardware. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 208 + 1 file changed, 208 insertions(+) diff --git

[PATCH v5 11/23] scsi: hisi_sas: add v3 hw init

From: Xiang Chen Add code to initialise v3 hardware. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 277 + 1 file changed, 277

[PATCH v5 14/23] scsi: hisi_sas: add v3 cq interrupt handler

From: Xiang Chen Add v3 cq interrupt handler slot_complete_v3_hw(). Note: The slot error handling needs to be further refined in the future to examine all fields in the error record, and handle appropriately, instead of current solution - just report

[PATCH v5 11/23] scsi: hisi_sas: add v3 hw init

From: Xiang Chen Add code to initialise v3 hardware. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 277 + 1 file changed, 277 insertions(+) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

[PATCH v5 14/23] scsi: hisi_sas: add v3 cq interrupt handler

From: Xiang Chen Add v3 cq interrupt handler slot_complete_v3_hw(). Note: The slot error handling needs to be further refined in the future to examine all fields in the error record, and handle appropriately, instead of current solution - just report SAS_OPEN_REJECT.

[PATCH v5 18/23] scsi: hisi_sas: add v3 code for itct setup and free

From: Xiang Chen Add code to itct setup and free for v3 hw. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 114 + 1 file changed, 114

[PATCH v5 18/23] scsi: hisi_sas: add v3 code for itct setup and free

From: Xiang Chen Add code to itct setup and free for v3 hw. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 114 + 1 file changed, 114 insertions(+) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

Re: [PATCH] mfd: Add driver for RAVE Supervisory Processor

On Tue, Jun 06, 2017 at 11:06:43AM -0700, Andrey Smirnov wrote: > Add a driver for RAVE Supervisory Processor, an MCU implementing > varoius bits of housekeeping functionality (watchdoging, backlight > control, LED control, etc) on RAVE family of products by Zodiac > Inflight Innovations. > >

[PATCH v5 00/23] hisi_sas: hip08 support

This patchset adds support for the HiSilicon SAS controller in the hip08 chipset. The key difference compared to earlier chipsets is that the controller is an integrated PCI endpoint in hip08. As such, the controller is a pci device (not a platform device, like v2 hw in hip07). The driver is

Re: [PATCH] mfd: Add driver for RAVE Supervisory Processor

On Tue, Jun 06, 2017 at 11:06:43AM -0700, Andrey Smirnov wrote: > Add a driver for RAVE Supervisory Processor, an MCU implementing > varoius bits of housekeeping functionality (watchdoging, backlight > control, LED control, etc) on RAVE family of products by Zodiac > Inflight Innovations. > >

[PATCH v5 00/23] hisi_sas: hip08 support

This patchset adds support for the HiSilicon SAS controller in the hip08 chipset. The key difference compared to earlier chipsets is that the controller is an integrated PCI endpoint in hip08. As such, the controller is a pci device (not a platform device, like v2 hw in hip07). The driver is

[PATCH v5 10/23] scsi: hisi_sas: add initialisation for v3 pci-based controller

Add the code to initialise the controller which is based on pci device in hisi_sas_v3_hw.c The core controller routines are still in hisi_sas_main.c; some common initialisation functions are also exported from hisi_sas_main.c For pci-based controller, the device properties, like phy count and

[PATCH v5 22/23] scsi: hisi_sas: add v3 code to fill some more hw function pointers

From: Xiang Chen Add code to fill the interface of phy_hard_reset, phy_get_max_linkrate, and phy enable/disable. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 39

[PATCH v5 10/23] scsi: hisi_sas: add initialisation for v3 pci-based controller

Add the code to initialise the controller which is based on pci device in hisi_sas_v3_hw.c The core controller routines are still in hisi_sas_main.c; some common initialisation functions are also exported from hisi_sas_main.c For pci-based controller, the device properties, like phy count and

[PATCH v5 22/23] scsi: hisi_sas: add v3 code to fill some more hw function pointers

From: Xiang Chen Add code to fill the interface of phy_hard_reset, phy_get_max_linkrate, and phy enable/disable. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 39 ++ 1 file changed, 39 insertions(+) diff

[PATCH v5 03/23] scsi: hisi_sas: optimise the usage of hisi_hba.lock

From: Xiang Chen Currently hisi_hba.lock is locked to deliver and receive a command to/from any hw queue. This causes much contention at high data-rates. To boost performance, lock on a per queue basis for sending and receiving commands to/from hw. Certain critical

[PATCH v5 06/23] scsi: hisi_sas: relocate get_ncq_tag_v2_hw()

From: Xiang Chen Relocate get_ncq_tag_v2_hw() to a common location, as future hw versions will require it. Also rename with "hisi_sas_" prefix for consistency. Signed-off-by: Xiang Chen Signed-off-by: John Garry ---

[PATCH v5 03/23] scsi: hisi_sas: optimise the usage of hisi_hba.lock

From: Xiang Chen Currently hisi_hba.lock is locked to deliver and receive a command to/from any hw queue. This causes much contention at high data-rates. To boost performance, lock on a per queue basis for sending and receiving commands to/from hw. Certain critical regions still need to be

[PATCH v5 06/23] scsi: hisi_sas: relocate get_ncq_tag_v2_hw()

From: Xiang Chen Relocate get_ncq_tag_v2_hw() to a common location, as future hw versions will require it. Also rename with "hisi_sas_" prefix for consistency. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 1 +

Re: [PATCH 10/17] irqchip: New RISC-V PLIC Driver

On Wed, Jun 07, 2017 at 11:52:10AM +0100, Marc Zyngier wrote: > On 07/06/17 00:00, Palmer Dabbelt wrote: > > +static void plic_disable(struct plic_data *data, int i, int hwirq) > > +{ > > + struct plic_enable_context *enable = plic_enable_context(data, i); > > + > > + atomic_and(~(1 << (hwirq

Re: [PATCH 10/17] irqchip: New RISC-V PLIC Driver

On Wed, Jun 07, 2017 at 11:52:10AM +0100, Marc Zyngier wrote: > On 07/06/17 00:00, Palmer Dabbelt wrote: > > +static void plic_disable(struct plic_data *data, int i, int hwirq) > > +{ > > + struct plic_enable_context *enable = plic_enable_context(data, i); > > + > > + atomic_and(~(1 << (hwirq

Re: [PATCH] gpio: zynq: Clarify quirk and provide helper function

On Thu, Jun 8, 2017 at 7:32 PM, Soren Brinkmann wrote: > The one quirk used in the zynq GPIO driver was called FOO which is not > very descriptive. Rename the quirk to IS_ZYNQ as it indicates whether > the HW is a zynq or zynqmp device to allow handling of

Re: [PATCH] gpio: zynq: Clarify quirk and provide helper function

On Thu, Jun 8, 2017 at 7:32 PM, Soren Brinkmann wrote: > The one quirk used in the zynq GPIO driver was called FOO which is not > very descriptive. Rename the quirk to IS_ZYNQ as it indicates whether > the HW is a zynq or zynqmp device to allow handling of device-specific > differences of the

Re: linux-next: manual merge of the devicetree tree with the renesas tree

On Thu, Jun 8, 2017 at 10:53 PM, Stephen Rothwell wrote: > Hi Rob, > > Today's linux-next merge of the devicetree tree got a conflict in: > > Documentation/devicetree/bindings/vendor-prefixes.txt > > between commit: > > d795f15618b8 ("of: Add vendor prefix for iWave

Re: linux-next: manual merge of the devicetree tree with the renesas tree

On Thu, Jun 8, 2017 at 10:53 PM, Stephen Rothwell wrote: > Hi Rob, > > Today's linux-next merge of the devicetree tree got a conflict in: > > Documentation/devicetree/bindings/vendor-prefixes.txt > > between commit: > > d795f15618b8 ("of: Add vendor prefix for iWave Systems Technologies Pvt.

Re: [kernel-hardening] Re: [PATCH v2 1/1] Add Trusted Path Execution as a stackable LSM

On Fri, 2017-06-09 at 09:18 -0400, Matt Brown wrote: > On 6/9/17 9:16 AM, Mimi Zohar wrote: > > On Fri, 2017-06-09 at 05:55 -0700, Kees Cook wrote: > >> On Fri, Jun 9, 2017 at 3:18 AM, Mimi Zohar > >> wrote: > >>> On Thu, 2017-06-08 at 23:50 -0400, Matt Brown wrote: >

Re: [kernel-hardening] Re: [PATCH v2 1/1] Add Trusted Path Execution as a stackable LSM

On Fri, 2017-06-09 at 09:18 -0400, Matt Brown wrote: > On 6/9/17 9:16 AM, Mimi Zohar wrote: > > On Fri, 2017-06-09 at 05:55 -0700, Kees Cook wrote: > >> On Fri, Jun 9, 2017 at 3:18 AM, Mimi Zohar > >> wrote: > >>> On Thu, 2017-06-08 at 23:50 -0400, Matt Brown wrote: > >> > >> * Issues:

Re: [PATCH v3 1/2] DT: pinctrl: Add binding documentation for Spreadtrum pin controller

On Tue, Jun 06, 2017 at 09:03:13PM +0800, Baolin Wang wrote: > This patch adds the binding documentation for Spreadtrum SC9860 pin > controller device. For the subject: "dt-bindings: pinctrl: Add Spreadtrum SC9860 pin controller" > > Signed-off-by: Baolin Wang >

RE: [PATCH net-next] qed: add qed_int_sb_init() stub function

> When CONFIG_QED_SRIOV is disabled, we get a build error: > > drivers/net/ethernet/qlogic/qed/qed_int.c: In function 'qed_int_sb_init': > drivers/net/ethernet/qlogic/qed/qed_int.c:1499:4: error: implicit declaration > of function 'qed_vf_set_sb_info'; did you mean 'qed_mcp_get_resc_info'? [- >

Re: [PATCH v3 1/2] DT: pinctrl: Add binding documentation for Spreadtrum pin controller

On Tue, Jun 06, 2017 at 09:03:13PM +0800, Baolin Wang wrote: > This patch adds the binding documentation for Spreadtrum SC9860 pin > controller device. For the subject: "dt-bindings: pinctrl: Add Spreadtrum SC9860 pin controller" > > Signed-off-by: Baolin Wang > --- > Changes since v2: > -

RE: [PATCH net-next] qed: add qed_int_sb_init() stub function

> When CONFIG_QED_SRIOV is disabled, we get a build error: > > drivers/net/ethernet/qlogic/qed/qed_int.c: In function 'qed_int_sb_init': > drivers/net/ethernet/qlogic/qed/qed_int.c:1499:4: error: implicit declaration > of function 'qed_vf_set_sb_info'; did you mean 'qed_mcp_get_resc_info'? [- >

Re: [PATCH] arm: aspeed: Add clock-names property to timer node

On Tue, Jun 6, 2017 at 11:41 AM, Arnd Bergmann wrote: > On Mon, Jun 5, 2017 at 10:59 AM, Joel Stanley wrote: >> On Mon, Jun 5, 2017 at 5:18 PM, Andrew Jeffery wrote: >>> The merging of a number of clocksource drivers into fttmr010 means we >>>

Re: [PATCH] arm: aspeed: Add clock-names property to timer node

On Tue, Jun 6, 2017 at 11:41 AM, Arnd Bergmann wrote: > On Mon, Jun 5, 2017 at 10:59 AM, Joel Stanley wrote: >> On Mon, Jun 5, 2017 at 5:18 PM, Andrew Jeffery wrote: >>> The merging of a number of clocksource drivers into fttmr010 means we >>> require clock-names to be specified in the Aspeed

Re: [PATCH 03/10] fpga: allow to compile-test Altera FPGA bridge drivers

On 2017-06-09 at 11:49:02 +0200, Greg Kroah-Hartman wrote: > On Mon, Jun 05, 2017 at 02:07:34PM -0500, Alan Tull wrote: > > From: Tobias Klauser > > > > Add COMPILE_TEST to the Kconfig entry for the Altera SoCFPGA FPGA > > Bridge. The Altera

Re: [PATCH 03/10] fpga: allow to compile-test Altera FPGA bridge drivers

On 2017-06-09 at 11:49:02 +0200, Greg Kroah-Hartman wrote: > On Mon, Jun 05, 2017 at 02:07:34PM -0500, Alan Tull wrote: > > From: Tobias Klauser > > > > Add COMPILE_TEST to the Kconfig entry for the Altera SoCFPGA FPGA > > Bridge. The Altera FPGA Freeze Bridge can also be used on Altera PEIe >

Re: [PATCH v1 24/25] kdb: Switch to use %pt

On 08/06/17 14:48, Andy Shevchenko wrote: Use %pt instead of open coded variant to print content of struct rtc_time in human readable format. Cc: Jason Wessel Cc: Ingo Molnar Signed-off-by: Andy Shevchenko

Re: [PATCH v1 24/25] kdb: Switch to use %pt

On 08/06/17 14:48, Andy Shevchenko wrote: Use %pt instead of open coded variant to print content of struct rtc_time in human readable format. Cc: Jason Wessel Cc: Ingo Molnar Signed-off-by: Andy Shevchenko Reviewed-by: Daniel Thompson --- kernel/debug/kdb/kdb_main.c | 7 +-- 1

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote: > On 31/05/17 12:39, YT Shen wrote: > > This adds basic chip support for Mediatek 2712 > > > > Signed-off-by: YT Shen > > --- > > arch/arm64/boot/dts/mediatek/Makefile | 1 + > >

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote: > On 31/05/17 12:39, YT Shen wrote: > > This adds basic chip support for Mediatek 2712 > > > > Signed-off-by: YT Shen > > --- > > arch/arm64/boot/dts/mediatek/Makefile | 1 + > > arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 39

Re: [linux-sunxi] [PATCH] arm64: allwinner: sun50i-a64: Remove duplicate ethernet@1c30000

Hi, On 09/06/17 13:40, Jagan Teki wrote: > From: Jagan Teki > > Remove duplicate ethernet@1c3 from allwinner/sun50i-a64.dtsi I think this is an artefact of the sun8i-dwmac merging, where both David and Maxime merged the DT patches in their trees (compare

Re: [linux-sunxi] [PATCH] arm64: allwinner: sun50i-a64: Remove duplicate ethernet@1c30000

Hi, On 09/06/17 13:40, Jagan Teki wrote: > From: Jagan Teki > > Remove duplicate ethernet@1c3 from allwinner/sun50i-a64.dtsi I think this is an artefact of the sun8i-dwmac merging, where both David and Maxime merged the DT patches in their trees (compare e53f67e9 and 103aefa0). I think

Re: [PATCH v2 1/3] dt-bindings: arm: amlogic: Add SoC information bindings

On Tue, Jun 06, 2017 at 11:45:38AM +0200, Neil Armstrong wrote: > Add bindings for the SoC information register of the Amlogic SoCs. > > Signed-off-by: Neil Armstrong > --- > Documentation/devicetree/bindings/arm/amlogic.txt | 32 > +++ > 1 file

Re: [PATCH v2 1/3] dt-bindings: arm: amlogic: Add SoC information bindings

On Tue, Jun 06, 2017 at 11:45:38AM +0200, Neil Armstrong wrote: > Add bindings for the SoC information register of the Amlogic SoCs. > > Signed-off-by: Neil Armstrong > --- > Documentation/devicetree/bindings/arm/amlogic.txt | 32 > +++ > 1 file changed, 32 insertions(+) >

Re: [PATCH v3 4/6] regulator: pfuze100: add fsl,pmic-stby-poweroff property

On Tue, Jun 06, 2017 at 09:31:44AM +0200, Oleksij Rempel wrote: > Document the new optional "fsl,pmic_stby_poweroff" property. Needs updating... > > Signed-off-by: Oleksij Rempel > --- > Documentation/devicetree/bindings/regulator/pfuze100.txt | 7 +++ > 1 file

Re: [PATCH v3 4/6] regulator: pfuze100: add fsl,pmic-stby-poweroff property

On Tue, Jun 06, 2017 at 09:31:44AM +0200, Oleksij Rempel wrote: > Document the new optional "fsl,pmic_stby_poweroff" property. Needs updating... > > Signed-off-by: Oleksij Rempel > --- > Documentation/devicetree/bindings/regulator/pfuze100.txt | 7 +++ > 1 file changed, 7 insertions(+) >

[PATCH v8 05/10] hyper-v: use fast hypercall for HVCALL_SIGNAL_EVENT

We need to pass only 8 bytes of input for HvSignalEvent which makes it a perfect fit for fast hypercall. hv_input_signal_event_buffer is not needed any more and hv_input_signal_event is converted to union for convenience. Signed-off-by: Vitaly Kuznetsov Reviewed-by: Andy

[PATCH v8 05/10] hyper-v: use fast hypercall for HVCALL_SIGNAL_EVENT

We need to pass only 8 bytes of input for HvSignalEvent which makes it a perfect fit for fast hypercall. hv_input_signal_event_buffer is not needed any more and hv_input_signal_event is converted to union for convenience. Signed-off-by: Vitaly Kuznetsov Reviewed-by: Andy Shevchenko ---

Re: [PATCH v3 1/6] ARM: imx6q: provide documentation for new fsl,pmic-stby-poweroff property

On Tue, Jun 06, 2017 at 09:31:41AM +0200, Oleksij Rempel wrote: > Signed-off-by: Oleksij Rempel > --- > Documentation/devicetree/bindings/clock/imx6q-clock.txt | 8 > 1 file changed, 8 insertions(+) Acked-by: Rob Herring

[PATCH v8 07/10] hyper-v: globalize vp_index

To support implementing remote TLB flushing on Hyper-V with a hypercall we need to make vp_index available outside of vmbus module. Rename and globalize. Signed-off-by: Vitaly Kuznetsov Reviewed-by: Andy Shevchenko --- arch/x86/hyperv/hv_init.c

Re: [PATCH v3 1/6] ARM: imx6q: provide documentation for new fsl,pmic-stby-poweroff property

On Tue, Jun 06, 2017 at 09:31:41AM +0200, Oleksij Rempel wrote: > Signed-off-by: Oleksij Rempel > --- > Documentation/devicetree/bindings/clock/imx6q-clock.txt | 8 > 1 file changed, 8 insertions(+) Acked-by: Rob Herring

[PATCH v8 07/10] hyper-v: globalize vp_index

To support implementing remote TLB flushing on Hyper-V with a hypercall we need to make vp_index available outside of vmbus module. Rename and globalize. Signed-off-by: Vitaly Kuznetsov Reviewed-by: Andy Shevchenko --- arch/x86/hyperv/hv_init.c | 34 +-

[PATCH v8 08/10] x86/hyper-v: use hypercall for remote TLB flush

Hyper-V host can suggest us to use hypercall for doing remote TLB flush, this is supposed to work faster than IPIs. Implementation details: to do HvFlushVirtualAddress{Space,List} hypercalls we need to put the input somewhere in memory and we don't really want to have memory allocation on each

[PATCH v8 08/10] x86/hyper-v: use hypercall for remote TLB flush

Hyper-V host can suggest us to use hypercall for doing remote TLB flush, this is supposed to work faster than IPIs. Implementation details: to do HvFlushVirtualAddress{Space,List} hypercalls we need to put the input somewhere in memory and we don't really want to have memory allocation on each

Re: [RFC PATCH 2/3] Implement sysfs based cpuinfo for x86 cpus.

On Thursday, June 08, 2017 08:24:01 PM Greg KH wrote: > On Thu, Jun 08, 2017 at 06:56:14PM +0200, Felix Schnizlein wrote: > > --- > > arch/x86/kernel/Makefile| 1 + > > arch/x86/kernel/cpuinfo_sysfs.c | 166 > > drivers/base/cpuinfo.c |

[PATCH v8 10/10] tracing/hyper-v: trace hyperv_mmu_flush_tlb_others()

Add Hyper-V tracing subsystem and trace hyperv_mmu_flush_tlb_others(). Tracing is done the same way we do xen_mmu_flush_tlb_others(). Signed-off-by: Vitaly Kuznetsov --- MAINTAINERS | 1 + arch/x86/hyperv/mmu.c | 7 +++

Re: [RFC PATCH 2/3] Implement sysfs based cpuinfo for x86 cpus.

On Thursday, June 08, 2017 08:24:01 PM Greg KH wrote: > On Thu, Jun 08, 2017 at 06:56:14PM +0200, Felix Schnizlein wrote: > > --- > > arch/x86/kernel/Makefile| 1 + > > arch/x86/kernel/cpuinfo_sysfs.c | 166 > > drivers/base/cpuinfo.c |

[PATCH v8 10/10] tracing/hyper-v: trace hyperv_mmu_flush_tlb_others()

Add Hyper-V tracing subsystem and trace hyperv_mmu_flush_tlb_others(). Tracing is done the same way we do xen_mmu_flush_tlb_others(). Signed-off-by: Vitaly Kuznetsov --- MAINTAINERS | 1 + arch/x86/hyperv/mmu.c | 7 +++

[PATCH v8 09/10] x86/hyper-v: support extended CPU ranges for TLB flush hypercalls

Hyper-V hosts may support more than 64 vCPUs, we need to use HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX/LIST_EX hypercalls in this case. Signed-off-by: Vitaly Kuznetsov --- Changes since v7: - Drop explicit casting from virt_to_phys() [Andy Shevchenko] - Re-format max_gvas

[PATCH v8 09/10] x86/hyper-v: support extended CPU ranges for TLB flush hypercalls

Hyper-V hosts may support more than 64 vCPUs, we need to use HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX/LIST_EX hypercalls in this case. Signed-off-by: Vitaly Kuznetsov --- Changes since v7: - Drop explicit casting from virt_to_phys() [Andy Shevchenko] - Re-format max_gvas calculus [Andy Shevchenko]

[PATCH v8 04/10] x86/hyper-v: fast hypercall implementation

Hyper-V supports 'fast' hypercalls when all parameters are passed through registers. Implement an inline version of a simpliest of these calls: hypercall with one 8-byte input and no output. Signed-off-by: Vitaly Kuznetsov Reviewed-by: Andy Shevchenko

[PATCH v8 06/10] x86/hyper-v: implement rep hypercalls

Rep hypercalls are normal hypercalls which perform multiple actions at once. Hyper-V guarantees to return exectution to the caller in not more than 50us and the caller needs to use hypercall continuation. Touch NMI watchdog between hypercall invocations. This is going to be used for

[PATCH v8 06/10] x86/hyper-v: implement rep hypercalls

Rep hypercalls are normal hypercalls which perform multiple actions at once. Hyper-V guarantees to return exectution to the caller in not more than 50us and the caller needs to use hypercall continuation. Touch NMI watchdog between hypercall invocations. This is going to be used for

[PATCH v8 04/10] x86/hyper-v: fast hypercall implementation

Hyper-V supports 'fast' hypercalls when all parameters are passed through registers. Implement an inline version of a simpliest of these calls: hypercall with one 8-byte input and no output. Signed-off-by: Vitaly Kuznetsov Reviewed-by: Andy Shevchenko --- arch/x86/include/asm/mshyperv.h | 34

[PATCH v8 03/10] x86/hyper-v: make hv_do_hypercall() inline

We have only three call sites for hv_do_hypercall() and we're going to change HVCALL_SIGNAL_EVENT to doing fast hypercall so we can inline this function for optimization. Hyper-V top level functional specification states that r9-r11 registers and flags may be clobbered by the hypervisor during

[PATCH v8 03/10] x86/hyper-v: make hv_do_hypercall() inline

We have only three call sites for hv_do_hypercall() and we're going to change HVCALL_SIGNAL_EVENT to doing fast hypercall so we can inline this function for optimization. Hyper-V top level functional specification states that r9-r11 registers and flags may be clobbered by the hypervisor during

[PATCH v8 02/10] x86/hyper-v: stash the max number of virtual/logical processor

Max virtual processor will be needed for 'extended' hypercalls supporting more than 64 vCPUs. While on it, unify on 'Hyper-V' in mshyperv.c as we currently have a mix, report acquired misc features as well. Signed-off-by: Vitaly Kuznetsov Reviewed-by: Andy Shevchenko

[PATCH v8 02/10] x86/hyper-v: stash the max number of virtual/logical processor

Max virtual processor will be needed for 'extended' hypercalls supporting more than 64 vCPUs. While on it, unify on 'Hyper-V' in mshyperv.c as we currently have a mix, report acquired misc features as well. Signed-off-by: Vitaly Kuznetsov Reviewed-by: Andy Shevchenko ---

[PATCH v8 01/10] x86/hyper-v: include hyperv/ only when CONFIG_HYPERV is set

Code is arch/x86/hyperv/ is only needed when CONFIG_HYPERV is set, the 'basic' support and detection lives in arch/x86/kernel/cpu/mshyperv.c which is included when CONFIG_HYPERVISOR_GUEST is set. Signed-off-by: Vitaly Kuznetsov Reviewed-by: Andy Shevchenko

[PATCH v8 01/10] x86/hyper-v: include hyperv/ only when CONFIG_HYPERV is set

Code is arch/x86/hyperv/ is only needed when CONFIG_HYPERV is set, the 'basic' support and detection lives in arch/x86/kernel/cpu/mshyperv.c which is included when CONFIG_HYPERVISOR_GUEST is set. Signed-off-by: Vitaly Kuznetsov Reviewed-by: Andy Shevchenko --- arch/x86/Kbuild |

[PATCH v8 00/10] Hyper-V: paravirtualized remote TLB flushing and hypercall improvements

Changes since v7: - Minor code style fixes (drop explicit casting, reformat code a bit) in PATCH3 and PATCH9 [Andy Shevchenko] Original description: Hyper-V supports hypercalls for doing local and remote TLB flushing and gives its guests hints when using hypercall is preferred. While doing

[PATCH v8 00/10] Hyper-V: paravirtualized remote TLB flushing and hypercall improvements

Changes since v7: - Minor code style fixes (drop explicit casting, reformat code a bit) in PATCH3 and PATCH9 [Andy Shevchenko] Original description: Hyper-V supports hypercalls for doing local and remote TLB flushing and gives its guests hints when using hypercall is preferred. While doing

Re: [PATCH v8 8/9] drivers: perf: hisi: Miscellanous node(MN) event counting in perf

On Mon, May 22, 2017 at 08:48:37PM +0800, Shaokun Zhang wrote: > 1. Add support to count MN hardware events. > 2. Mn events are listed in sysfs at /sys/devices/hisi_mn_2/events/ >The events can be selected as shown in perf list >e.g.: For MN_READ_REQUEST event for Super CPU cluster 2 the >

Re: [PATCH v8 8/9] drivers: perf: hisi: Miscellanous node(MN) event counting in perf

On Mon, May 22, 2017 at 08:48:37PM +0800, Shaokun Zhang wrote: > 1. Add support to count MN hardware events. > 2. Mn events are listed in sysfs at /sys/devices/hisi_mn_2/events/ >The events can be selected as shown in perf list >e.g.: For MN_READ_REQUEST event for Super CPU cluster 2 the >

Re: [RFC PATCH net-next 2/5] bpf/verifier: rework value tracking

On 06/08/2017 06:45 PM, Alexei Starovoitov wrote: [...] I think Daniel will be happy to test your next rev of the patches. I'll test them as well. At least 'insn_processed' from C code in tools/testing/selftests/bpf/ is a good estimate of how these changes affect pruning. Without having looked

Re: [RFC PATCH net-next 2/5] bpf/verifier: rework value tracking

On 06/08/2017 06:45 PM, Alexei Starovoitov wrote: [...] I think Daniel will be happy to test your next rev of the patches. I'll test them as well. At least 'insn_processed' from C code in tools/testing/selftests/bpf/ is a good estimate of how these changes affect pruning. Without having looked

Re: [PATCH 0/3] cpufreq: schedutil: Fix 4.12 regressions

On Fri, Jun 9, 2017 at 2:32 PM, Viresh Kumar wrote: > On 9 June 2017 at 17:54, Rafael J. Wysocki wrote: >> Hi, >> >> On Fri, Jun 9, 2017 at 12:15 PM, Viresh Kumar >> wrote: >>> Hi Rafael, >>> >>> I have identified some

Re: [PATCH 05/10] dt-bindings: interrupt-controller: sunxi-nmi: Add compatible for A31 R_INTC

On Tue, Jun 06, 2017 at 01:59:27PM +0800, Chen-Yu Tsai wrote: > The A31 and later have an R_INTC block which handles the NMI interrupt > pin on the SoC. This interrupt pin is used by the external PMIC to > signal interrupts to the SoC. > > While this hardware block is undocumented, the interrupt

Re: [PATCH 0/3] cpufreq: schedutil: Fix 4.12 regressions

On Fri, Jun 9, 2017 at 2:32 PM, Viresh Kumar wrote: > On 9 June 2017 at 17:54, Rafael J. Wysocki wrote: >> Hi, >> >> On Fri, Jun 9, 2017 at 12:15 PM, Viresh Kumar >> wrote: >>> Hi Rafael, >>> >>> I have identified some regressions with the schedutil governor which >>> happen due to one of your

Re: [PATCH 05/10] dt-bindings: interrupt-controller: sunxi-nmi: Add compatible for A31 R_INTC

On Tue, Jun 06, 2017 at 01:59:27PM +0800, Chen-Yu Tsai wrote: > The A31 and later have an R_INTC block which handles the NMI interrupt > pin on the SoC. This interrupt pin is used by the external PMIC to > signal interrupts to the SoC. > > While this hardware block is undocumented, the interrupt

Re: [PATCH v8 7/9] drivers: perf: hisi: Add support for Hisilicon SoC event counters

Hi, On Mon, May 22, 2017 at 08:48:35PM +0800, Shaokun Zhang wrote: > +/* > + * ARMv8 HiSilicon Hardware counter Index. > + */ > +enum hisi_l3c_pmu_counters { > + HISI_IDX_L3C_COUNTER0 = 0x0, > + HISI_IDX_L3C_COUNTER_MAX= 0x8, Just to check, there are 8 counters,

Re: [PATCH v8 7/9] drivers: perf: hisi: Add support for Hisilicon SoC event counters

Hi, On Mon, May 22, 2017 at 08:48:35PM +0800, Shaokun Zhang wrote: > +/* > + * ARMv8 HiSilicon Hardware counter Index. > + */ > +enum hisi_l3c_pmu_counters { > + HISI_IDX_L3C_COUNTER0 = 0x0, > + HISI_IDX_L3C_COUNTER_MAX= 0x8, Just to check, there are 8 counters,

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