From: Wanpeng Li
Last year guys from huawei reported that the call of
memory_global_dirty_log_start/stop()
takes 13s for 4T memory and cause guest freeze too long which increases the
unacceptable
migration downtime. [1] [2]
Guangrong pointed out:
| collapsible_sptes zaps 4k mappings to
From: Wanpeng Li
Last year guys from huawei reported that the call of
memory_global_dirty_log_start/stop()
takes 13s for 4T memory and cause guest freeze too long which increases the
unacceptable
migration downtime. [1] [2]
Guangrong pointed out:
| collapsible_sptes zaps 4k mappings to
On Thu, 6 Dec 2018 at 00:33, Du, Alek wrote:
>
> From a081e783383adf1179c71bc37b4e199d087af643 Mon Sep 17 00:00:00 2001
> From: Alek Du
> Date: Fri, 30 Nov 2018 14:02:28 +0800
> Subject: [PATCH] mmc: sdhci: fix the timeout check window for clock and reset
>
> We observed some premature timeouts
On Thu, 6 Dec 2018 at 00:33, Du, Alek wrote:
>
> From a081e783383adf1179c71bc37b4e199d087af643 Mon Sep 17 00:00:00 2001
> From: Alek Du
> Date: Fri, 30 Nov 2018 14:02:28 +0800
> Subject: [PATCH] mmc: sdhci: fix the timeout check window for clock and reset
>
> We observed some premature timeouts
On Wed 2018-12-05 15:49:14, Joe Lawrence wrote:
> On 11/29/2018 04:44 AM, Petr Mladek wrote:
> > The atomic replace allows to create cumulative patches. They
> > are useful when you maintain many livepatches and want to remove
> > one that is lower on the stack. In addition it is very useful when
On Wed 2018-12-05 15:49:14, Joe Lawrence wrote:
> On 11/29/2018 04:44 AM, Petr Mladek wrote:
> > The atomic replace allows to create cumulative patches. They
> > are useful when you maintain many livepatches and want to remove
> > one that is lower on the stack. In addition it is very useful when
Hi Krzysztof,
On Wed, 5 Dec 2018 at 21:49, Krzysztof Kozlowski wrote:
>
> On Wed, 5 Dec 2018 at 17:11, Anand Moon wrote:
> >
> > Hi Krzysztof,
> >
> > Thanks for your review.
> > .
> > On Wed, 5 Dec 2018 at 19:36, Krzysztof Kozlowski wrote:
> > >
> > > On Tue, 4 Dec 2018 at 20:40, Anand Moon
Hi Krzysztof,
On Wed, 5 Dec 2018 at 21:49, Krzysztof Kozlowski wrote:
>
> On Wed, 5 Dec 2018 at 17:11, Anand Moon wrote:
> >
> > Hi Krzysztof,
> >
> > Thanks for your review.
> > .
> > On Wed, 5 Dec 2018 at 19:36, Krzysztof Kozlowski wrote:
> > >
> > > On Tue, 4 Dec 2018 at 20:40, Anand Moon
Dear Rider,
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For road / offroad motorcycles, visit our website on
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Dear Rider,
RED Racing Parts offers the new full line of carbon fiber parts for your
motorbike.
For road / offroad motorcycles, visit our website on
https://www.redracingparts.com/english/motorbikesmotorcycles/productsandcomponents/general/intro/carbonfibrefiber.php
For trial motorcycles,
On Thu, Dec 06, 2018 at 01:42:30AM +, Anson Huang wrote:
> From: Fabio Estevam
>
> It is not recommended to place regulators inside "simple-bus", so move
> them out to make it cleaner the addition of new regulators.
>
> Signed-off-by: Fabio Estevam
Applied all, thanks.
On Thu, Dec 06, 2018 at 01:42:30AM +, Anson Huang wrote:
> From: Fabio Estevam
>
> It is not recommended to place regulators inside "simple-bus", so move
> them out to make it cleaner the addition of new regulators.
>
> Signed-off-by: Fabio Estevam
Applied all, thanks.
Building a kernel with CONFIG_PCI_IMX6=y, but CONFIG_PCIEPORTBUS=n
produces a system where built-in PCIE bridge (16c3:abcd) isn't bound
to pcieport driver. This, in turn, results in a PCIE bus that is
capable of enumerating attached PCIE device, but lacks functional
interrupt support.
Building a kernel with CONFIG_PCI_IMX6=y, but CONFIG_PCIEPORTBUS=n
produces a system where built-in PCIE bridge (16c3:abcd) isn't bound
to pcieport driver. This, in turn, results in a PCIE bus that is
capable of enumerating attached PCIE device, but lacks functional
interrupt support.
Hi,
Thank you for your comments.
On 2018/12/05 8:03, Rob Herring wrote:
On Mon, Nov 19, 2018 at 10:01:09AM +0900, Sugaya Taichi wrote:
Add DT bindings document for Milbeaut M10V timer.
Signed-off-by: Sugaya Taichi
---
.../bindings/timer/socionext,milbeaut-timer.txt | 17
Hi,
Thank you for your comments.
On 2018/12/05 8:03, Rob Herring wrote:
On Mon, Nov 19, 2018 at 10:01:09AM +0900, Sugaya Taichi wrote:
Add DT bindings document for Milbeaut M10V timer.
Signed-off-by: Sugaya Taichi
---
.../bindings/timer/socionext,milbeaut-timer.txt | 17
On Wed, Dec 05, 2018 at 09:19:35AM -0200, Fabio Estevam wrote:
> On the vf610-zii-scu4-aib board there is a hi8435 (32-channel
> discrete-to-digital SPI sensor device) in the DSPI0 bus.
>
> Add support for it.
>
> Signed-off-by: Fabio Estevam
> Reviewed-by: Chris Healy
Applied, thanks.
On Wed, Dec 05, 2018 at 09:19:35AM -0200, Fabio Estevam wrote:
> On the vf610-zii-scu4-aib board there is a hi8435 (32-channel
> discrete-to-digital SPI sensor device) in the DSPI0 bus.
>
> Add support for it.
>
> Signed-off-by: Fabio Estevam
> Reviewed-by: Chris Healy
Applied, thanks.
On Wed, Dec 05, 2018 at 01:14:25AM +, Anson Huang wrote:
> Add egalax touch screen support on i2c2 bus, it is connected
> to LVDS0, while the existing one on i2c3 bus is connected to
> LVDS1.
>
> Signed-off-by: Anson Huang
Applied, thanks.
On Wed, Dec 05, 2018 at 01:14:25AM +, Anson Huang wrote:
> Add egalax touch screen support on i2c2 bus, it is connected
> to LVDS0, while the existing one on i2c3 bus is connected to
> LVDS1.
>
> Signed-off-by: Anson Huang
Applied, thanks.
PCIE PHY IP block on i.MX7D differs from the one used on i.MX6 family,
so none of the code in current implementation of imx6_setup_phy_mpll()
is applicable.
Cc: bhelg...@google.com
Cc: Fabio Estevam
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc:
Add code needed to support i.MX8MQ variant.
Cc: bhelg...@google.com
Cc: Fabio Estevam
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc:
PCIE PHY IP block on i.MX7D differs from the one used on i.MX6 family,
so none of the code in current implementation of imx6_pcie_reset_phy()
is applicable.
Cc: bhelg...@google.com
Cc: Fabio Estevam
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc:
PCIE PHY IP block on i.MX7D differs from the one used on i.MX6 family,
so none of the code in current implementation of imx6_setup_phy_mpll()
is applicable.
Cc: bhelg...@google.com
Cc: Fabio Estevam
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc:
Add code needed to support i.MX8MQ variant.
Cc: bhelg...@google.com
Cc: Fabio Estevam
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc:
PCIE PHY IP block on i.MX7D differs from the one used on i.MX6 family,
so none of the code in current implementation of imx6_pcie_reset_phy()
is applicable.
Cc: bhelg...@google.com
Cc: Fabio Estevam
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc:
Everyone:
This series contains changes I made in order to enable support of PCIE
IP block on i.MX8MQ SoCs (full tree can be found at [github-v2]).
NOTE: The last patch have a Kconfig symbol depenency on [imx8mq-kconfig].
Changes since [v1]:
- Driver changed to use single "fsl,controller-id"
Everyone:
This series contains changes I made in order to enable support of PCIE
IP block on i.MX8MQ SoCs (full tree can be found at [github-v2]).
NOTE: The last patch have a Kconfig symbol depenency on [imx8mq-kconfig].
Changes since [v1]:
- Driver changed to use single "fsl,controller-id"
From: Lan Tianyu
Fix max line length problem.
Signed-off-by: Lan Tianyu
---
arch/x86/kvm/vmx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 6577ec8cbb0f..2356118ea440 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
From: Lan Tianyu
Fix max line length problem.
Signed-off-by: Lan Tianyu
---
arch/x86/kvm/vmx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 6577ec8cbb0f..2356118ea440 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
From: Lan Tianyu
This patch is to initialize ept_pointer to INVALID_PAGE and check it
before flushing ept tlb. If ept_pointer is invalid, bypass the flush
request.
Signed-off-by: Lan Tianyu
---
arch/x86/kvm/vmx.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git
From: Lan Tianyu
This patch is to initialize ept_pointer to INVALID_PAGE and check it
before flushing ept tlb. If ept_pointer is invalid, bypass the flush
request.
Signed-off-by: Lan Tianyu
---
arch/x86/kvm/vmx.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git
* Sean Christopherson wrote:
> ...instead of manually handling the case where error_code=0, e.g. to
> display "[SUPERVISOR] [READ]" instead of "normal kernel read fault".
>
> This makes the zero case consistent with all other messages and also
> provides additional information for other error
* Sean Christopherson wrote:
> ...instead of manually handling the case where error_code=0, e.g. to
> display "[SUPERVISOR] [READ]" instead of "normal kernel read fault".
>
> This makes the zero case consistent with all other messages and also
> provides additional information for other error
If the number of input parameters is less than the total
parameters, an EINVAL error will be returned.
e.g.
We use proc_doulongvec_minmax to pass up to two parameters
with kern_table.
{
.procname = "monitor_signals",
.data = _sigs,
.maxlen =
If the number of input parameters is less than the total
parameters, an EINVAL error will be returned.
e.g.
We use proc_doulongvec_minmax to pass up to two parameters
with kern_table.
{
.procname = "monitor_signals",
.data = _sigs,
.maxlen =
On Tue 04 Dec 23:15 PST 2018, Stephen Boyd wrote:
> Quoting David Dai (2018-12-04 17:14:10)
> >
> > On 12/4/2018 2:34 PM, Stephen Boyd wrote:
> > > Quoting Alex Elder (2018-12-04 13:41:47)
> > >> On 12/4/18 1:24 PM, Stephen Boyd wrote:
> > >>> Quoting David Dai (2018-12-03 19:50:13)
> > Add
From: Paul Selles
Current Switchtec's BAR setup registers are limited to 32bits,
corresponding to the maximum MW (memory window) size is <4G.
Increase the MW sizes with the addition of the BAR Setup Extension
Register for the upper 32bits of a 64bits MW size. This increases the MW
range to
The number of available NT req id mapping table entries per NTB control
register is 512. The driver mistakenly limits the number to 256.
Fix the array size of NT req id mapping table.
Fixes: c082b04c9d40 ("NTB: switchtec: Add NTB hardware register definitions")
Signed-off-by: Wesley Sheng
Hi, Everyone,
This patch series adds support of >=4G memory windows.
Current Switchtec's BAR setup registers are limited to 32bits,
corresponding to the maximum MW (memory window) size is <4G.
Increase the MW sizes with the addition of the BAR Setup Extension
Register for the upper 32bits of a
From: Paul Selles
Current Switchtec's BAR setup registers are limited to 32bits,
corresponding to the maximum MW (memory window) size is <4G.
Increase the MW sizes with the addition of the BAR Setup Extension
Register for the upper 32bits of a 64bits MW size. This increases the MW
range to
The number of available NT req id mapping table entries per NTB control
register is 512. The driver mistakenly limits the number to 256.
Fix the array size of NT req id mapping table.
Fixes: c082b04c9d40 ("NTB: switchtec: Add NTB hardware register definitions")
Signed-off-by: Wesley Sheng
Hi, Everyone,
This patch series adds support of >=4G memory windows.
Current Switchtec's BAR setup registers are limited to 32bits,
corresponding to the maximum MW (memory window) size is <4G.
Increase the MW sizes with the addition of the BAR Setup Extension
Register for the upper 32bits of a
On Tue 04 Dec 23:15 PST 2018, Stephen Boyd wrote:
> Quoting David Dai (2018-12-04 17:14:10)
> >
> > On 12/4/2018 2:34 PM, Stephen Boyd wrote:
> > > Quoting Alex Elder (2018-12-04 13:41:47)
> > >> On 12/4/18 1:24 PM, Stephen Boyd wrote:
> > >>> Quoting David Dai (2018-12-03 19:50:13)
> > Add
From: Paul Selles
Switchtec NTB crosslink BARs are 64bit addressed but they are printed as
32bit addressed BARs. Fix debug log to increment the BAR numbers by 2 to
reflect the 64bit address alignment.
Fixes: 017525018202 ("ntb_hw_switchtec: Add initialization code for crosslink")
Signed-off-by:
From: Paul Selles
Switchtec NTB crosslink BARs are 64bit addressed but they are printed as
32bit addressed BARs. Fix debug log to increment the BAR numbers by 2 to
reflect the 64bit address alignment.
Fixes: 017525018202 ("ntb_hw_switchtec: Add initialization code for crosslink")
Signed-off-by:
Hi Morimoto-san
On 2018/12/06 14:38, Kuninori Morimoto wrote:
Hi Jiada
SMSTPCR922 controls input of two clocks "S0D1ϕ" and "S0D4ϕ",
Ahh, OK I could check it via Block diagram.
But it is "Module stop" for these, anyway.
"Module stop" and "S0D1ϕ/S0D4ϕ" are completely different clocks.
Yes,
Hi Morimoto-san
On 2018/12/06 14:38, Kuninori Morimoto wrote:
Hi Jiada
SMSTPCR922 controls input of two clocks "S0D1ϕ" and "S0D4ϕ",
Ahh, OK I could check it via Block diagram.
But it is "Module stop" for these, anyway.
"Module stop" and "S0D1ϕ/S0D4ϕ" are completely different clocks.
Yes,
Convert all instances of 1 << x to BIT(x) for consistency with other
kernel code.
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc:
Convert all instances of 1 << x to BIT(x) for consistency with other
kernel code.
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc:
Move identical offset calculation code into a small helper function
and make use of it in the rest of the code.
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Add code needed to support i.MX8MQ.
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Make error messages more consistent by making sure each starts with
"%pOF:".
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc:
Add code needed to support i.MX8MQ.
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Make error messages more consistent by making sure each starts with
"%pOF:".
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc:
Move identical offset calculation code into a small helper function
and make use of it in the rest of the code.
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Everyone:
This series is 4 trivial (and optional) changes and a patch to add
support for i.MX8MQ to GPCv2 irqchip driver. Bingings for new GPC
variant were taken from [gpcv2-imx8mq]. Hopefully all of the patches
are self-explanatory.
Feedback is welcome!
Thanks,
Andrey Smrinov
[gpcv2-imx8mq]
Varaible 'reg' in imx_gpcv2_irq_set_wake() has no users. Remove it.
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc: linux-arm-ker...@lists.infradead.org
Cc:
Everyone:
This series is 4 trivial (and optional) changes and a patch to add
support for i.MX8MQ to GPCv2 irqchip driver. Bingings for new GPC
variant were taken from [gpcv2-imx8mq]. Hopefully all of the patches
are self-explanatory.
Feedback is welcome!
Thanks,
Andrey Smrinov
[gpcv2-imx8mq]
Varaible 'reg' in imx_gpcv2_irq_set_wake() has no users. Remove it.
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphe...@gmail.com
Cc: l.st...@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc: linux-arm-ker...@lists.infradead.org
Cc:
Hi all,
Today's linux-next merge of the akpm-current tree got a conflict in:
fs/btrfs/extent_io.c
between commit:
e42c38c80535 ("btrfs: Refactor main loop in extent_readpages")
from the btrfs-kdave tree and commit:
"fs: don't open code lru_to_page()"
from the akpm-current tree.
I
Hi all,
Today's linux-next merge of the akpm-current tree got a conflict in:
fs/btrfs/extent_io.c
between commit:
e42c38c80535 ("btrfs: Refactor main loop in extent_readpages")
from the btrfs-kdave tree and commit:
"fs: don't open code lru_to_page()"
from the akpm-current tree.
I
To get the number of cache leaves on AMD or Hygon platform, it should
get the value of cpuid leaf 0x801d. But on certain broken platform
such as a not fullly implemented virtual platform(for example Xen),
the value of the cpuid leaf will nerver be CTYPE_NULL, so the kernel
will run into an
To get the number of cache leaves on AMD or Hygon platform, it should
get the value of cpuid leaf 0x801d. But on certain broken platform
such as a not fullly implemented virtual platform(for example Xen),
the value of the cpuid leaf will nerver be CTYPE_NULL, so the kernel
will run into an
On Wed, Dec 05, 2018 at 11:39:05PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 29, 2018 at 03:12:15PM +0100, Greg Kroah-Hartman wrote:
> > 4.19-stable review patch. If anyone has any objections, please let me know.
>
> This one apparently introduces some annoying dmesg errors:
> [3.487895]
On Wed, Dec 05, 2018 at 11:39:05PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 29, 2018 at 03:12:15PM +0100, Greg Kroah-Hartman wrote:
> > 4.19-stable review patch. If anyone has any objections, please let me know.
>
> This one apparently introduces some annoying dmesg errors:
> [3.487895]
On Thu 06-12-18 11:34:30, Pingfan Liu wrote:
[...]
> > I suspect we are looking at two issues here. The first one, and a more
> > important one is that there is a NUMA affinity configured for the device
> > to a non-existing node. The second one is that nr_cpus affects
> > initialization of
On Thu 06-12-18 11:34:30, Pingfan Liu wrote:
[...]
> > I suspect we are looking at two issues here. The first one, and a more
> > important one is that there is a NUMA affinity configured for the device
> > to a non-existing node. The second one is that nr_cpus affects
> > initialization of
Hi,
Kindly, this format change formats the rtc dump from:
alrm_time : 00:00:00
alrm_date : 1970-01-01
alarm_IRQ : no
alrm_pending: no
to:
alarm time : 00:00:00
alarm date : 1970-01-01
alarm IRQ
Hi,
Kindly, this format change formats the rtc dump from:
alrm_time : 00:00:00
alrm_date : 1970-01-01
alarm_IRQ : no
alrm_pending: no
to:
alarm time : 00:00:00
alarm date : 1970-01-01
alarm IRQ
On Tue 20 Nov 13:02 PST 2018, Sibi Sankar wrote:
> After sending a sysmon shutdown request to the SSCTL service on the
> subsystem, wait for the service to send shutdown-ack interrupt or
> an indication message back.
>
So we get a reply immediate on the shutdown request, and then some time
On Tue 20 Nov 13:02 PST 2018, Sibi Sankar wrote:
> After sending a sysmon shutdown request to the SSCTL service on the
> subsystem, wait for the service to send shutdown-ack interrupt or
> an indication message back.
>
So we get a reply immediate on the shutdown request, and then some time
On Wed, 5 Dec 2018 at 20:51, Rob Herring wrote:
>
> Convert string compares of DT node names to use of_node_name_eq helper
> instead. This removes direct access to the node name pointer.
>
> Cc: Tomasz Figa
> Cc: Krzysztof Kozlowski
> Cc: Sylwester Nawrocki
> Cc: Linus Walleij
> Cc:
On Wed, 5 Dec 2018 at 20:51, Rob Herring wrote:
>
> Convert string compares of DT node names to use of_node_name_eq helper
> instead. This removes direct access to the node name pointer.
>
> Cc: Tomasz Figa
> Cc: Krzysztof Kozlowski
> Cc: Sylwester Nawrocki
> Cc: Linus Walleij
> Cc:
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Thursday, December 6, 2018 12:16 PM
> To: Yogesh Narayan Gaur
> Cc: Vignesh R ; broo...@kernel.org; linux-
> m...@lists.infradead.org; marek.va...@gmail.com; linux-...@vger.kernel.org;
>
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Thursday, December 6, 2018 12:16 PM
> To: Yogesh Narayan Gaur
> Cc: Vignesh R ; broo...@kernel.org; linux-
> m...@lists.infradead.org; marek.va...@gmail.com; linux-...@vger.kernel.org;
>
On Thu, 6 Dec 2018 04:20:26 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Wednesday, December 5, 2018 6:16 PM
> > To: Vignesh R ; broo...@kernel.org
> > Cc: Yogesh Narayan Gaur ; linux-
> >
This patchset adds PMU driver for Cavium's ThunderX2 SoC UNCORE devices.
The SoC has PMU support in L3 cache controller (L3C) and in the
DDR4 Memory Controller (DMC).
v10:
Updated Documentation patch with comments [6].
[6] https://lkml.org/lkml/2018/12/5/649
v9:
Updated with
On Thu, 6 Dec 2018 04:20:26 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Wednesday, December 5, 2018 6:16 PM
> > To: Vignesh R ; broo...@kernel.org
> > Cc: Yogesh Narayan Gaur ; linux-
> >
This patchset adds PMU driver for Cavium's ThunderX2 SoC UNCORE devices.
The SoC has PMU support in L3 cache controller (L3C) and in the
DDR4 Memory Controller (DMC).
v10:
Updated Documentation patch with comments [6].
[6] https://lkml.org/lkml/2018/12/5/649
v9:
Updated with
> Btw. the way how we drop all the work on the first page that we
> cannot
> isolate is just goofy. Why don't we simply migrate all that we
> already
> have on the list and go on? Something for a followup cleanup though.
Indeed, that is just wrong.
I will try to send a followup cleanup to fix
> Btw. the way how we drop all the work on the first page that we
> cannot
> isolate is just goofy. Why don't we simply migrate all that we
> already
> have on the list and go on? Something for a followup cleanup though.
Indeed, that is just wrong.
I will try to send a followup cleanup to fix
The context loaded only one time before channel running,but
currently sdma_config_channel() and dma_prep_* duplicated with
sdma_load_context(), so refine it to load context only one time
before channel running and reload after the channel terminated.
Signed-off-by: Robin Gong
---
The context loaded only one time before channel running,but
currently sdma_config_channel() and dma_prep_* duplicated with
sdma_load_context(), so refine it to load context only one time
before channel running and reload after the channel terminated.
Signed-off-by: Robin Gong
---
The accelerometer's power supply could be controlled by regulator
on some platforms, such as i.MX6Q-SABRESD board, the mma8451's
power supply is controlled by a GPIO fixed regulator, need to make
sure the regulator is enabled before any communication with mma8451,
this patch adds optional vcc
The accelerometer's power supply could be controlled by regulator
on some platforms, such as i.MX6Q-SABRESD board, the mma8451's
power supply is controlled by a GPIO fixed regulator, need to make
sure the regulator is enabled before any communication with mma8451,
this patch adds optional vcc
Add SCM tree for the gnss subsystem.
Signed-off-by: Johan Hovold
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6682420421c1..03766ddf95a3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6316,6 +6316,7 @@ F:
Add SCM tree for the gnss subsystem.
Signed-off-by: Johan Hovold
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6682420421c1..03766ddf95a3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6316,6 +6316,7 @@ F:
Exclude the gnss subsystem from SIRMPRIMA2 regex matching, which would
otherwise match the unrelated gnss sirf driver.
Cc: Barry Song
Signed-off-by: Johan Hovold
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 03766ddf95a3..0f083103d625
The accelerometer's power supply could be controlled by regulator
on some platforms, add optional property "vcc-supply" to let device
tree to pass phandle to the regulator to driver.
Signed-off-by: Anson Huang
---
Documentation/devicetree/bindings/iio/accel/mma8452.txt | 2 ++
1 file changed, 2
The accelerometer's power supply could be controlled by regulator
on some platforms, add optional property "vcc-supply" to let device
tree to pass phandle to the regulator to driver.
Signed-off-by: Anson Huang
---
Documentation/devicetree/bindings/iio/accel/mma8452.txt | 2 ++
1 file changed, 2
Exclude the gnss subsystem from SIRMPRIMA2 regex matching, which would
otherwise match the unrelated gnss sirf driver.
Cc: Barry Song
Signed-off-by: Johan Hovold
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 03766ddf95a3..0f083103d625
Hi all,
After merging the device-mapper tree, today's linux-next build (powerpc
ppc44x_defconfig) failed like this:
In file included from arch/powerpc/include/asm/local.h:144,
from include/linux/genhd.h:20,
from block/genhd.c:7:
block/genhd.c: In function
Hi all,
After merging the device-mapper tree, today's linux-next build (powerpc
ppc44x_defconfig) failed like this:
In file included from arch/powerpc/include/asm/local.h:144,
from include/linux/genhd.h:20,
from block/genhd.c:7:
block/genhd.c: In function
On Tue, 4 Dec 2018 at 18:38, Faiz Abbas wrote:
>
> Hi,
>
> On 04/12/18 12:54 PM, Chunyan Zhang wrote:
> > Some standard SD host controllers can support both external dma
> > controllers as well as ADMA/SDMA in which the SD host controller
> > acts as DMA master. TI's omap controller is the case
On Tue, 4 Dec 2018 at 18:38, Faiz Abbas wrote:
>
> Hi,
>
> On 04/12/18 12:54 PM, Chunyan Zhang wrote:
> > Some standard SD host controllers can support both external dma
> > controllers as well as ADMA/SDMA in which the SD host controller
> > acts as DMA master. TI's omap controller is the case
On 12/05/2018 08:26 PM, Matthew Wilcox wrote:
> On Wed, Dec 05, 2018 at 04:44:15PM -0800, Anthony Yznaga wrote:
>> On 12/05/2018 11:44 AM, Matthew Wilcox wrote:
>>> Nobody seems terribly interested in mapcount overflows. I got no response
>>> to https://lkml.org/lkml/2018/3/2/991
>> Okay.
On 12/05/2018 08:26 PM, Matthew Wilcox wrote:
> On Wed, Dec 05, 2018 at 04:44:15PM -0800, Anthony Yznaga wrote:
>> On 12/05/2018 11:44 AM, Matthew Wilcox wrote:
>>> Nobody seems terribly interested in mapcount overflows. I got no response
>>> to https://lkml.org/lkml/2018/3/2/991
>> Okay.
On Thu, 2018-12-06 at 09:09 +0800, Jianjun Wang wrote:
> MT7629 is an arm platform SoC which has the same PCIe IP with MT7622.
>
> The read value of BAR0 is 0x_, it's size will be calculated as 4GB
> in arm64 but bogus alignment values at arm32, the pcie device and devices
:s /the pcie
On Thu, 2018-12-06 at 09:09 +0800, Jianjun Wang wrote:
> MT7629 is an arm platform SoC which has the same PCIe IP with MT7622.
>
> The read value of BAR0 is 0x_, it's size will be calculated as 4GB
> in arm64 but bogus alignment values at arm32, the pcie device and devices
:s /the pcie
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