On Fri, 1 Feb 2019 07:07:40 +
wrote:
> >
> >> #define QSPI_IFR_TFRTYP_MASKGENMASK(13, 12)
> >> #define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12)
> >> #define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12)
> >
> > Looks like the read/write flag is on bit 13. Can we just add
No users left.
Signed-off-by: Christoph Hellwig
---
block/blk-mq.c | 1 -
include/linux/blkdev.h | 2 --
2 files changed, 3 deletions(-)
diff --git a/block/blk-mq.c b/block/blk-mq.c
index 3ba37b9e15e9..502cbf964a3b 100644
--- a/block/blk-mq.c
+++ b/block/blk-mq.c
@@ -331,7 +331,6 @@
No more need in a blk-mq world where the scsi command and request
are allocated together.
Signed-off-by: Christoph Hellwig
---
drivers/scsi/qedf/qedf_io.c | 6 --
drivers/scsi/qedi/qedi_fw.c | 7 ---
drivers/scsi/scsi_lib.c | 3 ---
drivers/scsi/sr.c | 1 -
4 files
Now that all the users are gone the SCSI OSD library can be removed
as well.
Signed-off-by: Christoph Hellwig
---
Documentation/scsi/osd.txt | 192 ---
MAINTAINERS |6 -
drivers/scsi/Kconfig |2 -
drivers/scsi/Makefile|1 -
We can just stash away the second request in struct bsg_job instead
of using the block layer req->next_rq field, allowing for the eventual
removal of the latter.
Signed-off-by: Christoph Hellwig
---
block/bsg-lib.c | 44 +---
block/bsg.c |
Move all actual functionality into helpers, just leaving the dispatch
in this function.
Signed-off-by: Christoph Hellwig
Reviewed-by: Benjamin Block
Tested-by: Benjamin Block
Tested-by: Avri Altman
---
block/bsg.c | 158
1 file changed, 72
Unused now, and another field in struct request bites the dust.
Signed-off-by: Christoph Hellwig
---
block/blk-mq-debugfs.c | 1 -
block/blk-mq.c | 3 ---
include/linux/blkdev.h | 6 --
3 files changed, 10 deletions(-)
diff --git a/block/blk-mq-debugfs.c b/block/blk-mq-debugfs.c
Thanks.
On 2019/2/1 14:59, Qing Xia wrote:
> In the first loop, gfp_flags will be modified to high_order_gfp_flags,
> and there will be no chance to change back to low_order_gfp_flags.
>
> Fixes: e7f63771 ("ION: Sys_heap: Add cached pool to spead up cached buffer
> alloc")
> Signed-off-by: Qing
No real need for bidi support once the OSD code is gone.
Signed-off-by: Christoph Hellwig
---
drivers/scsi/cxgbi/libcxgbi.c | 13 +++---
drivers/scsi/iscsi_tcp.c | 9 +
drivers/scsi/libiscsi.c| 64 +++---
drivers/scsi/libiscsi_tcp.c
The only real user of the T10 OSD protocol, the pNFS object layout
driver never went to the point of having shipping products, and we
removed it 1.5 years ago. Exofs is just a simple example without
real life users.
The code has been mostly unmaintained for years and is getting in the
way of
From: Eric Biggers
The generic MORUS implementations all fail the improved AEAD tests
because they produce the wrong result with some data layouts. The issue
is that they assume that if the skcipher_walk API gives 'nbytes' not
aligned to the walksize (a.k.a. walk.stride), then it is the end of
From: Eric Biggers
The generic AEGIS implementations all fail the improved AEAD tests
because they produce the wrong result with some data layouts. The issue
is that they assume that if the skcipher_walk API gives 'nbytes' not
aligned to the walksize (a.k.a. walk.stride), then it is the end of
From: Eric Biggers
The arm64 NEON bit-sliced implementation of AES-CTR fails the improved
skcipher tests because it sometimes produces the wrong ciphertext. The
bug is that the final keystream block isn't returned from the assembly
code when the number of non-final blocks is zero. This can
From: Eric Biggers
Check that algorithms do not change the aead_request structure, as users
may rely on submitting the request again (e.g. after copying new data
into the same source buffer) without reinitializing everything.
Signed-off-by: Eric Biggers
---
crypto/testmgr.c | 44
From: Eric Biggers
Check that algorithms do not change the skcipher_request structure, as
users may rely on submitting the request again (e.g. after copying new
data into the same source buffer) without reinitializing everything.
Signed-off-by: Eric Biggers
---
crypto/testmgr.c | 41
From: Eric Biggers
Hash algorithms with an alignmask set, e.g. "xcbc(aes-aesni)" and
"michael_mic", fail the improved hash tests because they sometimes
produce the wrong digest. The bug is that in the case where a
scatterlist element crosses pages, not all the data is actually hashed
because
From: Eric Biggers
Add functions that generate a random testvec_config, in preparation for
using it for randomized fuzz tests.
Signed-off-by: Eric Biggers
---
crypto/testmgr.c | 117 +++
1 file changed, 117 insertions(+)
diff --git
From: Eric Biggers
Crypto algorithms must produce the same output for the same input
regardless of data layout, i.e. how the src and dst scatterlists are
divided into chunks and how each chunk is aligned. Request flags such
as CRYPTO_TFM_REQ_MAY_SLEEP must not affect the result either.
From: Eric Biggers
To achieve more comprehensive crypto test coverage, I'd like to add fuzz
tests that use random data layouts and request flags.
To be most effective these tests should be part of testmgr, so they
automatically run on every algorithm registered with the crypto API.
However,
From: Eric Biggers
Convert alg_test_skcipher() to use the new test framework, adding a list
of testvec_configs to test by default. When the extra self-tests are
enabled, randomly generated testvec_configs are tested as well.
This improves skcipher test coverage mainly because now all
Hi Jiri,
On 2/1/19 1:13 PM, Jiri Olsa wrote:
> On Thu, Jan 31, 2019 at 09:27:11AM +0100, Jiri Olsa wrote:
>> On Wed, Jan 30, 2019 at 07:36:48PM +0100, Jiri Olsa wrote:
>>
>> SNIP
>>
>>> diff --git a/kernel/events/core.c b/kernel/events/core.c
>>> index 280a72b3a553..22ec63a0782e 100644
>>> ---
Hello,
Crypto algorithms must produce the same output for the same input
regardless of data layout, i.e. how the src and dst scatterlists are
divided into chunks and how each chunk is aligned. Request flags such
as CRYPTO_TFM_REQ_MAY_SLEEP must not affect the result either.
However, testing of
From: Eric Biggers
gcmaes_crypt_by_sg() dereferences the NULL pointer returned by
scatterwalk_ffwd() when encrypting an empty plaintext and the source
scatterlist ends immediately after the associated data.
Fix it by only fast-forwarding to the src/dst data scatterlists if the
data length is
From: Eric Biggers
The x86 MORUS implementations all fail the improved AEAD tests because
they produce the wrong result with some data layouts. The issue is that
they assume that if the skcipher_walk API gives 'nbytes' not aligned to
the walksize (a.k.a. walk.stride), then it is the end of the
From: Eric Biggers
Convert alg_test_aead() to use the new test framework, using the same
list of testvec_configs that skcipher testing uses.
This significantly improves AEAD test coverage mainly because previously
there was only very limited test coverage of the possible data layouts.
Now the
From: Eric Biggers
The x86 AEGIS implementations all fail the improved AEAD tests because
they produce the wrong result with some data layouts. The issue is that
they assume that if the skcipher_walk API gives 'nbytes' not aligned to
the walksize (a.k.a. walk.stride), then it is the end of the
From: Eric Biggers
Convert alg_test_hash() to use the new test framework, adding a list of
testvec_configs to test by default. When the extra self-tests are
enabled, randomly generated testvec_configs are tested as well.
This improves hash test coverage mainly because now all algorithms have
a
On Fri 01-02-19 08:12:03, Michal Hocko wrote:
> On Thu 31-01-19 23:57:11, Chris Down wrote:
> > memcg is NULL if we have CONFIG_MEMCG set, but cgroup_disable=memory on
> > the kernel command line.
> >
> > Fixes: 8a907cdf0177ab40 ("mm, memcg: proportional memory.{low,min} reclaim")
>
> JFYI this
On Thu, Jan 31, 2019 at 09:27:11AM +0100, Jiri Olsa wrote:
> On Wed, Jan 30, 2019 at 07:36:48PM +0100, Jiri Olsa wrote:
>
> SNIP
>
> > diff --git a/kernel/events/core.c b/kernel/events/core.c
> > index 280a72b3a553..22ec63a0782e 100644
> > --- a/kernel/events/core.c
> > +++
Hi,
On 19. 1. 31. 오후 5:49, Lukasz Luba wrote:
> Define new IDs for clocks used by Dynamic Memory Controller in
> Exynos5422 SoC.
>
> CC: Sylwester Nawrocki
> CC: Chanwoo Choi
> CC: Rob Herring
> CC: Mark Rutland
> CC: Kukjin Kim
> CC: Krzysztof Kozlowski
> CC:
Hi Mark
> Currently kctrl with same name can only be created once,
> but in "MIX Playback Volume" case, same kctrl is used to
> control different MIX volume for different dai-link.
>
> this patch by check kctrl's cfg, allow to create kctrl
> with same name but different cfg.
>
> Fixes: commit
From: Michael Kao
This patch adds binding document for mt8183 thermal controller.
Signed-off-by: Michael Kao
---
Documentation/devicetree/bindings/thermal/mediatek-thermal.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
From: Michael Kao
One thermal controller can read four sensors at most,
so we need to add controller_offset for the project with
more than four sensors to reuse the same register settings.
Signed-off-by: Michael Kao
---
drivers/thermal/mtk_thermal.c | 79
From: Michael Kao
MT8183 has two built-in thermal controllers with total six thermal
sensors. And it doesn't have bank, so doesn't need to select bank.
This patch adds support for mt8183.
Signed-off-by: Michael Kao
---
drivers/thermal/mtk_thermal.c | 98
From: Michael Kao
The index of msr and adcpnp should match the sensor
which belongs to the selected bank in the for loop.
Signed-off-by: Michael Kao
---
drivers/thermal/mtk_thermal.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/thermal/mtk_thermal.c
From: Michael Kao
Each project has different number of vts settings.
For the MT2701 just have to set three vts, but the
original code flow add five unnecessary vts.
Add common index of vts settings for scalablity,
and reduce the setting of unnecessary vts.
Signed-off-by: Michael Kao
---
From: Michael Kao
For past ic designs, the thermal controller should select banks before
reading the thermal sensor.
And the new ic design architecture removes this mechanism.
Signed-off-by: Michael Kao
---
drivers/thermal/mtk_thermal.c | 20 ++--
1 file changed, 14
From: Michael Kao
Add calibration item in thermal_data to support
the project with different calibration coefficient.
Signed-off-by: Michael Kao
---
drivers/thermal/mtk_thermal.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git
From: Michael Kao
This patchset supports for mt8183 chip to mtk_thermal.c.
MT8183 has six temperature sensors and two thermal
controllers. It has different calibration coefficent with
past project, and doesn't need to select bank.
As a result, we add the common architecture for scalability.
On Thu, Jan 31, 2019 at 9:42 PM Herbert Xu wrote:
>
> This push fixes a bug in cavium/nitrox where the callback is invoked
> prior to the DMA unmap.
This is not so much a comment about the pull itself (which I did half
an hour ago), as about the fact that it looks like the pr-tracker
robot
Only Coffeelake should use Cannonlake regmap other than Cannonlake
platform. This allows Coffeelake special handling only when there is no
matching PCI device and default reg map selected as per CPUID is for
Sunrisepoint PCH. This change is needed to enable support for newer SoCs
such as Icelake.
On some platforms such as HP Elite-x2-1013-g3, the platform BIOS
enforces XTAL to remain off before S0ix state can be achieved. This may
not be optimum when we want to enable use cases like Low Power Audio,
Wake on Voice etc which always need 24mhz clock.
This introduces a new quirk to allow S0ix
File permissions for ltr_show attribute should be similar to other
debugfs attributes created by this driver. '0644' should be used only
when there is a write operation desired such as for ltr_ignore.
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Fixes: 63cde0c16c67 ("platform/x86: intel_pmc_core:
This patch series provides Icelake support for PMC Core driver and while
doing so it introduces the Icelake Mobile to intel-family.h as per the
CPUID from below Coreboot link
This patch introduces a new debugfs entry to read current Package
cstate residency counters. A similar variant of this patch was discussed
earlier "https://patchwork.kernel.org/patch/9908563/; but didn't make it
into mainline for various reasons. Current version only adds debugfs
entry which is
Icelake can resue most of the CNL PCH IPs as they are mostly similar.
This patch enables the PMC Core driver for ICL family.
It also addresses few other minor issues like upper case conversions and
some tab alignments.
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Signed-off-by: Rajneesh Bhardwaj
Add CPUID of Icelake (ICL) mobile processors to Intel family list. The
Information related to ICL CPUID is referenced from below Coreboot
project link.
https://github.com/coreboot/coreboot/blob/5ebcea33cd358bc5bccaa156b13a6ef25df6/src/soc/intel/common/block/include/intelblocks/mp_init.h
Cc:
For Cannonlake and Icelake, the IP name for Res_6 should be SPF i.e.
South Port F. No functional change is intended other than just renaming
the IP appropriately.
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Fixes: 291101f6a735 ("platform/x86: intel_pmc_core: Add CannonLake PCH support")
INTEL_CPU_FAM6() macro provides better abstraction and reduces code size so use
it instead of custom grown ICPU().
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git
Recently introduced commit "platform/x86: intel_pmc_core: Show Latency
Tolerance info <51337cd94d18184601ac0fb4cf1a02b8bbabc3d7> skipped the
LTR from a reserved IP. Though this doesn't cause any functional issue
but it is needed for the consumers of "ltr_ignore" as the index printing
for
A previous commit "platform/x86: intel_pmc_core: Make the driver PCH
family agnostic " provided
better abstraction to this driver but has some fundamental issues.
e.g. the following condition
for (index = 0; index < pmcdev->map->ppfear_buckets &&
index < PPFEAR_MAX_NUM_ENTRIES; index++,
Elaborate on possible perf_event/Perf privileged users groups
and document steps about creating such groups.
Signed-off-by: Alexey Budankov
---
Documentation/admin-guide/perf-security.rst | 43 +
1 file changed, 43 insertions(+)
diff --git
Document and categorize system and performance data into groups that
can be captured by perf_events/Perf and explicitly indicate the group
that can contain process sensitive data.
Signed-off-by: Alexey Budankov
---
Documentation/admin-guide/perf-security.rst | 32 +++--
1 file
Extend perf-security.rst file with perf_events/Perf resource control
section describing RLIMIT_NOFILE and perf_event_mlock_kb settings for
performance monitoring user processes.
Signed-off-by: Alexey Budankov
---
Documentation/admin-guide/perf-security.rst | 36 +
1 file
The pull request you sent on Thu, 31 Jan 2019 16:03:32 -0600:
> git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
> tags/pci-v5.0-fixes-3
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/44e56f325b7d63e8a53008956ce7b28e4272a599
Thank you!
--
The pull request you sent on Thu, 31 Jan 2019 23:10:37 -0800:
> https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
> tags/clk-fixes-for-linus
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/5b4746a031992d3b788b7e5280d949b8ab6d32d0
Thank you!
--
On Thu, Jan 31, 2019 at 11:04:31AM -0800, Gurchetan Singh wrote:
> On Wed, Jan 30, 2019 at 1:43 AM Gerd Hoffmann wrote:
> >
> > There is no need to wait for completion here.
> >
> > The host will process commands in submit order, so commands can
> > reference the new resource just fine even when
The patch set extends the first version of perf-security.rst documentation
file [1], [2], [3] with the following topics:
1) perf_events/Perf resource limits and control management that describes
RLIMIT_NOFILE and perf_event_mlock_kb settings for processes conducting
performance
On Thu, Jan 31, 2019 at 11:05 PM Linus Torvalds
wrote:
>
> And part of "best effort" is very much "not a security information leak".
Side note: it's entirely possible that the preadv2(RWF_NOWAIT)
interface is actually already effectively too slow to be effectively
used as much of an attack
On Thu 31-01-19 20:13:52, Chris Down wrote:
[...]
> The current situation goes against both the expectations of users of
> memory.high, and our intentions as cgroup v2 developers. In
> cgroup-v2.txt, we claim that we will throttle and only under "extreme
> conditions" will memory.high protection
Hey Bjorn,
Tested-by: Sibi Sankar
Reviewed-by: Sibi Sankar
On 01/31/2019 06:09 AM, Bjorn Andersson wrote:
The AOSS QMP provides a number of power domains, used for QDSS and
PIL, add the node for this.
Signed-off-by: Bjorn Andersson
---
Changes since v4:
- None
Changes since v3:
- None
On Thu, Jan 31, 2019 at 11:24:22AM -0800, Thomas Garnier wrote:
> Provide an option to default visibility to hidden except for key
> symbols.
It took me a while to figure out the verb in this sentence... :P
It's weird that we're annotating things to be default. What visibility
are they we
Hey Bjorn,
On 01/31/2019 06:09 AM, Bjorn Andersson wrote:
The AOSS QMP genpd provider implements control over power-related
resources related to low-power state associated with the remoteprocs in
the system as well as control over a set of clocks related to debug
hardware in the SoC.
Quoting Stephen Boyd (2019-01-31 13:53:42)
>
> I'm prototyping out some code to do the remapping based on this type of
> DT property, because it will make the irqdomain::alloc function a little
> simpler to implement by passing in a struct irq_fwspec and getting out a
> parent irq_fwspec and it
On Thu, Jan 31, 2019 at 06:17:31PM +0800, lantianyu1...@gmail.com wrote:
>
>
This comment needs to be indented one tab or it looks like we're outside
the funciton.
> +/*
> + * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic,
> + * set x2apic destination mode to physcial mode
On Thu, Jan 31, 2019 at 9:16 PM Dave Chinner wrote:
>
> You are conflating "best effort non-blocking operation" with
> "atomic guarantee". RWF_NOWAIT/IOCB_NOWAIT is the
> former, not the latter.
Right.
That's my *point*, Dave.
It's not 'atomic guarantee", and never will be. We are in 100%
On Thu 31-01-19 23:57:11, Chris Down wrote:
> memcg is NULL if we have CONFIG_MEMCG set, but cgroup_disable=memory on
> the kernel command line.
>
> Fixes: 8a907cdf0177ab40 ("mm, memcg: proportional memory.{low,min} reclaim")
JFYI this is not a valid sha1. It is from linux next and it will
The following changes since commit b488517b28a47d16b228ce8dcf07f5cb8e5b3dc5:
clk: socfpga: stratix10: fix naming convention for the fixed-clocks
(2019-01-15 12:58:38 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
On Fri, Feb 1, 2019 at 3:07 PM Dan Carpenter wrote:
>
> On Thu, Jan 31, 2019 at 06:17:31PM +0800, lantianyu1...@gmail.com wrote:
> >
> >
>
> This comment needs to be indented one tab or it looks like we're outside
> the funciton.
>
> > +/*
> > + * Hyper-V doesn't provide irq remapping for
On 2019/2/1 13:22, Herbert Xu wrote:
> On Wed, Jan 23, 2019 at 09:08:51PM +0800, Zhou Wang wrote:
>>
>> +/**
>> + * hisi_qp_poll() - Poll current cqe to see if a task is finished.
>> + * @qp: The qp which will poll.
>> + *
>> + * This function polls current cqe for a give qp to see if a task is
Herbert,
On Fri, Feb 01, 2019 at 02:26:55PM +0800, Herbert Xu wrote:
> On Fri, Jan 25, 2019 at 09:01:16PM +0300, Vitaly Chikunov wrote:
> >
> > @@ -781,36 +780,17 @@ static int tpm_key_verify_signature(const struct key
> > *key,
> > if (!req)
> > goto error_free_tfm;
> >
> > -
On 01/31/2019 06:32 PM, Boris Brezillon wrote:
> On Thu, 31 Jan 2019 16:15:51 +
> wrote:
>
>> From: Tudor Ambarus
>>
>> The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
>> access, the other for the qspi core and phy. Both are mandatory. It uses
>> dedicated
Hi All,
On 2019-01-18 12:37, Christoph Hellwig wrote:
> Hi all,
>
> this series fixes a rather gross layering violation in videobuf2, which
> pokes into arm DMA mapping internals to get a DMA address for memory that
> does not have a page structure, and to do so fixes up the dma_map_resource
>
On Fri, Feb 01, 2019 at 01:31:46PM +0800, Herbert Xu wrote:
> On Wed, Jan 23, 2019 at 02:49:20PM -0800, Eric Biggers wrote:
> >
> > diff --git a/crypto/Kconfig b/crypto/Kconfig
> > index 86960aa53e0f..cbeba16fd8c1 100644
> > --- a/crypto/Kconfig
> > +++ b/crypto/Kconfig
> > @@ -168,6 +168,16 @@
In the first loop, gfp_flags will be modified to high_order_gfp_flags,
and there will be no chance to change back to low_order_gfp_flags.
Fixes: e7f63771 ("ION: Sys_heap: Add cached pool to spead up cached buffer
alloc")
Signed-off-by: Qing Xia
---
drivers/staging/android/ion/ion_system_heap.c
On Fri, Jan 25, 2019 at 03:07:48PM +0900, Masahiro Yamada wrote:
> The header search path -I. in kernel Makefiles is very suspicious;
> it allows the compiler to search for headers in the top of $(srctree),
> where obviously no header file exists.
>
> 'git grep BCMDRIVER' has no hit. So, this
On Fri, Jan 25, 2019 at 12:49:36PM +0900, Masahiro Yamada wrote:
> Currently, the Kbuild core manipulates header search paths in a crazy
> way [1].
>
> To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
> the search paths in the srctree. Some Makefiles are already written in
>
On 01/31/2019 06:55 PM, Boris Brezillon wrote:
> On Thu, 31 Jan 2019 16:15:28 +
> wrote:
>
>> From: Tudor Ambarus
>>
>> Cache MR value to avoid write access when setting the controller
>> in Serial Memory Mode (SMM). SMM is set in exec_op() and not at
>> probe time, to let room for future
On Wed, Jan 23, 2019 at 11:24:18AM +, Corentin Labbe wrote:
> When building without CONFIG_HW_RANDOM_PPC4XX, I hit the following build
> failure:
> drivers/crypto/amcc/crypto4xx_core.c: In function 'crypto4xx_probe':
> drivers/crypto/amcc/crypto4xx_core.c:1407:20: error: passing argument 1 of
On Wed, Jan 23, 2019 at 02:55:17PM +0800, YueHaibing wrote:
> Fix a static code checker warning:
> drivers/crypto/chelsio/chcr_algo.c:3681
> chcr_aead_op() warn: passing zero to 'PTR_ERR'
>
> Fixes: 2debd3325e55 ("crypto: chcr - Add AEAD algos.")
> Signed-off-by: YueHaibing
> ---
>
On Tue, Jan 22, 2019 at 04:14:15PM +0100, Greg Kroah-Hartman wrote:
> When calling debugfs code, there is no need to ever check the return
> value of the call, as no logic should ever change if a call works
> properly or not. Fix up a bunch of crypto-specific code to not care
> about the results
On 2019/1/31 23:12, Marc Zyngier wrote:
> Hi Zeng,
>
> On 31/01/2019 14:47, Zheng Xiang wrote:
>> Hi Marc,
>>
>> On 2019/1/29 13:42, Zheng Xiang wrote:
>>> On 2019/1/28 21:51, Marc Zyngier wrote:
On 28/01/2019 07:13, Zheng Xiang wrote:
> Hi Marc,
>
> Thanks for your review.
Loongson-1 is a series of MIPS MCUs.
This patch add the clock bindings for loongson-1b and
loongson-1c clock subsystem.
Signed-off-by: Jiaxun Yang
---
.../bindings/clock/loongson1-clock.txt | 14 ++
include/dt-bindings/clock/ls1b-clock.h | 17 +
The patch introduces options for loongson1 clocks so we can
select the driver we need.
Signed-off-by: Jiaxun Yang
---
drivers/clk/Kconfig| 1 +
drivers/clk/Makefile | 2 +-
drivers/clk/loongson1/Kconfig | 27 +++
drivers/clk/loongson1/Makefile |
This patch add of support by split the clk_hw register and
clkdev register, then handle the of clk_hw via
of_clk_hw_onecell_get.
Signed-off-by: Jiaxun Yang
---
drivers/clk/loongson1/clk-loongson1b.c | 197 -
drivers/clk/loongson1/clk-loongson1c.c | 164
v2->v3: Fix dt-bindings issues
On Fri, Jan 25, 2019 at 08:10:13AM +, Peng Ma wrote:
> Add SATA device nodes for fsl-lx2160a and enable support
> for QDS and RDB boards.
>
> Signed-off-by: Peng Ma
> ---
> changed for V5:
> - no change
>
> arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 +++
>
On Fri, Jan 25, 2019 at 09:01:16PM +0300, Vitaly Chikunov wrote:
>
> @@ -781,36 +780,17 @@ static int tpm_key_verify_signature(const struct key
> *key,
> if (!req)
> goto error_free_tfm;
>
> - ret = -ENOMEM;
> - outlen = crypto_akcipher_maxsize(tfm);
> - output =
On Wed, Jan 30, 2019 at 10:30 PM Paul Moore wrote:
>
> On Wed, Jan 30, 2019 at 4:01 PM syzbot
> wrote:
> >
> > Hello,
> >
> > syzbot found the following crash on:
> >
> > HEAD commit:62967898789d Merge git://git.kernel.org/pub/scm/linux/kern..
> > git tree: upstream
> > console output:
Dt-bindings doc about Loongson-1 interrupt controller.
Reviewed-by: Rob Herring
Signed-off-by: Jiaxun Yang
---
.../loongson,ls1x-intc.txt| 25 +++
1 file changed, 25 insertions(+)
create mode 100644
v1->v2: Fix SPDX-License-Identifier
v2->v3: Rework according suggestions from Marc Zyngier, Thanks.
v3->v4: Rework the driver into a single chip driver.
v4->v5: Fix minor issues.
v5->v6: Fix doc and collect Rob's review tag.
This controller appeared on Loongson-1 family MCUs
including Loongson-1B and Loongson-1C.
Signed-off-by: Jiaxun Yang
---
drivers/irqchip/Kconfig| 9 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ls1x.c | 192 +
3 files changed, 202
On 31-01-19, 23:02, Taniya Das wrote:
> Add support to read the voltage look up table and populate OPP for all
> corresponding CPUS for consumers like the energy model could use the
> frequency and voltage from the OPP tables. Also update the logic to not add
> duplicate OPPs.
>
> Tested-by:
On Wed, Jan 23, 2019 at 08:10:17AM -0600, Adam Ford wrote:
> The EVM consists of a system on module (SOM) and baseboard, and LCD.
> This patch adds a DTSI file for the SOM and baseboard separately,
> then a wrapper to combine them and specify processor type and a
> LCD information.
>
>
Freq attribute for "trans_table" is defined right after its callback
(without any blank line between them), but the others are defined
separately later on. Keep this consistent and define all attributes
right after their callbacks.
Signed-off-by: Viresh Kumar
---
drivers/cpufreq/cpufreq_stats.c
It is possible for cpufreq_stats_clear_table() and
cpufreq_stats_record_transition() to get called concurrently and they
will try to update same variables simultaneously and may lead to
corruption of data.
Prevent that with the help of existing spinlock.
Signed-off-by: Viresh Kumar
---
Hi John,
On 2019/1/31 17:54, John Garry wrote:
> On 30/01/2019 07:01, Hanjun Guo wrote:
>> From: Hanjun Guo
[...]
>>
>> drivers/usb/core/hcd-pci.c | 4
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/usb/core/hcd-pci.c b/drivers/usb/core/hcd-pci.c
>> index 0343246..a9c33e6
Hi James,
> -Original Message-
> From: linux-arm-kernel
> [mailto:linux-arm-kernel-boun...@lists.infradead.org] On Behalf Of
> James Morse
> Sent: Thursday, January 31, 2019 12:00 AM
> To: Zhang, Lei/張 雷
> Cc: 'Mark Rutland'; 'Catalin Marinas'; 'will.dea...@arm.com';
>
Hi Bjorn,
Commits
f14bcc0add3a ("Revert "PCI: armada8k: Add support for gpio controlled reset
signal"")
432dd7064aa1 ("ARM: cns3xxx: Use actual size reads for PCIe")
65dbb423cf28 ("ARM: cns3xxx: Fix writing to wrong PCI config registers after
alignment")
a4ace4fa2007 ("PCI: imx: Fix
comments fix: input_size is ZO image size which just don't count .bss
in, but has .text, .data, etc;
drop unecessary alignment: minimum is either 512M or output, both are
CONFIG_PHYSICAL_ALIGN aligned(output is aligned in head_32/64.S). But
mention it in earlier comments.
Signed-off-by: Cao jin
1 - 100 of 1208 matches
Mail list logo
