On Mon, Apr 8, 2019 at 5:04 PM Denys Vlasenko wrote:
>
> On 4/8/19 4:57 PM, Sedat Dilek wrote:
> > We have arch/x86/crypto/chacha-avx2-x86_64.S and
> > arch/x86/crypto/chacha-avx512vl-x86_64.S:
> >
> > .rodata.cst32.CTR2BL
> > .rodata.cst32.CTR4BL
> > .rodata.cst32.CTR2BL
> > .rodata.cst32.CTR4BL
On Sun, 7 Apr 2019, Linus Torvalds wrote:
> On Sat, Apr 6, 2019 at 12:59 PM Qian Cai wrote:
> >
> > The commit 510ded33e075 ("slab: implement slab_root_caches list")
> > changes the name of the list node within "struct kmem_cache" from
> > "list" to "root_caches_node", but leaks_show() still use
The chosen clocksource and clockevent bindings have never been accepted and
parsed, remove them.
Signed-off-by: Alexandre Belloni
---
arch/arm/boot/dts/at91sam9261ek.dts | 8
1 file changed, 8 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts
On Mon, Apr 08, 2019 at 04:12:11PM +0800, Zhao Yakui wrote:
> When acrn_hypervisor is detected, the hypercall is needed so that the
> acrn guest can query/config some settings. For example: it can be used
> to query the resources in hypervisor and manage the CPU/memory/device/
> interrupt for
Hello, Sebastian.
On Fri, Apr 05, 2019 at 04:42:18PM +0200, Sebastian Andrzej Siewior wrote:
> On 2019-03-22 18:59:23 [+0100], To Tejun Heo wrote:
> > On 2019-03-22 10:43:34 [-0700], Tejun Heo wrote:
> > > Hello,
> Hi,
>
> > > We can switch but it doesn't really say why we'd want to. Can you
>
On Mon, Apr 8, 2019 at 5:04 PM Denys Vlasenko wrote:
>
> On 4/8/19 4:57 PM, Sedat Dilek wrote:
> > We have arch/x86/crypto/chacha-avx2-x86_64.S and
> > arch/x86/crypto/chacha-avx512vl-x86_64.S:
> >
> > .rodata.cst32.CTR2BL
> > .rodata.cst32.CTR4BL
> > .rodata.cst32.CTR2BL
> > .rodata.cst32.CTR4BL
On Mon, Apr 08, 2019 at 09:05:19AM -0600, Jens Axboe wrote:
> I did consider that, and that would be doable. But honestly, I'm having a
> hard time seeing what issue we are attempting to fix by doing this.
Yeah, I guess the real fix would be to update the documentation and the
expectations
On Sun, Apr 7, 2019 at 10:53 PM Stephen Rothwell wrote:
>
> Hi Dan,
>
> In commit
>
> 7c33bd4e3e97 ("libnvdimm/pmem: fix a possible OOB access when read and
> write pmem")
>
> Fixes tag
>
> Fixes: 98cc093cba1e "(block, THP: make block_device_operations.rw_page
> support THP)"
>
> has these
> Il giorno 8 apr 2019, alle ore 17:05, Jens Axboe ha scritto:
>
> On 4/8/19 9:04 AM, Johannes Thumshirn wrote:
>> [+Cc Michal ]
>> On Mon, Apr 08, 2019 at 04:54:39PM +0200, Paolo Valente wrote:
>>>
>>>
Il giorno 8 apr 2019, alle ore 16:49, Johannes Thumshirn
ha scritto:
On Tue, Apr 02, 2019 at 12:45:05PM -0700, kan.li...@linux.intel.com wrote:
> +static struct event_constraint *
> +icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
> + struct perf_event *event)
> +{
> + /*
> + * Fixed counter 0 has less skid.
> + *
When calling debugfs functions, there is no need to ever check the
return value. The function can work or not, but the code logic should
never do something different based on this.
Cc: Greg Kroah-Hartman
Signed-off-by: Enric Balletbo i Serra
---
drivers/platform/chrome/cros_ec_debugfs.c | 35
On 4/8/19 9:04 AM, Johannes Thumshirn wrote:
> [+Cc Michal ]
> On Mon, Apr 08, 2019 at 04:54:39PM +0200, Paolo Valente wrote:
>>
>>
>>> Il giorno 8 apr 2019, alle ore 16:49, Johannes Thumshirn
>>> ha scritto:
>>>
>>> On Mon, Apr 08, 2019 at 04:39:35PM +0200, Paolo Valente wrote:
From:
On Mon, Apr 8, 2019 at 7:09 AM shuah wrote:
> The patch is series in now in linux-kselftest next for 5.2
Yay, awesome! :) Thanks!
--
Kees Cook
On 4/8/19 4:57 PM, Sedat Dilek wrote:
We have arch/x86/crypto/chacha-avx2-x86_64.S and
arch/x86/crypto/chacha-avx512vl-x86_64.S:
.rodata.cst32.CTR2BL
.rodata.cst32.CTR4BL
.rodata.cst32.CTR2BL
.rodata.cst32.CTR4BL
...and in arch/x86/crypto/sha256-avx2-asm.S and
On Mon, Apr 8, 2019 at 12:21 AM David Rheinsberg
wrote:
>
> Hi
>
> A recent commit changed how `/sys/module/apparmor/parameters/enabled`
> looks. It was "Y"/"N" before, now it is an integer. I *think* the
> commit that changed this was:
Oooh... the _output_ appears differently based on the type.
On Wed, May 9, 2018 at 7:03 PM syzbot
wrote:
>
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit:036db8bd9637 Merge branch 'for-4.17-fixes' of git://git.ke..
> git tree: upstream
> console output: https://syzkaller.appspot.com/x/log.txt?x=14d187e780
> kernel config:
You can prefix your subject now like this:
x86/acrn: Use ...
On Mon, Apr 08, 2019 at 04:12:10PM +0800, Zhao Yakui wrote:
> Linux kernel uses the HYPERVISOR_CALLBACK_VECTOR for hypervisor upcall
> vector. And it is already used for Xen and HyperV.
> After Acrn hypervisor is detected, it will also
We have arch/x86/crypto/chacha-avx2-x86_64.S and
arch/x86/crypto/chacha-avx512vl-x86_64.S:
.rodata.cst32.CTR2BL
.rodata.cst32.CTR4BL
.rodata.cst32.CTR2BL
.rodata.cst32.CTR4BL
...and in arch/x86/crypto/sha256-avx2-asm.S and
arch/x86/crypto/sha512-avx2-asm.S:
.rodata.cst32.PSHUFFLE_BYTE_FLIP_MASK
On Mon, Apr 08, 2019 at 07:41:15AM -0700, Sean Christopherson wrote:
> > +{
> > + if (guest_cpuid_is_amd(vcpu)) {
> > + struct msr_data tmp;
> > +
> > + tmp.index = MSR_K7_HWCR;
> > +
> > + if (kvm_get_msr_common(vcpu, ))
>
> No need to get through
On Tue, Apr 02, 2019 at 12:45:02PM -0700, kan.li...@linux.intel.com wrote:
> +static u64 pebs_update_adaptive_cfg(struct perf_event *event)
> +{
> + struct perf_event_attr *attr = >attr;
> + u64 sample_type = attr->sample_type;
> + u64 pebs_data_cfg = 0;
> + bool gprs, tsx_weight;
On Mon, Apr 8, 2019 at 4:42 PM Denys Vlasenko wrote:
>
> On 4/8/19 4:34 PM, Sedat Dilek wrote:
> > v2:
> >
> > sdi@iniza:~/src/linux-kernel/linux$ git --no-pager diff
> > diff --git a/arch/x86/crypto/camellia-aesni-avx-asm_64.S
> > b/arch/x86/crypto/camellia-aesni-avx-asm_64.S
> > index
+cc Alessandro Rubini
On 2019/4/8 22:37, Yue Haibing wrote:
> From: YueHaibing
>
> Syzkaller report this:
>
> kasan: GPF could be caused by NULL-ptr deref or user memory access
> general protection fault: [#1] SMP KASAN PTI
> CPU: 0 PID: 3692 Comm: syz-executor.0 Tainted: G C
The ASPEED AST2400, and AST2500 in some configurations include a
PCI-to-AHB MMIO bridge. This bridge allows a server to read and write
in the BMC's physical address space. This feature is especially useful
when using this bridge to send large files to the BMC.
The host may use this to send down
On 4/8/19 4:34 PM, Sedat Dilek wrote:
v2:
sdi@iniza:~/src/linux-kernel/linux$ git --no-pager diff
diff --git a/arch/x86/crypto/camellia-aesni-avx-asm_64.S
b/arch/x86/crypto/camellia-aesni-avx-asm_64.S
index a14af6eb09cb..712d6a7e8b8f 100644
--- a/arch/x86/crypto/camellia-aesni-avx-asm_64.S
+++
Hello,
overall looks good for me.
I would just prefer to change the define name for temperature to
INV_ICM20602_SCAN_TEMP. It is the chip temperature that can be used for
temperature compensation for both accel and gyro data.
But it is really just a details.
Best regards,
Jean-Baptiste
Document the ast2400, ast2500 PCI-to-AHB bridge control driver bindings.
Signed-off-by: Patrick Venture
Reviewed-by: Rob Herring
---
Changes for v10:
- Chopped out nearly identical information.
Changes for v9:
- Added missing details about syscon parent
Changes for v8:
- None
Changes for v7:
On Mon, Apr 08, 2019 at 11:09:46AM +0200, Borislav Petkov wrote:
> Hi all,
>
> here's v5 which keeps the HWCR functionality in kvm/x86.c so that
> emulation of AMD guests on Intel hw still can work.
>
> --
> From: Borislav Petkov
>
> The AMD hardware configuration register has some useful bits
From: YueHaibing
When building with CONFIG_SPI_MEM is not set
gc warns this:
drivers/spi/spi-zynq-qspi.o: In function `zynq_qspi_supports_op':
spi-zynq-qspi.c:(.text+0x1da): undefined reference to
`spi_mem_default_supports_op'
Fixes: 67dca5e580f1 ("spi: spi-mem: Add support for Zynq QSPI
On Mon, Apr 08, 2019 at 04:12:09PM +0800, Zhao Yakui wrote:
> ACRN is an open-source hypervisor maintained by Linuxfoundation.
I think tglx wanted to say "by the Linux Foundation" here.
> This is to add the Linux guest support on acrn-hypervisor.
I think you were told already:
"Please do not
Hi,
On Mon, 8 Apr 2019 at 12:42, Maxime Ripard wrote:
>
> On Mon, Apr 08, 2019 at 11:26:14AM +0200, Clément Péron wrote:
> > There is only one pinmuxing available for each MMC controller.
> >
> > Move the pinctrl to the SOC
> >
> > Signed-off-by: Clément Péron
> > ---
> >
From: YueHaibing
Syzkaller report this:
kasan: GPF could be caused by NULL-ptr deref or user memory access
general protection fault: [#1] SMP KASAN PTI
CPU: 0 PID: 3692 Comm: syz-executor.0 Tainted: G C5.0.0+ #5
Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS
On 08. 04. 19 16:17, Alan Tull wrote:
> On Mon, Apr 8, 2019 at 7:39 AM Nava kishore Manne wrote:
>>
>> Hi Alan,
>>
>> Thanks for look into it and providing the ACK.
>> I got one minor comments from Moritz Fischer do you want me fix that issue
>> now or I can fix it later as it’s a minor comment?
While validating new map we require the @start_data to be strictly less
than @end_data, which is fine for regular applications (this is why this
nit didn't trigger for that long). These members are set from executable
loaders such as elf halders, still it is pretty valid to have a loadable
data
Hello everyone,
On Mon, Apr 08, 2019 at 02:32:08PM +0200, Gavin Schenk wrote:
> Due to new challenges in my life I can no longer take care of SIOX.
> Thorsten takes over my SIOX tasks.
>
> Signed-off-by: Gavin Schenk
Acked-by: Thorsten Scherer
I will take over Gavin's SIOX tasks.
Best
On Mon, Apr 8, 2019 at 4:29 PM Denys Vlasenko wrote:
>
> On 4/8/19 4:23 PM, Sedat Dilek wrote:
> > For the .rodata.cst16 part you mean sth. like this?
>
> yes, see below
>
> > --- a/arch/x86/crypto/camellia-aesni-avx-asm_64.S
> > +++ b/arch/x86/crypto/camellia-aesni-avx-asm_64.S
> > @@ -573,8
Hi Bjorn,
Thanks for reviewing!
On 4/5/19 17:57, Bjorn Andersson wrote:
> On Fri 05 Apr 10:54 +07 2019, Georgi Djakov wrote:
> [..]
>> diff --git a/drivers/interconnect/qcom/qcs404.c
>> b/drivers/interconnect/qcom/qcs404.c
>> new file mode 100644
>> index ..42d36db13ec0
>> ---
Commit-ID: 67e87d43b794a8886b5d075b3e0fdd0c615a595f
Gitweb: https://git.kernel.org/tip/67e87d43b794a8886b5d075b3e0fdd0c615a595f
Author: Borislav Petkov
AuthorDate: Fri, 29 Mar 2019 19:52:59 +0100
Committer: Borislav Petkov
CommitDate: Mon, 8 Apr 2019 12:13:34 +0200
x86: Convert some
Commit-ID: 28e3ace70c3d2ea47a62dffe046011d1b74ee839
Gitweb: https://git.kernel.org/tip/28e3ace70c3d2ea47a62dffe046011d1b74ee839
Author: Borislav Petkov
AuthorDate: Fri, 29 Mar 2019 20:00:38 +0100
Committer: Borislav Petkov
CommitDate: Mon, 8 Apr 2019 12:14:16 +0200
x86/mm: Convert
On 4/8/19 4:23 PM, Sedat Dilek wrote:
For the .rodata.cst16 part you mean sth. like this?
yes, see below
--- a/arch/x86/crypto/camellia-aesni-avx-asm_64.S
+++ b/arch/x86/crypto/camellia-aesni-avx-asm_64.S
@@ -573,8 +573,12 @@
Commit-ID: bfdd5a67c8cb02c147c6b012543e84cb1f5759ba
Gitweb: https://git.kernel.org/tip/bfdd5a67c8cb02c147c6b012543e84cb1f5759ba
Author: Borislav Petkov
AuthorDate: Fri, 29 Mar 2019 19:35:24 +0100
Committer: Borislav Petkov
CommitDate: Mon, 8 Apr 2019 12:02:55 +0200
x86/asm: Clarify
On Mon, 8 Apr 2019 15:57:07 +0200
Daniel Bristot de Oliveira wrote:
> > Just to remove confusion. Your example is to show that the new
> > tracepoints would have shown that the NMI was long due to the printk? As
> > running printk from NMI (even with the delayed output) isn't a normal
> > path.
On Mon, Apr 8, 2019 at 3:58 PM Denys Vlasenko wrote:
>
> On 4/8/19 3:56 PM, Denys Vlasenko wrote:
> > I propose to change section name, append _module_ name and optionally
> > a comment why this is done:
> >
> > /* NB: section is mergeable, all elements must be aligned 16-byte blocks
> > */
>
Jessica? ping?
P.
On 4/2/19 9:39 AM, Prarit Bhargava wrote:
> Microsoft HyperV disables the X86_FEATURE_SMCA bit on AMD systems, and
> linux guests boot with repeated errors:
>
> amd64_edac_mod: Unknown symbol amd_unregister_ecc_decoder (err -2)
> amd64_edac_mod: Unknown symbol
On Mon, Apr 8, 2019 at 7:39 AM Nava kishore Manne wrote:
>
> Hi Alan,
>
> Thanks for look into it and providing the ACK.
> I got one minor comments from Moritz Fischer do you want me fix that issue
> now or I can fix it later as it’s a minor comment?
Please fix for Moritz comment.
> In which
On Mon, 8 Apr 2019, Andrea Parri wrote:
> > > > > I'd have:
> > > > >
> > > > > *x = 1; /* A */
> > > > > smp_mb__before_atomic();
> > > > > r0 = xchg_relaxed(x, 2); /* B (read or write part) */
> > > > >
> > > > > => (A ->barrier B)
> > > >
> > > > Perhaps so. It
On Mon 2019-04-01 22:51:58, Kimberly Brown wrote:
> The kobj_type default_attrs field is being replaced by the
> default_groups field. Replace klp_ktype_patch's default_attrs field
> with default_groups and use the ATTRIBUTE_GROUPS macro to create
> klp_patch_groups.
>
> This patch was tested by
Ping
On 3/26/19 10:57 AM, Suthikulpanit, Suravee wrote:
> Only clear the valid bit when invalidate logical APIC id entry.
> The current logic clear the valid bit, but also set the rest of
> the bits (including reserved bits) to 1.
>
> Fixes: 98d90582be2e ('svm: Fix AVIC DFR and LDR handling')
>
Ping
On 3/20/19 3:12 PM, Suthikulpanit, Suravee wrote:
> This reverts commit bb218fbcfaaa3b115d4cd7a43c0ca164f3a96e57.
>
> As Oren Twaig pointed out the old discussion:
>
>https://patchwork.kernel.org/patch/8292231/
>
> that the change coud potentially cause an extra IPI to be sent to
>
On Mon, Apr 08, 2019 at 10:37:45AM +0800, Huang Shijie wrote:
> When CONFIG_HAVE_GENERIC_GUP is defined, the kernel will use its own
> get_user_pages_fast().
>
> In the following scenario, we will may meet the bug in the DMA case:
> .
>
From: Yazen Ghannam
Current AMD systems have unique MCA banks per logical CPU even though
the type of the banks may all align to the same bank number. Each CPU
will have control of a set of MCA banks in the hardware and these are
not shared with other CPUs.
For example, bank 0 may be the
On Sun, Apr 7, 2019 at 7:03 PM Andrew Jeffery wrote:
>
>
>
> On Fri, 5 Apr 2019, at 01:55, Patrick Venture wrote:
> > Document the ast2400, ast2500 PCI-to-AHB bridge control driver bindings.
> >
> > Signed-off-by: Patrick Venture
> > Reviewed-by: Rob Herring
> > ---
> > Changes for v9:
> > -
From: Yazen Ghannam
The struct mce_banks[] array is only used in mce/core.c so move the
definition of struct mce_bank to mce/core.c and make the array static.
Also, change the "init" field to bool type.
Signed-off-by: Yazen Ghannam
---
arch/x86/kernel/cpu/mce/core.c | 11 ++-
From: Yazen Ghannam
The OS is expected to write all bits in MCA_CTL. However, only
implemented bits get set in the hardware.
Read back MCA_CTL so that the value in the hardware is saved and
reported through sysfs.
Signed-off-by: Yazen Ghannam
---
arch/x86/kernel/cpu/mce/core.c | 15
From: Yazen Ghannam
The number of MCA banks is provided per logical CPU. Historically, this
number has been the same across all CPUs, but this is not an
architectural guarantee. Future AMD systems may have MCA bank counts
that vary between logical CPUs in a system.
This issue was partially
From: Yazen Ghannam
The focus of this patchset is define and use the MCA bank structures
and bank count per logical CPU.
With the exception of patch 4, this set applies to systems in production
today.
Patch 1:
Moves the declaration of struct mce_banks[] to the only file it's used.
Patch 2:
From: Yazen Ghannam
On legacy systems, the addresses of the MCA_MISC* registers need to be
recursively discovered based on a Block Pointer field in the registers.
On Scalable MCA systems, the register space is fixed, and particular
addresses can be derived by regular offsets for bank and
On 4/4/19 7:58 PM, Tobin C. Harding wrote:
Hi Shua,
Here is the set with cleanup as suggested by Kees on v3.
Configured, built, and tested all modules loaded by
tools/testing/selftests/lib/*.sh
From previous cover letters ...
While doing the testing for strscpy_pad() it was noticed that
On Mon, Apr 08, 2019 at 11:51:16AM +0100, Suzuki K Poulose wrote:
> On 04/06/2019 12:21 PM, Leo Yan wrote:
> > Following the same fashion with replicator DT binding, this patch is to
> > unify the DT binding for funnel to support static and dynamic modes;
> > finally we get the funnel DT binding
On Mon, Apr 8, 2019 at 8:58 AM Antonio Ospite wrote:
> On Sun, 7 Apr 2019 16:07:41 +0200
> Alexandre Belloni wrote:
> adding Robert to CC as he is listed as the current maintainer of
> ARM/EZX SMARTPHONES in the MAINTAINERS file.
>
> > I've had a look at the PCAP RTC driver because I'm removing
Hi Suzuki,
On Mon, Apr 08, 2019 at 11:44:56AM +0100, Suzuki K Poulose wrote:
> On 04/06/2019 12:21 PM, Leo Yan wrote:
> > CoreSight uses below bindings for replicator:
> >
> >Static replicator, aka. non-configurable replicator:
> > "arm,coresight-replicator";
> >
> >Dynamic
On 08/04/2019 15:22:50+0200, Daniel Lezcano wrote:
> On 08/04/2019 14:42, Alexandre Belloni wrote:
> > On 08/04/2019 14:35:05+0200, Daniel Lezcano wrote:
> >>
> >> What about commit 51f0aeb2d21f1 ?
> >>
> >
> > Well, do you see anything parsing that in drivers/clocksource ?
>
> So to make it
On Mon, Apr 8, 2019 at 2:46 PM Christoph Hellwig wrote:
>
> I just stumbled over the MAP_UNINITIALIZED defintion, initially
> added by:
>
> commit ea637639591def87a54cea811cbac796980cb30d
> Author: Jie Zhang
> Date: Mon Dec 14 18:00:02 2009 -0800
>
> nommu: fix malloc performance by adding
On 4/8/19 3:56 PM, Denys Vlasenko wrote:
I propose to change section name, append _module_ name and optionally
a comment why this is done:
/* NB: section is mergeable, all elements must be aligned 16-byte blocks */
+/* There is more than one object in this section, let's use module name
+
On 4/8/19 3:46 PM, Steven Rostedt wrote:
> On Mon, 8 Apr 2019 14:24:47 +0200
> Daniel Bristot de Oliveira wrote:
>
>> NMI starts:
>> f-4447 [000] d.Z. 1487.689290: nmi_entry: vector=2
>> f-4447 [000] d.Z. 1487.689291: default_do_nmi <-do_nmi
>> f-4447 [000] d.Z. 1487.689291:
On 4/8/19 3:36 PM, Sedat Dilek wrote:
I fell over your commit "crypto: x86 - make constants readonly, allow
linker to merge them" [1] while digging into ClangBuiltLinux issue 431
[0].
I see the following in my dmesg-log:
$ grep sysfs: dmesg_5.0.4-rc1-1-amd64-cbl-asmgoto.txt
[Fri Mar 22
On 4/8/19 8:51 AM, Bartosz Golaszewski wrote:
pon., 8 kwi 2019 o 15:47 David Lechner napisał(a):
On 4/8/19 2:59 AM, Bartosz Golaszewski wrote:
From: David Lechner
This adds a cpu node and operating points to the common da850.dtsi file.
Additionally, a regulator is added to the LEGO EV3
On 08/04/2019 15:49, Bartosz Golaszewski wrote:
> wt., 2 kwi 2019 o 11:21 Daniel Lezcano napisał(a):
>>
>> On 18/03/2019 13:10, Bartosz Golaszewski wrote:
>>> From: Bartosz Golaszewski
>>>
>>> Currently the clocksource and clockevent support for davinci platforms
>>> lives in mach-davinci. It
pon., 8 kwi 2019 o 15:47 David Lechner napisał(a):
>
> On 4/8/19 2:59 AM, Bartosz Golaszewski wrote:
> > From: David Lechner
> >
> > This adds a cpu node and operating points to the common da850.dtsi file.
> >
> > Additionally, a regulator is added to the LEGO EV3 board along with
> > some
Some definitions of Inner Cacheability attibutes need to be corrected.
Fixes: 8c828a535e29f ("irqchip/gicv3-its: Restore all cacheability
attributes")
Signed-off-by: Hongbo Yao
---
include/linux/irqchip/arm-gic-v3.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
wt., 2 kwi 2019 o 11:21 Daniel Lezcano napisał(a):
>
> On 18/03/2019 13:10, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski
> >
> > Currently the clocksource and clockevent support for davinci platforms
> > lives in mach-davinci. It hard-codes many things, uses global variables,
> >
On 4/8/19 2:59 AM, Bartosz Golaszewski wrote:
From: David Lechner
This adds a cpu node and operating points to the common da850.dtsi file.
Additionally, a regulator is added to the LEGO EV3 board along with
some board-specific CPU configuration.
Regulators need to be hooked up on other
On Mon, 8 Apr 2019 14:24:47 +0200
Daniel Bristot de Oliveira wrote:
> NMI starts:
> f-4447 [000] d.Z. 1487.689290: nmi_entry: vector=2
> f-4447 [000] d.Z. 1487.689291: default_do_nmi <-do_nmi
> f-4447 [000] d.Z. 1487.689291: nmi_handle <-default_do_nmi
> f-4447 [000] d.Z.
From: Vladimir Murzin
Some definitions of Inner Cacheability attibutes need to be corrected.
Fixes: 8c828a535e29f ("irqchip/gicv3-its: Restore all cacheability
attributes")
Signed-off-by: Hongbo Yao
---
include/linux/irqchip/arm-gic-v3.h | 12 ++--
1 file changed, 6 insertions(+), 6
Hi Denys,
I fell over your commit "crypto: x86 - make constants readonly, allow
linker to merge them" [1] while digging into ClangBuiltLinux issue 431
[0].
I see the following in my dmesg-log:
$ grep sysfs: dmesg_5.0.4-rc1-1-amd64-cbl-asmgoto.txt
[Fri Mar 22 10:32:09 2019] sysfs: cannot create
On Sun, Mar 31, 2019 at 06:14:01PM +0530, Mukesh Ojha wrote:
>
> On 3/31/2019 3:51 AM, Nishad Kamdar wrote:
> > This patch corrects the SPDX License Identifier style
> > in the Hardware Architecture subsystem. For C header files
> > Documentation/process/license-rules.rst mandates C-like comments
On Mon, Apr 8, 2019 at 2:41 AM Pavel Machek wrote:
>
> Hi!
>
> > > > > > This document also states "The naming scheme above leaves scope
> > > > > > for further attributes should they be needed". It does not permit,
> > > > > > however, to redefine one of the fields to mean "location", much less
Hello Greg,
On Mon, Apr 08, 2019 at 02:32:08PM +0200, Gavin Schenk wrote:
> Due to new challenges in my life I can no longer take care of SIOX.
> Thorsten takes over my SIOX tasks.
>
> Signed-off-by: Gavin Schenk
Acked-by: Uwe Kleine-König
I assume it will be you who picks up this patch? I
> On Mon, Apr 08, 2019 at 09:13:58AM +0300, Elena Reshetova wrote:
> > diff --git a/arch/x86/entry/common.c b/arch/x86/entry/common.c
> > index 7bc105f47d21..38ddc213a5e9 100644
> > --- a/arch/x86/entry/common.c
> > +++ b/arch/x86/entry/common.c
> > @@ -35,6 +35,12 @@
> > #define
On Sun, Mar 31, 2019 at 01:41:26AM -0500, Rob Herring wrote:
> On Sat, Mar 23, 2019 at 06:58:14PM +0530, Nishad Kamdar wrote:
> > This patch corrects the SPDX License Identifier style
> > in the Hardware Architecture subsystem.
> >
> > Changes made by using a script provided by Joe Perches here:
On Mon, Apr 8, 2019 at 8:05 PM Arnaud Pouliquen wrote:
>
>
>
> On 4/6/19 9:56 AM, xiang xiao wrote:
> > On Sat, Apr 6, 2019 at 12:08 AM Arnaud Pouliquen
> > wrote:
> >>
> >>
> >>
> >> On 4/5/19 4:03 PM, xiang xiao wrote:
> >>> On Fri, Apr 5, 2019 at 8:33 PM Arnaud Pouliquen
> >>> wrote:
>
On 4/8/19 11:50 AM, Peter Zijlstra wrote:
> On Mon, Apr 08, 2019 at 10:22:29AM +0200, Peter Zijlstra wrote:
>> On Mon, Apr 08, 2019 at 09:12:28AM +0200, Thomas-Mich Richter wrote:
>
>>> very good news, your fix ran over the weekend without any hit!!!
>>>
>>> Thanks very much for your help. Do you
On Mon, Apr 08, 2019 at 12:36:32PM +0200, Thomas Huth wrote:
> On 08/04/2019 09.09, David Hildenbrand wrote:
> > On 07.04.19 14:55, Thomas Huth wrote:
> >> If CONFIG_PGSTE is not set (e.g. when compiling without KVM), GCC
> >> complains:
> >>
> >> CC arch/s390/mm/pgtable.o
> >>
Hi Eugeniy,
From: Eugeniy Paltsev
Date: Mon, Apr 08, 2019 at 12:40:00
> Hi Vitor,
>
> On Mon, 2019-04-08 at 12:31 +0200, Vitor Soares wrote:
> > Some custom IP-block connected to ARC AXS10x board need assert and
> > deassert functions to control reset signal of selected peripherals.
> >
> >
On 08/04/2019 14:42, Alexandre Belloni wrote:
> On 08/04/2019 14:35:05+0200, Daniel Lezcano wrote:
>>
>> What about commit 51f0aeb2d21f1 ?
>>
>
> Well, do you see anything parsing that in drivers/clocksource ?
So to make it clear:
1. You say I said anything, emphasis this word in the previous
On Sun, 2019-04-07 at 19:35 -1000, Linus Torvalds wrote:
> On Sat, Apr 6, 2019 at 12:59 PM Qian Cai wrote:
> >
> > The commit 510ded33e075 ("slab: implement slab_root_caches list")
> > changes the name of the list node within "struct kmem_cache" from
> > "list" to "root_caches_node", but
On 03/30, Jann Horn wrote:
>
> --- a/kernel/signal.c
> +++ b/kernel/signal.c
> @@ -3605,16 +3605,11 @@ SYSCALL_DEFINE4(pidfd_send_signal, int, pidfd, int,
> sig,
> if (unlikely(sig != kinfo.si_signo))
> goto err;
>
> + /* Only allow sending
Hi, Aisheng
Best Regards!
Anson Huang
> -Original Message-
> From: Aisheng Dong
> Sent: 2019年4月8日 18:35
> To: Anson Huang ; robh...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; s.ha...@pengutronix.de;
> ker...@pengutronix.de; feste...@gmail.com; a.zu...@towertech.it;
>
On Mon, Apr 8, 2019 at 2:26 PM Pascal PAILLET-LME wrote:
> > I hope you are not trying to work around a bug in the driver by
> > stripping out DMA configuration from the device tree, because then
> > it is probably a better idea to fix the bug.
> This is not a workaround. The PMIC can use the
On Mon, Apr 08, 2019 at 09:20:50AM +, David Laight wrote:
> From: Josh Poimboeuf
> > Sent: 05 April 2019 18:23
> > On Fri, Apr 05, 2019 at 05:17:15PM +, David Laight wrote:
> > > > Hm, I don't see that in cmd_objtool, or any commits from you in
> > > > scripts/Makefile.build.
> > >
> > >
On 8/4/19 13:29, Enric Balletbo i Serra wrote:
> Hi Tim,
>
> Many thanks for sending this patch upstream, some comments below
>
> On 27/3/19 19:20, Tim Wawrzynczak wrote:
>> The new debugfs entry 'uptime' is being made available to userspace so that
>> a userspace daemon can synchronize EC
On Mon, Apr 08, 2019 at 01:54:06PM +0200, Alexandre Belloni wrote:
> On 08/04/2019 12:22:49+0200, Thierry Reding wrote:
> > On Sun, Apr 07, 2019 at 11:16:44PM +0200, Alexandre Belloni wrote:
> > > The Tegra 20 RTC is a 32bit seconds counter (with an unused millisecond
> > > counter).
> > >
> > >
On 4/4/19 7:40 PM, Joel Fernandes wrote:
>> Currently, recursion control uses the preempt_counter to
>> identify the current context. The NMI/HARD/SOFT IRQ counters
>> are set in the preempt_counter in the irq_enter/exit functions.
> Just started looking.
>
> Thinking out loud... can we not just
Assalamualaikum My Dear Friend,
Before I introduce myself, I wish to inform you that this letter is
not a hoax mail and I urge you to treat it serious. This letter must
come to you as a big surprise, but I believe it is only a day that
people meet and become great friends and business partners.
On Mon, Apr 08, 2019 at 03:43:48PM +0300, Andy Shevchenko wrote:
> On Mon, Apr 08, 2019 at 06:49:26PM +0800, Binbin Wu wrote:
> > In current driver, SET_LATE_SYSTEM_SLEEP_PM_OPS is used to install the
> > callbacks for suspend/resume.
> > GPIO pin may be used as the interrupt pin by some device.
On Mon, Apr 08, 2019 at 09:13:58AM +0300, Elena Reshetova wrote:
> diff --git a/arch/x86/entry/common.c b/arch/x86/entry/common.c
> index 7bc105f47d21..38ddc213a5e9 100644
> --- a/arch/x86/entry/common.c
> +++ b/arch/x86/entry/common.c
> @@ -35,6 +35,12 @@
> #define CREATE_TRACE_POINTS
>
On 4/4/19 2:01 AM, Andy Lutomirski wrote:
>> To resolve this problem, the set/unset of the IRQ/NMI context needs to
>> be done before the execution of the first C execution, and after its
>> return. By doing so, and using this method to identify the context in the
>> trace recursion protection, no
I just stumbled over the MAP_UNINITIALIZED defintion, initially
added by:
commit ea637639591def87a54cea811cbac796980cb30d
Author: Jie Zhang
Date: Mon Dec 14 18:00:02 2009 -0800
nommu: fix malloc performance by adding uninitialized flag
The defintion depends on
On Thu, Apr 4, 2019 at 3:16 PM Singh, Sandeep wrote:
> From: Sandeep Singh
>
> Some of the AMD reference boards used single GPIO line for
> multiple devices. So added IRQF_SHARED flag in amd pinctrl driver.
>
>
> Signed-off-by: Sandeep Singh
> Signed-off-by: Shyam Sundar S K
> cc: Nehal Shah
On 08/04/2019 14:35:05+0200, Daniel Lezcano wrote:
>
> What about commit 51f0aeb2d21f1 ?
>
Well, do you see anything parsing that in drivers/clocksource ?
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Mon, Apr 08, 2019 at 06:49:26PM +0800, Binbin Wu wrote:
> In current driver, SET_LATE_SYSTEM_SLEEP_PM_OPS is used to install the
> callbacks for suspend/resume.
> GPIO pin may be used as the interrupt pin by some device. However, using
> SET_LATE_SYSTEM_SLEEP_PM_OPS() to install the callbacks,
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