for your effort on this. Can you share your config?
>
> attached (but its s390x) for next-20210330
Thanks. Can you apply the following patch and help me test?
Very Thanks.
diff --git a/include/linux/memcontrol.h b/include/linux/memcontrol.h
index 7fdc92e1983e..579408e4d46f 100644
--- a/in
30.03.2021 17:19, Yicong Yang пишет:
...
> +struct hisi_i2c_controller {
> + struct i2c_adapter adapter;
> + void __iomem *iobase;
> + struct device *dev;
> + int irq;
> +
> + /* Intermediates for recording the transfer process */
> + struct completion *completion;
> +
On Tue, Mar 30, 2021 at 11:30 AM Mark Brown wrote:
>10.22.8.121
> On Tue, Mar 30, 2021 at 10:08:16AM -0500, Rob Herring wrote:
> > On Fri, Mar 26, 2021 at 03:18:59PM -0400, Jim Quinlan wrote:
>
> > > +pcie-ep@0,0 {
> > > +reg = <0x0 0x0 0x0 0x0
Hi,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.12-rc5]
[cannot apply to hnaz-linux-mm/master next-20210330]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
Hi Sahil,
Am 2021-03-30 16:42, schrieb Sahil Malhotra:
I tried the same on LS1028A-RDB board with 5.11 kernel and my
submitted patch applied.
Board booted up successfully: https://pastebin.com/15D91K5k
I used OP-TEE from OP-TEE github repo:
https://github.com/OP-TEE/optee_os with commit
On Tue, Mar 30, 2021 at 5:01 PM David Hildenbrand wrote:
> >> +long faultin_vma_page_range(struct vm_area_struct *vma, unsigned long
> >> start,
> >> + unsigned long end, bool write, int *locked)
> >> +{
> >> + struct mm_struct *mm = vma->vm_mm;
> >> +
Reviewed-by: Christian König for the entire
series.
Alex will probably pick them up for the next feature pull request.
Regards,
Christian.
Am 30.03.21 um 17:33 schrieb Xℹ Ruoyao:
In AMDGPU driver, the bo mapping should always align to CPU page or
the page table is corrupted.
The first
On Mon, 2021-03-15 at 10:16 -0700, Sagi Grimberg wrote:
> > Hi Sagi,
> >
> > On Fri, Mar 05, 2021 at 11:57:30AM -0800, Sagi Grimberg wrote:
> > > Daniel, again, there is nothing specific about this to nvme-tcp,
> > > this is a safeguard against a funky controller (or a different
> > > bug that is
Change from using device tree (Open Firmware) APIs to the unified
'fwnode' interface.
Change of_nvmem_cell_get() to fwnode_nvmem_cell_get(), and add a
wrapper for of_nvmem_cell_get().
Change of_nvmem_device_get() to fwnode_nvmem_device_get(). There
are no known accessors to the OF interface, so
nvmem: Change to unified property interface
Change from using device tree (Open Firmware) APIs to the unified
'fwnode' interface.
Change of_nvmem_cell_get() to fwnode_nvmem_cell_get(), and add a
wrapper for of_nvmem_cell_get().
Change of_nvmem_device_get() to fwnode_nvmem_device_get(). There
On Wed, Mar 31, 2021 at 12:15:37AM +1030, Joel Stanley wrote:
> overlayfs using jffs2 as the upper filesystem would fail in some cases
> since moving to v5.10. The test case used was to run 'touch' on a file
> that exists in the lower fs, causing the modification time to be
> updated. It returns
Hi Richard,
On Tue, Mar 30, 2021 at 09:33:05AM -0500, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Extend Intel service layer driver to get the firmware version running at
> FPGA device. Therefore FPGA manager driver, one of Intel service layer
> driver's client, can decide
Hi!
On 2021-03-26 18:24, Andy Shevchenko wrote:
> Use already prepared dev_err_probe() introduced by the commit
> a787e5400a1c ("driver core: add device probe log helper").
> It simplifies EPROBE_DEFER handling.
>
> Signed-off-by: Andy Shevchenko
> ---
> drivers/mux/gpio.c | 8 ++--
> 1
On Mon, Mar 29, 2021 at 9:56 PM Zhou Yanjie wrote:
>
> On 2021/3/29 上午10:48, Ilya Lipnitskiy wrote:
> >
> > Try:
> > diff --git a/mm/memory.c b/mm/memory.c
> > index c8e357627318..1fd753245369 100644
> > --- a/mm/memory.c
> > +++ b/mm/memory.c
> > @@ -166,7 +166,7 @@ static int __init
Hi!
On 2021-03-26 18:24, Andy Shevchenko wrote:
> Module doesn't use OF APIs anyhow, make it OF independent by replacing
> headers and dropping useless of_match_ptr() call.
>
> Signed-off-by: Andy Shevchenko
> ---
> drivers/mux/gpio.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Hi!
On 2021-03-26 18:23, Andy Shevchenko wrote:
> Assigning bitmaps like it's done in the driver might be error prone.
> Fix this by using bitmap API.
A bit strongly worded perhaps, since the size of a mux chip with
anywhere near 31 inputs and 2^31 possible selections is a bit
ridiculous. Please
On Tue, Mar 30, 2021 at 11:13:55AM +0800, Guo Ren wrote:
> On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra wrote:
> >
> > On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote:
> > > u32 a = 0x55aa66bb;
> > > u16 *ptr =
> > >
> > > CPU0 CPU1
> > > =
On Tue, 30 Mar 2021 09:47:10 +0100, Colin King wrote:
> There is a spelling mistake in a dev_err error message. Fix it.
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[1/1] ASoC: mediatek: mt6359: Fix spelling mistake "reate" -> "create"
On Tue, Mar 30, 2021 at 8:47 AM Jason Gunthorpe wrote:
>
> On Tue, Mar 30, 2021 at 08:37:19AM -0700, Dan Williams wrote:
> > On Tue, Mar 30, 2021 at 4:16 AM Jason Gunthorpe wrote:
> > >
> > > On Mon, Mar 29, 2021 at 07:47:49PM -0700, Dan Williams wrote:
> > >
> > > > @@ -1155,21 +1175,12 @@
On Fri, 26 Mar 2021 13:50:03 -0600, Rob Herring wrote:
> The nvidia,tegra210-ahub binding is missing schema for child nodes. This
> results in warnings if 'additionalProperties: false' is set (or when the
> tools implement 'unevaluatedProperties' support). Add the child nodes
> and reference their
On 3/30/2021 2:01 AM, Lv Yunlong wrote:
In the first list_for_each_entry() macro of dma_async_device_register,
it gets the chan from list and calls __dma_async_device_channel_register
(..,chan). We can see that chan->local is allocated by alloc_percpu() and
it is freed chan->local by
On Tue, Mar 30, 2021 at 8:31 AM Will Deacon wrote:
>
> On Tue, Mar 30, 2021 at 08:03:36AM -0700, Rob Clark wrote:
> > On Tue, Mar 30, 2021 at 2:34 AM Will Deacon wrote:
> > >
> > > On Mon, Mar 29, 2021 at 09:02:50PM -0700, Rob Clark wrote:
> > > > On Mon, Mar 29, 2021 at 7:47 AM Will Deacon
On Mon, Mar 29, 2021 at 10:47:52PM -0700, Eric Biggers wrote:
> > Isn't this a user problem? If the modules required to boot are on the
> > filesystem itself, you are in trouble. But, if that is the case, your
> > rootfs is case-insensitive and you gotta have utf8 as built-in or have
> > it in
The pull request you sent on Tue, 30 Mar 2021 15:02:19 +0200:
> git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/
> tags/mips-fixes_5.12_3
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/2bb25b3a748af6f11df42298e80b9863ed23f2b3
Thank you!
--
The pull request you sent on Tue, 30 Mar 2021 14:03:37 +0200:
> git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git
> for-linus-5.12b-rc6-tag
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/a080642d2f831cc34b68663c0db1c447d3807421
Thank you!
--
Deet-doot-dot,
30.03.2021 18:29, Dmitry Osipenko пишет:
> 30.03.2021 11:48, Krzysztof Kozlowski пишет:
>>> + power-domains:
>>> +$ref: /schemas/types.yaml#/definitions/phandle
>>> +description:
>>> + Phandle of the SoC "core" power domain.
>> I think the core checks the type, so you only need to
From: Tamar Mashiah
The manufacturing access to the PCH/SOC SPI device is traditionally
performed via user space driver accessing registers via /dev/mem
but due to security concerns /dev/mem access is being much restricted,
hence the reason for utilizing dedicated Intel PCH/SOC SPI controller
On 3/30/21 5:31 PM, Andrey Konovalov wrote:
> My commit "integrate page_alloc init with HW_TAGS" changed the order of
> kernel_unpoison_pages() and kernel_init_free_pages() calls. This leads
> to __GFP_ZERO allocations being incorrectly poisoned when page poisoning
> is enabled.
Correction: This
DPI can sample on falling, rising or both edge.
When DPI sample the data both rising and falling edge.
It can reduce half data io pins.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 12
1 file changed, 12 insertions(+)
diff --git
Add the atomic_get_output_bus_fmts, atomic_get_input_bus_fmts to negociate
the possible output and input formats for the current mode and monitor,
and use the negotiated formats in a basic atomic_check callback.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 96
DPI can sample on falling, rising or both edge.
When DPI sample the data both rising and falling edge.
It can reduce half data io pins.
Jitao Shi (3):
drm/mediatek: dpi dual edge sample mode support
drm/mediatek: config mt8183 driver data to support dual edge sample
drm/mediatek: dpi: add
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ccd681a2a4c2..87bb27649c4c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++
Fix the following out-of-bounds warnings by enclosing
structure members file and finder into new struct info:
fs/hfsplus/xattr.c:300:5: warning: 'memcpy' offset [65, 80] from the object at
'entry' is out of the bounds of referenced subobject 'user_info' with type
'struct DInfo' at offset 48
Hi,
On Tue, Mar 30, 2021 at 05:09:42PM +0200, Rafael J. Wysocki wrote:
> On 3/29/2021 9:52 PM, Angela Czubak wrote:
> > Do not overwrite flags as it leads to erasing triggering and polarity
> > information which might be useful in case of hard-coded interrupts.
> > This way the information can be
On Tue, Mar 30, 2021 at 12:07:35PM +0300, Heikki Krogerus wrote:
> On Mon, Mar 29, 2021 at 02:49:46PM -0400, Alan Stern wrote:
> > On Mon, Mar 29, 2021 at 11:44:25AM +0300, Heikki Krogerus wrote:
> > > Introducing usb_for_each_port(). It works the same way as
> > > usb_for_each_dev(), but instead
On 2021-03-30 15:24 +0200, Christian König wrote:
> Am 30.03.21 um 15:23 schrieb Dan Horák:
> > On Tue, 30 Mar 2021 21:09:12 +0800
> > Xi Ruoyao wrote:
> >
> > > On 2021-03-30 21:02 +0800, Xi Ruoyao wrote:
> > > > On 2021-03-30 14:55 +0200, Christian König wrote:
> > > > > I rather see this as a
On Tue, Mar 30, 2021 at 08:37:19AM -0700, Dan Williams wrote:
> On Tue, Mar 30, 2021 at 4:16 AM Jason Gunthorpe wrote:
> >
> > On Mon, Mar 29, 2021 at 07:47:49PM -0700, Dan Williams wrote:
> >
> > > @@ -1155,21 +1175,12 @@ static void cxlmdev_unregister(void *_cxlmd)
> > > struct cxl_memdev
Em Fri, Feb 26, 2021 at 02:52:23AM -0500, Fabian Hemmer escreveu:
> Some OCaml developers reported that this bit of information is sometimes
> useful for disambiguating functions for which the OCaml compiler assigns
> the same name, e.g. nested or inlined functions.
Sorry for the delay in
On 2021-03-30 16:32:10, Aneesh Kumar K.V wrote:
> Tyler Hicks writes:
>
> > The alignment constraint for namespace creation in a region was
> > increased, from 2M to 16M, for non-PowerPC architectures in v5.7 with
> > commit 2522afb86a8c ("libnvdimm/region: Introduce an 'align'
> > attribute").
Hi David,
On 3/30/21 9:19 AM, David Laight wrote:
From: richard.g...@linux.intel.com
Sent: 30 March 2021 15:33
Extend Intel service layer driver to get the firmware version running at
FPGA device. Therefore FPGA manager driver, one of Intel service layer
driver's client, can decide whether
Em Tue, Mar 30, 2021 at 09:41:33AM +0200, Martin Liška escreveu:
> PING^2
>
> On 3/7/21 8:23 PM, Martin Liška wrote:
> > Hello.
> >
> > May I please remind this patch. Apparently, you applied the perf-config
> > counterpart of the patch as 804fd30c6bd9aec7859a0503581312834fb197f1
> > (in
On Wed, Feb 10, 2021 at 01:44:34PM +0200, Tudor Ambarus wrote:
> This is a follow-up for:
> commit 3c9ea42802a1 ("clk: Mark fwnodes when their clock provider is
> added/removed")
>
> The above commit updated the deprecated of_clk_add_provider(),
> but missed to update the preferred
Commit f211ac154577ec9ccf07c15f18a6abf0d9bdb4ab 'net: correct
sk_acceptq_is_full()' breaks a system with the Smack LSM.
Reverting this change results in a return to correct behavior.
The Smack testsuite can be found at:
https://github.com/smack-team/smack-testsuite.git
The failing test
Hi Andy,
> I would like to look at it closer, but don't have time right now. So,
> some kind of a shallow review.
Still, thanks for that!
> But the idea is, let's say, interesting.
:)
> > +The binding documentation is in the ``misc`` folder of the Kernel binding
> > +documentation.
>
> Can't
On Tue, Mar 30, 2021 at 10:14 AM Lecopzer Chen
wrote:
>
> > Do you know if anybody is working on this? It's really unfortunate that
> > we can't move exclusively to VMAP_STACK just because of SW_TAGS KASAN.
> >
> > That said, what is there to do? As things stand, won't kernel stack
> > addresses
20.03.2021 18:26, Dmitry Osipenko пишет:
> This series fixes couple minor standalone problems of the Tegra clk
> driver.
Hello Stephen,
Do you have any objects if Thierry will take this series into the Tegra
tree?
Or will you be able to take the patches into the clk tree?
Please let us know
On Tue, Mar 30, 2021 at 4:16 AM Jason Gunthorpe wrote:
>
> On Mon, Mar 29, 2021 at 07:47:49PM -0700, Dan Williams wrote:
>
> > @@ -1155,21 +1175,12 @@ static void cxlmdev_unregister(void *_cxlmd)
> > struct cxl_memdev *cxlmd = _cxlmd;
> > struct device *dev = >dev;
> >
> > -
The page table of AMDGPU requires an alignment to CPU page so we should
check ioctl parameters for it. Return -EINVAL if some parameter is
unaligned to CPU page, instead of corrupt the page table sliently.
Signed-off-by: Xi Ruoyao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8
1 file
@syslog_lock was a raw_spin_lock to simplify the transition of
removing @logbuf_lock and the safe buffers. With that transition
complete, and since all uses of @syslog_lock are within sleepable
contexts, @syslog_lock can become a mutex.
Note that until now register_console() would disable
Syslog's SYSLOG_ACTION_READ is supposed to block until the next
syslog record can be read, and then it should read that record.
However, because @syslog_lock is not held between waking up and
reading the record, another reader could read the record first,
thus causing SYSLOG_ACTION_READ to return
On Tue, Mar 30, 2021 at 09:12:11PM +0530, Mukunda,Vijendar wrote:
> On 3/30/21 7:52 PM, Pierre-Louis Bossart wrote:
> > > static const struct acpi_device_id acp3x_audio_acpi_match[] = {
> > > { "AMDI5682", (unsigned long)_5682},
> > > { "AMDI1015", (unsigned long)_1015},
> > > +
Currently the printk safe buffers provide a form of recursion
protection by redirecting to the safe buffers whenever printk() is
recursively called.
In preparation for removal of the safe buffers, provide an alternate
explicit recursion protection. Recursion is limited to 3 levels
per-CPU and
When page poisoning is enabled, it accesses memory that is marked as
poisoned by KASAN, which leas to false-positive KASAN reports.
Suppress the reports by adding KASAN annotations to unpoison_page()
(poison_page() already has them).
Signed-off-by: Andrey Konovalov
---
mm/page_poison.c | 4
Hi,
Here is v2 of a series to remove the safe buffers. v1 can be
found here [0]. The safe buffers are no longer needed because
messages can be stored directly into the log buffer from any
context.
However, the safe buffers also provided a form of recursion
protection. For that reason, explicit
With @logbuf_lock removed, the high level printk functions for
storing messages are lockless. Messages can be stored from any
context, so there is no need for the NMI and safe buffers anymore.
Remove the NMI and safe buffers.
Although the safe buffers are removed, the NMI and safe context
All NMI contexts are handled the same as the safe context: store the
message and defer printing. There is no need to have special NMI
context tracking for this. Using in_nmi() is enough.
Signed-off-by: John Ogness
---
arch/arm/kernel/smp.c | 2 --
arch/powerpc/kexec/crash.c | 3 ---
From: Huacai Chen
In Mesa, dev_info.gart_page_size is used for alignment and it was
set to AMDGPU_GPU_PAGE_SIZE(4KB). However, the page table of AMDGPU
driver requires an alignment on CPU pages. So, for non-4KB page system,
gart_page_size should be max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE).
On Tue, Mar 30, 2021 at 09:23:14AM -0600, Mathieu Poirier wrote:
> On Tue, Mar 30, 2021 at 11:38:18AM +0100, Suzuki K Poulose wrote:
> > On 26/03/2021 16:55, Mathieu Poirier wrote:
> > > On Tue, Mar 23, 2021 at 12:06:35PM +, Suzuki K Poulose wrote:
> > > > For a nvhe host, the EL2 must allow
On Tue, 30 Mar 2021 16:23:14 +0100,
Mathieu Poirier wrote:
>
> On Tue, Mar 30, 2021 at 11:38:18AM +0100, Suzuki K Poulose wrote:
> > On 26/03/2021 16:55, Mathieu Poirier wrote:
> > > On Tue, Mar 23, 2021 at 12:06:35PM +, Suzuki K Poulose wrote:
> > > > For a nvhe host, the EL2 must allow the
30.03.2021 11:48, Krzysztof Kozlowski пишет:
>> + "^emc-tables@[a-z0-9\\-]+$":
> Why \ and - in the pattern?
Good catch, I thought that '-' needs to be escaped, but then forgot to
remove the unnecessary slashes.
In AMDGPU driver, the bo mapping should always align to CPU page or
the page table is corrupted.
The first patch is cherry-picked from Loongson community, which sets a
suitable dev_info.gart_page_size so Mesa will handle the alignment
correctly.
The second patch is added to ensure an ioctl with
Am Tue, 30 Mar 2021 15:41:53 +0300
schrieb Andy Shevchenko :
> On Tue, Mar 30, 2021 at 3:35 PM Henning Schild
> wrote:
> > Am Tue, 30 Mar 2021 15:15:16 +0300
> > schrieb Andy Shevchenko :
> > > On Tue, Mar 30, 2021 at 2:58 PM Henning Schild
> > > wrote:
> > > > Am Tue, 30 Mar 2021 14:04:35
30.03.2021 11:48, Krzysztof Kozlowski пишет:
>> + nvidia,use-ram-code:
>> +type: boolean
>> +description:
>> + If present, the emc-tables@ sub-nodes will be addressed.
>> +
>> +patternProperties:
>> + "^emc-table@[0-9]+$":
> This might not be easy but you should add constraints when
My commit "integrate page_alloc init with HW_TAGS" changed the order of
kernel_unpoison_pages() and kernel_init_free_pages() calls. This leads
to __GFP_ZERO allocations being incorrectly poisoned when page poisoning
is enabled.
Fix by restoring the initial order. Also add a warning comment.
On Wed, Mar 10, 2021 at 05:08:29PM -0700, Rob Herring wrote:
> From: Raphael Gault
>
> Keep track of event opened with direct access to the hardware counters
> and modify permissions while they are open.
>
> The strategy used here is the same which x86 uses: every time an event
> is mapped, the
On Tue, Mar 30, 2021 at 08:03:36AM -0700, Rob Clark wrote:
> On Tue, Mar 30, 2021 at 2:34 AM Will Deacon wrote:
> >
> > On Mon, Mar 29, 2021 at 09:02:50PM -0700, Rob Clark wrote:
> > > On Mon, Mar 29, 2021 at 7:47 AM Will Deacon wrote:
> > > >
> > > > On Fri, Mar 26, 2021 at 04:13:02PM -0700,
On Wed, Mar 10, 2021 at 05:08:28PM -0700, Rob Herring wrote:
> From: Raphael Gault
>
> In order to be able to access the counter directly for userspace,
> we need to provide the index of the counter using the userpage.
> We thus need to override the event_idx function to retrieve and
> convert
On Tue, Mar 30, 2021 at 10:08:16AM -0500, Rob Herring wrote:
> On Fri, Mar 26, 2021 at 03:18:59PM -0400, Jim Quinlan wrote:
> > +pcie-ep@0,0 {
> > +reg = <0x0 0x0 0x0 0x0 0x0>;
> > +compatible = "pci14e4,1688";
> > +
On Tue, Mar 30, 2021 at 04:11:33PM +0100, Marc Zyngier wrote:
> A long cargo-culted behaviour of PCI drivers is to allocate memory
> to obtain an address that is fed to the controller as the MSI
> capture address (i.e. the MSI doorbell).
>
> But there is no actual requirement for this address to
30.03.2021 11:48, Krzysztof Kozlowski пишет:
>> + power-domains:
>> +$ref: /schemas/types.yaml#/definitions/phandle
>> +description:
>> + Phandle of the SoC "core" power domain.
> I think the core checks the type, so you only need to limit max items.
>
It's a bit confusing that
Hi Dan,
Thank you very much for pointing out the issues.
However, I'm not sure that the code, you have analyzed, will be a part
of final patch set. I intend to redesign all the code deeply, as
Alexandre Belloni suggested [1].
Thank you again!
--
Best Regards,
Kirill Kapranov
Software
Add support for the GPIO controller employed by Realtek in multiple series of
MIPS SoCs. These include the supported RTL838x and RTL839x. The register layout
also matches the one found in the GPIO controller of other (Lexra-based) SoCs
such as RTL8196E, RTL8197D, and RTL8197F.
For the platform
Realtek MIPS SoCs (platform name Otto) have GPIO controllers with up to
64 GPIOs, divided over two banks. Each bank has a set of registers for
32 GPIOs, with support for edge-triggered interrupts.
Each GPIO bank consists of four 8-bit GPIO ports (ABCD and EFGH). Most
registers pack one bit per
Add a binding description for Realtek's GPIO controller found on several
of their MIPS-based SoCs (codenamed Otto), such as the RTL838x and
RTL839x series of switch SoCs.
A fallback binding 'realtek,otto-gpio' is provided for cases where the
actual port ordering is not known yet, and enabling the
Hello,
syzbot found the following issue on:
HEAD commit:93129492 Add linux-next specific files for 20210326
git tree: linux-next
console output: https://syzkaller.appspot.com/x/log.txt?x=169ab21ad0
kernel config: https://syzkaller.appspot.com/x/.config?x=6f2f73285ea94c45
dashboard
30.03.2021 11:37, Krzysztof Kozlowski пишет:
>> +properties:
>> + compatible:
>> +const: nvidia,tegra20-mc-gart
>> +
>> + reg:
>> +minItems: 1
>> +maxItems: 2
> I think you always need two regs, don't you? If so, then better to use
> "description" like in
>
30.03.2021 16:46, Rob Herring пишет:
> On Tue, Mar 30, 2021 at 08:08:43AM -0500, Rob Herring wrote:
>> On Mon, 29 Mar 2021 22:46:00 +0300, Dmitry Osipenko wrote:
>>> Convert Tegra20 Memory Controller binding to schema.
>>>
>>> Signed-off-by: Dmitry Osipenko
>>> ---
>>>
On 29/03/2021 17:47, Christian Hewitt wrote:
> MeCool (Videostrong) KIII Pro is based on the Amlogic Q200 reference
> board with an S912 chip and the following specs:
>
> - 3GB DDR3 RAM
> - 16GB eMMC
> - 10/100/1000 Base-T Ethernet
> - BCM4335 Wireless (802.11 b/g/n/ac, BT 4.0)
> -
On 29/03/2021 17:47, Christian Hewitt wrote:
> MeCool (Videostrong) KII Pro is based on the Amlogic P230 reference
> board with an S905D chip and the following specs:
>
> - 2GB DDR3 RAM
> - 16GB eMMC
> - 10/100 Base-T Ethernet
> - BCM4335 Wireless (802.11 b/g/n/ac, BT 4.0)
> - DVB-C/T/T2/S/S2
On 3/30/21 7:52 PM, Pierre-Louis Bossart wrote:
static const struct acpi_device_id acp3x_audio_acpi_match[] = {
{ "AMDI5682", (unsigned long)_5682},
{ "AMDI1015", (unsigned long)_1015},
+ { "AMDP1015", (unsigned long)_1015p},
This isn't a valid ACPI ID. AMDP does not
The generic PCI host driver relies on MSI domains for MSIs to
be provided to its end-points. Make this dependency explicit.
This cures the warnings occuring on arm/arm64 VMs when booted
with PCI virtio devices and no MSI controller (no GICv3 ITS,
for example).
It is likely that other drivers
On 29/03/2021 18:12, Christian Hewitt wrote:
> From: Hyeonki Hong
>
> Add GPIO line-name identifiers to the ODROID N2/N2+ common dtsi.
>
> Signed-off-by: Hyeonki Hong
> ---
> .../dts/amlogic/meson-g12b-odroid-n2.dtsi | 45 +++
> 1 file changed, 45 insertions(+)
>
> diff
We have now three ways of ending up with NO_MSI being set.
Document them.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/msi.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index
The few quirks that deal with NO_MSI tend to be copy-paste heavy.
Refactor them so that the hierarchy of conditions is slightly
cleaner.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/quirks.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff
Hi,
On 29/03/2021 18:12, Christian Hewitt wrote:
> From: Hyeonki Hong
>
> Add the meson saradc node to the ODROID N2/N2+ common dtsi.
Not sure why this is needed, does it fix something ?
Neil
>
> Signed-off-by: Hyeonki Hong
> ---
> arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 4
There is a whole class of host bridges that cannot know whether
MSIs will be provided or not, as they rely on other blocks
to provide the MSI functionnality, using MSI domains. This is
the case for example on systems that use the ARM GIC architecture.
Introduce a new attribute ('msi_domain')
From: Thomas Gleixner
Some Mediatek host bridges cannot handle MSIs, which is sad.
This also results in an ugly warning at device probe time,
as the core PCI code wasn't told that MSIs were not available.
Advertise this fact to the rest of the core PCI code by
using the 'msi_domain' attribute,
On Tue, Mar 30, 2021 at 11:38:18AM +0100, Suzuki K Poulose wrote:
> On 26/03/2021 16:55, Mathieu Poirier wrote:
> > On Tue, Mar 23, 2021 at 12:06:35PM +, Suzuki K Poulose wrote:
> > > For a nvhe host, the EL2 must allow the EL1&0 translation
> > > regime for TraceBuffer (MDCR_EL2.E2TB ==
On 29/03/2021 18:12, Christian Hewitt wrote:
> Remove an extra tab from the ext_mdio node in the ODROID N2/N2+ common
> dtsi file.
>
> Signed-off-by: Christian Hewitt
> ---
> arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
On Tue, 30 Mar 2021, Pali Rohár wrote:
> > The spec does not give any exceptions AFAICT as to the timeouts required
> > between the three kinds of a Conventional Reset (Hot, Warm, or Cold) and
> > refers to them collectively as a Conventional Reset across the relevant
> > parts of the
On Tue, Mar 30, 2021 at 04:44:32PM +0200, Oliver Neukum wrote:
> Am Dienstag, den 30.03.2021, 16:38 +0200 schrieb Johan Hovold:
> > @@ -1115,6 +1161,8 @@ static void usb_serial_disconnect(struct
> > usb_interface *interface)
> > if (serial->type->disconnect)
> >
The Gateworks GW7901 is an ARM based single board computer (SBC)
featuring:
- i.MX8M Mini SoC
- LPDDR4 DRAM
- eMMC FLASH
- SPI FRAM
- Gateworks System Controller (GSC)
- Atmel ATECC Crypto Authentication
- USB 2.0
- Microchip GbE Switch
- Multiple multi-protocol RS232/RS485/RS422 Serial
The Gateworks GW7901 is an ARM based single board computer (SBC)
featuring:
- i.MX8M Mini SoC
- LPDDR4 DRAM
- eMMC FLASH
- SPI FRAM
- Gateworks System Controller (GSC)
- Atmel ATECC Crypto Authentication
- USB 2.0
- Microchip GbE Switch
- Multiple multi-protocol RS232/RS485/RS422 Serial
ls1012a-freeway board contains a M.2 2230 slot. Update the status of
pcei1 node to okay so that the pcie controller can be probed.
Signed-off-by: Mian Yousaf Kaukab
---
arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts | 4
1 file changed, 4 insertions(+)
diff --git
On Wed, 24 Mar 2021, Lee Jones wrote:
> Daniel,
>
> > MIME-Version: 1.0
> > Content-Type: text/plain; charset=UTF-8
> > Content-Transfer-Encoding: 8bit
> >
> > This is a resend of the remaining patches.
> >
> > All of these patches have been sent before.
>
> Are you still keen to 'hoover
On Mon, 29 Mar 2021 14:52:02 +1300, Chris Packham wrote:
> Convert i2c-mpc to YAML.
>
> Signed-off-by: Chris Packham
> ---
>
> Notes:
> Changes in v2:
> - Rework compatible validation
> - Remove irrelevant i2ccontrol from example
>
> .../devicetree/bindings/i2c/i2c-mpc.txt |
The driver is capable of doing async page flips so we need to tell the
core to allow them.
Signed-off-by: Dan Sneddon
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
Argh, sent this just one hour ago and I already found the first problem:
On 30.03.21 16:13, Thorsten Leemhuis wrote:
> Make the TLDR a bit shorter while improving it at the same time by going
> straight to the aspects readers are more interested it. The change makes
> the process especially more
On Mon 22-03-21 11:21:38, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> Building with 'make W=1' shows a harmless -Wempty-body warning:
>
> fs/jbd2/recovery.c: In function 'fc_do_one_pass':
> fs/jbd2/recovery.c:267:75: error: suggest braces around empty body in an 'if'
> statement
Hi,
On Mon, Mar 29, 2021 at 6:34 PM John Stultz wrote:
>
> Commit 7bf168c8fe8c ("drm/msm: Fix speed-bin support not to
> access outside valid memory"), reworked the nvmem reading of
> "speed_bin", but in doing so dropped handling of the -ENOENT
> case which was previously documented as "fine".
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