On Mon, Apr 19, 2021 at 5:45 PM David Miller wrote:
>
> From: Adam Ford
> Date: Sat, 17 Apr 2021 08:23:29 -0500
>
> > The call to clk_disable_unprepare() can happen before priv is
> > initialized. This means moving clk_disable_unprepare out of
> > out_release i
On Thu, Mar 4, 2021 at 2:04 AM Geert Uytterhoeven wrote:
>
> On Wed, Feb 24, 2021 at 12:52 PM Adam Ford wrote:
> > The AVB refererence clock assumes an external clock that runs
>
> reference
>
> > automatically. Because the Versaclock is wired to provide the
> &
The call to clk_disable_unprepare() can happen before priv is
initialized. This means moving clk_disable_unprepare out of
out_release into a new label.
Fixes: 8ef7adc6beb2("net: ethernet: ravb: Enable optional refclk")
Signed-off-by: Adam Ford
diff --git a/drivers/net/ethern
On Tue, Apr 13, 2021 at 2:33 AM Geert Uytterhoeven wrote:
>
> Hi Adam,
>
> On Mon, Apr 12, 2021 at 3:27 PM Adam Ford wrote:
> > For devices that use a programmable clock for the AVB reference clock,
> > the driver may need to enable them. Add code to find the optio
For devices that use a programmable clock for the AVB reference clock,
the driver may need to enable them. Add code to find the optional clock
and enable it when available.
Signed-off-by: Adam Ford
Reviewed-by: Andrew Lunn
---
V4: Eliminate the NULL check when disabling refclk, and add
to add the additional optional clock, and explicitly
name both of them.
Signed-off-by: Adam Ford
Reviewed-by: Geert Uytterhoeven
Acked-by: Rob Herring
Reviewed-by: Sergei Shtylyov
---
V4: No Change
V3: No Change
V2: No Change
diff --git a/Documentation/devicetree/bindings/net/renesas
On Wed, Apr 7, 2021 at 8:27 PM Peng Fan (OSS) wrote:
>
> Hi Lucas,
>
> On 2021/4/8 6:13, Lucas Stach wrote:
> > Hi Adrien,
> >
> > I feel like I already mentioned to you some time ago that there is
> > already a much more complete patch series to add this functionality on
> > the list [1].
> >
>
On Wed, Apr 7, 2021 at 5:13 PM Lucas Stach wrote:
>
> Hi Adrien,
>
> I feel like I already mentioned to you some time ago that there is
> already a much more complete patch series to add this functionality on
> the list [1].
>
> If you want this functionality to go upstream, please help test and
peripherals is called SPBA1.
Rename the existing spba bus to spba2 and add spba1.
Signed-off-by: Adam Ford
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 4dac4da38f4c..e961acd237a8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
The i.MX8MM reference manual shows there are two spba busses.
SPBA1 handles much of the serial interfaces, and SPBA2 covers much
of the audio.
Add both of them.
Signed-off-by: Adam Ford
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index
On Fri, Apr 2, 2021 at 1:16 PM Adrien Grassein
wrote:
>
> Le ven. 2 avr. 2021 à 19:58, Abel Vesa a écrit :
> >
> > On 21-04-02 19:48:41, Adrien Grassein wrote:
> > > Hi,
> > >
> > > Le ven. 2 avr. 2021 à 19:42, Abel Vesa a écrit :
> > > >
> > > > On 21-04-02 18:45:04, Adrien Grassein wrote:
> >
On Mon, Nov 30, 2020 at 4:02 PM Rob Herring wrote:
>
> On Wed, 18 Nov 2020 17:04:14 -0600, Adam Ford wrote:
> > Add binding doc for fsl,spba-bus.
> >
> > Signed-off-by: Adam Ford
> > ---
> > make dt_binding_check -j8 |grep spba
> > DTEXDocu
On Tue, Dec 29, 2020 at 8:34 PM Peng Fan wrote:
>
> > Subject: Re: [PATCH 2/4] arm64: dts: imx8mn: add spba bus node
> >
> > On Tue, Dec 29, 2020 at 06:26:41AM -0600, Adam Ford wrote:
> > > On Tue, Dec 29, 2020 at 6:15 AM wrote:
> > > >
> > >
On Thu, Mar 4, 2021 at 2:08 AM Geert Uytterhoeven wrote:
>
> Hi Adam,
>
> On Wed, Feb 24, 2021 at 12:52 PM Adam Ford wrote:
> > For devices that use a programmable clock for the AVB reference clock,
> > the driver may need to enable them. Add code to find the optio
On Mon, Mar 22, 2021 at 4:42 PM Abel Vesa wrote:
>
> On 21-03-13 06:28:17, Adam Ford wrote:
> > Most if not all i.MX SoC's call a function which enables all UARTS.
> > This is a problem for users who need to re-parent the clock source,
> > because any attempt to c
On Wed, Mar 3, 2021 at 4:54 AM Marek Vasut wrote:
>
> On 3/3/21 11:47 AM, Abel Vesa wrote:
> > On 20-11-03 13:18:12, Abel Vesa wrote:
> >> The BLK_CTL according to HW design is basically the wrapper of the entire
> >> function specific group of IPs and holds GPRs that usually cannot be placed
>
On Sun, Mar 14, 2021 at 4:40 AM Ahmad Fatoum wrote:
>
> On 13.03.21 16:16, Ahmad Fatoum wrote:
> >> +/* i.MX boards use device trees now. For build tests without CONFIG_OF,
> >> do nothing */
> >> +#ifdef CONFIG_OF
> >> if (imx_keep_uart_clocks) {
> >> int i;
> >>
> >> -
On Thu, Mar 4, 2021 at 2:04 AM Geert Uytterhoeven wrote:
>
> On Wed, Feb 24, 2021 at 12:52 PM Adam Ford wrote:
> > The AVB refererence clock assumes an external clock that runs
>
> reference
>
> > automatically. Because the Versaclock is wired to provide the
> &
are shutdown, this mechanism will also disable any
clocks that were pre-initialized.
Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection")
Suggested-by: Aisheng Dong
Signed-off-by: Adam Ford
Reviewed-by: Abel Vesa
Tested-by: Ahmad Fatoum
---
V5: Combine
are shutdown, this mechanism will also disable any
clocks that were pre-initialized.
Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection")
Suggested-by: Aisheng Dong
Signed-off-by: Adam Ford
Reviewed-by: Abel Vesa
Tested-by: Ahmad Fatoum
---
V4: Check if
On Wed, Mar 10, 2021 at 4:25 PM Abel Vesa wrote:
>
> On 21-03-03 10:31:19, Abel Vesa wrote:
> > On 21-03-02 13:03:04, Adam Ford wrote:
> > > On Mon, Feb 15, 2021 at 7:06 AM Abel Vesa wrote:
> > > >
> > > > On 21-02-13 08:44:28, Adam Ford wrote:
>
On Wed, Mar 3, 2021 at 5:24 PM Philipp Zabel wrote:
>
> On Wed, 2021-03-03 at 16:20 +0100, Benjamin Gaignard wrote:
> > Le 03/03/2021 à 15:17, Philipp Zabel a écrit :
> > > Hi Benjamin,
> > >
> > > On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote:
> > > > The two VPUs inside IMX8MQ
On Mon, Feb 15, 2021 at 7:06 AM Abel Vesa wrote:
>
> On 21-02-13 08:44:28, Adam Ford wrote:
> > On Wed, Feb 3, 2021 at 3:22 PM Adam Ford wrote:
> > >
> > > On Thu, Jan 21, 2021 at 4:24 AM Abel Vesa wrote:
> > > >
> > > > On 21-01-21 10:56:
The AVB refererence clock assumes an external clock that runs
automatically. Because the Versaclock is wired to provide the
AVB refclock, the device tree needs to reference it in order for the
driver to start the clock.
Signed-off-by: Adam Ford
---
V3: New to series
diff --git a/arch/arm64
For devices that use a programmable clock for the AVB reference clock,
the driver may need to enable them. Add code to find the optional clock
and enable it when available.
Signed-off-by: Adam Ford
---
V3: Change 'avb' to 'AVB'
Remove unnessary else statement and pointer maniupluation
The bindings have been updated to support two clocks, but the
original clock now requires the name fck. Add a clock-names
list in the device tree with fck in it.
Signed-off-by: Adam Ford
Reviewed-by: Geert Uytterhoeven
---
V3: No Change
V2: No Change
diff --git a/arch/arm/boot/dts/r8a7742
to add the additional optional clock, and explicitly
name both of them.
Signed-off-by: Adam Ford
Reviewed-by: Geert Uytterhoeven
Acked-by: Rob Herring
---
V3: No Change
V2: No Change
diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
b/Documentation/devicetree/bindings/net
The bindings have been updated to support two clocks, but the
original clock now requires the name fck. Add a clock-names
list in the device tree with fck in it.
Signed-off-by: Adam Ford
Reviewed-by: Geert Uytterhoeven
---
V3: No Change
V2: No Change
diff --git a/arch/arm64/boot/dts/renesas
Enable 100Mhz and 200MHz pinmux and corrsesponding voltage supplies
to enable SDR104 on usdhc1 connecting the WiFi chip.
Signed-off-by: Adam Ford
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
index de2cd0e3201c
On Wed, Feb 3, 2021 at 3:22 PM Adam Ford wrote:
>
> On Thu, Jan 21, 2021 at 4:24 AM Abel Vesa wrote:
> >
> > On 21-01-21 10:56:17, Sascha Hauer wrote:
> > > On Wed, Jan 20, 2021 at 06:14:21PM +0200, Abel Vesa wrote:
> > > > On 21-01-20 16:50:01, Sascha Haue
On Wed, Feb 10, 2021 at 2:18 PM Rob Herring wrote:
>
> On Sun, Feb 07, 2021 at 12:51:38PM -0600, Adam Ford wrote:
> > There are two registers which can set the load capacitance for
> > XTAL1 and XTAL2. These are optional registers when using an
> > external crystal
There are two registers which can set the load capacitance for
XTAL1 and XTAL2. These are optional registers when using an
external crystal. Parse the device tree and set the
corresponding registers accordingly.
Signed-off-by: Adam Ford
---
V3: Fix whitespace. Use regmap_update_bits instead
There are two registers which can set the load capacitance for
XTAL1 and XTAL2. These are optional registers when using an
external crystal. Since XTAL1 and XTAL2 will set to the same value,
update the binding to support a single property called
xtal-load-femtofarads.
Signed-off-by: Adam Ford
down, so let's use 1.5ms timeout there. Waiting for sampling to start
> is faster and we can use 1ms timeout.
>
> Cc: Adam Ford
> Cc: Carl Philipp Klemm
> Cc: Eduardo Valentin
> Cc: H. Nikolaus Schaller
> Cc: Merlijn Wajer
> Cc: Pavel Machek
> Cc: Peter Ujfalusi
&
a wrote:
> > > > > On 21-01-20 16:13:05, Sascha Hauer wrote:
> > > > > > Hi Abel,
> > > > > >
> > > > > > On Wed, Jan 20, 2021 at 04:44:54PM +0200, Abel Vesa wrote:
> > > > > > &g
On Wed, Jan 20, 2021 at 10:35 AM Luca Ceresoli wrote:
>
> Hi Adam,
>
> On 19/01/21 22:21, Adam Ford wrote:
> > There are two registers which can set the load capacitance for
> > XTAL1 and XTAL2. These are optional registers when using an
> > external crystal.
The i.MX8M Nano has the same Flexspi controller used in the i.MX8M
Mini. Add the node and disable it by default.
Signed-off-by: Adam Ford
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 3fac73779fdd..16ea50089567 100644
--- a/arch/arm64
There is a QSPI chip connected to the FlexSPI bus. Enable it.
Signed-off-by: Adam Ford
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
index 2120e6485393..9f575184d899 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn
There are two registers which can set the load capacitance for
XTAL1 and XTAL2. These are optional registers when using an
external crystal. Since XTAL1 and XTAL2 will set to the same value,
update the binding to support a single property called
xtal-load-femtofarads.
Signed-off-by: Adam Ford
There are two registers which can set the load capacitance for
XTAL1 and XTAL2. These are optional registers when using an
external crystal. Parse the device tree and set the
corresponding registers accordingly.
Signed-off-by: Adam Ford
---
V2: Make the math subtract 9000 since we have
On Sat, Jan 16, 2021 at 3:55 PM Adam Ford wrote:
>
> There are two registers which can set the load capacitance for
> XTAL1 and XTAL2. These are optional registers when using an
> external crystal. Parse the device tree and set the
> corresponding registers accordingly.
>
>
On Mon, Jan 18, 2021 at 6:52 AM Abel Vesa wrote:
>
> On 21-01-15 12:29:08, Adam Ford wrote:
>
> ...
>
> > diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c
> > index a66cabfbf94f..66192fe0a898 100644
> > --- a/drivers/clk/imx/clk-imx25.c
>
There are two registers which can set the load capacitance for
XTAL1 and XTAL2. These are optional registers when using an
external crystal. Parse the device tree and set the
corresponding registers accordingly.
Signed-off-by: Adam Ford
diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk
There are two registers which can set the load capacitance for
XTAL1 and XTAL2. These are optional registers when using an
external crystal. Since XTAL1 and XTAL2 will set to the same value,
update the binding to support a single property called
xtal-load-femtofarads.
Signed-off-by: Adam Ford
The bindings have been updated to support two clocks, but the
original clock now requires the name fck. Add a clock-names
list in the device tree with fck in it.
Signed-off-by: Adam Ford
Reviewed-by: Geert Uytterhoeven
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 1 +
arch/arm64/boot/dts
to add the additional optional clock, and explicitly
name both of them.
Signed-off-by: Adam Ford
Reviewed-by: Geert Uytterhoeven
Acked-by: Rob Herring
---
.../devicetree/bindings/net/renesas,etheravb.yaml | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
V2: Change name from
For devices that use a programmable clock for the avb reference clock,
the driver may need to enable them. Add code to find the optional clock
and enable it when available.
Signed-off-by: Adam Ford
---
drivers/net/ethernet/renesas/ravb.h | 1 +
drivers/net/ethernet/renesas/ravb_main.c | 8
The bindings have been updated to support two clocks, but the
original clock now requires the name fck. Add a clock-names
list in the device tree with fck in it.
Signed-off-by: Adam Ford
Reviewed-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7742.dtsi | 1 +
arch/arm/boot/dts/r8a7743.dtsi
are shutdown, this mechanism will also disable any
clocks that were pre-initialized.
Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection")
Suggested-by: Aisheng Dong
Signed-off-by: Adam Ford
---
V3: Return a method more closely related to upstream kernel but
On Tue, Jan 12, 2021 at 9:16 PM Rob Herring wrote:
>
> On Wed, Jan 06, 2021 at 11:38:59AM -0600, Adam Ford wrote:
> > There are two registers which can set the load capacitance for
> > XTAL1 and XTAL2. These are optional registers when using an
> > external cryst
On Tue, Jan 12, 2021 at 10:45 AM Luca Ceresoli wrote:
>
> Hi Adam,
>
> On 11/01/21 17:40, Adam Ford wrote:
> > On Sat, Jan 9, 2021 at 12:02 PM Luca Ceresoli wrote:
> >>
> >> Hi Adam,
> >>
> >> On 09/01/21 04:00, Adam Ford wrote:
> >&
The RZ/G2 Series has the optional CLK_RCAR_USB2_CLOCK_SEL.
Enable it by default. It's disabled by default in the
the device tree, so it should be safe to enable it here.
Signed-off-by: Adam Ford
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 838301650a79
On Sat, Jan 9, 2021 at 12:02 PM Luca Ceresoli wrote:
>
> Hi Adam,
>
> On 09/01/21 04:00, Adam Ford wrote:
> > On Fri, Jan 8, 2021 at 4:49 PM Luca Ceresoli wrote:
> >>
> >> Hi Adam,
> >>
> >> On 06/01/21 18:39, Adam Ford wrote:
> >&
On Mon, Jan 4, 2021 at 1:12 AM Sascha Hauer wrote:
>
> Hi Adam,
>
> On Tue, Dec 29, 2020 at 08:51:28AM -0600, Adam Ford wrote:
> > Remove the earlycon uart clocks that are hard cord in platforms
> > clock driver, instead of parsing the earlycon uart port from dt
>
&g
to the external RTC all the time and
rtc1 point to the SVNS in order to correctly hold date/time over
a power-cycle.
Signed-off-by: Adam Ford
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
index 67e5e5b9ddea..2120e6485393
The WiFi chip is capable of communication at SDR104 speeds.
Enable 100Mhz and 200MHz pinmux to support this.
Signed-off-by: Adam Ford
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
index d897913537ca..988f8ab679ad 100644
On Sat, Jan 9, 2021 at 10:58 AM H. Nikolaus Schaller wrote:
>
> Hi Adam,
>
> > Am 09.01.2021 um 17:39 schrieb Adam Ford :
> >
> > Previously, the 1GHz variants were marked as a turbo,
> > because that variant has reduced thermal operating range.
> >
> >
.
Signed-off-by: Adam Ford
---
V2: The orignal patch had the wrong file added. Add the omap36xx.dtsi
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 05fe5ed127b0..20844dbc002e 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
On Sat, Jan 9, 2021 at 10:39 AM Adam Ford wrote:
>
> Previously, the 1GHz variants were marked as a turbo,
> because that variant has reduced thermal operating range.
>
> Now that the thermal throttling is in place, it should be
> safe to remove the turbo-mode from the 1GHz
.
Signed-off-by: Adam Ford
diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
index 3a5228562b0d..3451f9be104e 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
+++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
@@ -70,6 +70,7 @@ nand@0,0
On Fri, Jan 8, 2021 at 1:37 PM Andreas Kemnade wrote:
>
> Hi,
>
> On Fri, 8 Jan 2021 13:17:06 -0600
> Adam Ford wrote:
>
> > On Mon, Dec 7, 2020 at 8:01 AM Tony Lindgren wrote:
> > >
> > > * Doug Anderson [201204 16:43]:
> > > > Hi,
On Fri, Jan 8, 2021 at 4:49 PM Luca Ceresoli wrote:
>
> Hi Adam,
>
> On 06/01/21 18:39, Adam Ford wrote:
> > There are two registers which can set the load capacitance for
> > XTAL1 and XTAL2. These are optional registers when using an
> > external crystal.
On Fri, Jan 8, 2021 at 4:49 PM Luca Ceresoli wrote:
>
> Hi Adam,
>
> On 06/01/21 18:38, Adam Ford wrote:
> > There are two registers which can set the load capacitance for
> > XTAL1 and XTAL2. These are optional registers when using an
> > external crystal. Updat
On Fri, Jan 8, 2021 at 12:31 PM Adam Ford wrote:
>
> On Fri, Jan 8, 2021 at 7:45 AM Adam Ford wrote:
> >
> > On Fri, Jan 8, 2021 at 1:22 AM Tony Lindgren wrote:
> > >
> > > * H. Nikolaus Schaller [201230 13:29]:
> > > > > Am 30.12.2020 um
sues where nobody took care to debug them.
> > >
> > > That would be since v4.11.
> >
> > I guess maybe best is to include both. Then if someone is debugging
> > why their async probe is failing they will notice this commit, but
> > they also might decide to pick it earlier just to be safe...
>
> OK I'll add the above fixes tag too and apply this into fixes.
>
It might be too late, but...
Tested-by: Adam Ford #logicpd-torpedo-37xx-devkit
> Thanks,
>
> Tony
On Fri, Jan 8, 2021 at 7:45 AM Adam Ford wrote:
>
> On Fri, Jan 8, 2021 at 1:22 AM Tony Lindgren wrote:
> >
> > * H. Nikolaus Schaller [201230 13:29]:
> > > > Am 30.12.2020 um 13:55 schrieb Adam Ford :
> > > > On Wed, Dec 30, 2020 at 2:43 AM Tony L
On Fri, Jan 8, 2021 at 1:22 AM Tony Lindgren wrote:
>
> * H. Nikolaus Schaller [201230 13:29]:
> > > Am 30.12.2020 um 13:55 schrieb Adam Ford :
> > > On Wed, Dec 30, 2020 at 2:43 AM Tony Lindgren wrote:
> > >>
> > >> At least for 4430, try
There are two registers which can set the load capacitance for
XTAL1 and XTAL2. These are optional registers when using an
external crystal. Update the bindings to support them.
Signed-off-by: Adam Ford
---
.../devicetree/bindings/clock/idt,versaclock5.yaml | 12
1 file changed
There are two registers which can set the load capacitance for
XTAL1 and XTAL2. These are optional registers when using an
external crystal. Parse the device tree and set the
corresponding registers accordingly.
Signed-off-by: Adam Ford
---
drivers/clk/clk-versaclock5.c | 64
On Mon, Jan 4, 2021 at 4:41 AM Geert Uytterhoeven wrote:
>
> Hi Adam,
>
> On Mon, Dec 28, 2020 at 10:32 PM Adam Ford wrote:
> > The bindings have been updated to support two clocks, but the
> > original clock now requires the name fck to distinguish it
> > from
On Mon, Jan 4, 2021 at 9:03 PM Shawn Guo wrote:
>
> On Wed, Dec 02, 2020 at 07:59:50AM -0600, Adam Ford wrote:
> > The WiFi chip is capable of communication at SDR104 speeds, and
> > the pinmux was configured to support this, but the sdhc1 controller
> > didn't prope
The RZ/G2 series contain the SPI Multi I/O Bus Controller (RPC-IF).
Add the nodes, but make them disabled by default.
Signed-off-by: Adam Ford
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 17 +
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 17 +
arch/arm64/boot
The Renesas RPC-IF is present on the RZ/G2 Series. Add that to
the description.
Suggested-by: Biju Das
Signed-off-by: Adam Ford
---
drivers/memory/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
V2: New to series
diff --git a/drivers/memory/Kconfig b/drivers/memory
The SPI driver for the Renesas RPC-IF is present on the RZ/G2
Series. Add that to the description.
Suggested-by: Biju Das
Signed-off-by: Adam Ford
---
drivers/spi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
V2: New to series
diff --git a/drivers/spi/Kconfig b/drivers/spi
The RZ/G2 Series has the RPC-IF interface.
Update bindings to support: r8a774a1, r8a774b1, r8a774c0, and r8a774e1
Signed-off-by: Adam Ford
---
.../bindings/memory-controllers/renesas,rpc-if.yaml | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
V2: Updated renesas,rcar-gen3
On Sat, Jan 2, 2021 at 2:13 AM Biju Das wrote:
>
>
>
> > -Original Message-
> > From: Adam Ford
> > Sent: 01 January 2021 21:34
> > To: Biju Das
> > Cc: linux-renesas-...@vger.kernel.org; af...@beaconembedded.com; Krzysztof
> > Kozlowski ;
On Fri, Jan 1, 2021 at 12:58 PM Biju Das wrote:
>
> Hi Adam,
>
> Thanks for the patch.
>
> > -Original Message-
> > From: Adam Ford
> > Sent: 01 January 2021 11:39
> > To: linux-renesas-...@vger.kernel.org
> > Cc: af...@beaconembedded.c
The RZ/G2 series contain the SPI Multi I/O Bus Controller (RPC-IF).
Add the nodes, but make them disabled by default.
Signed-off-by: Adam Ford
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 17 +
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 17 +
arch/arm64/boot
The RZ/G2 Series has the RPC-IF interface.
Update bindings to support: r8a774a1, r8a774b1, r8a774c0, and r8a774e1
Signed-off-by: Adam Ford
---
.../bindings/memory-controllers/renesas,rpc-if.yaml | 4
1 file changed, 4 insertions(+)
diff --git
a/Documentation/devicetree/bindings
so need to add udelay to for the EOCZ (end of conversion)
> bit polling as otherwise we have it time out too early on 4430. We'll be
> changing the loop to use iopoll in the following clean-up patch.
>
> Cc: Adam Ford
I don't have an OMAP4, but if you want, I can test a DM3730.
adam
With the clk driver scanning the device tree the for stdout, it
doesn't require a list of clocks to be passed to it. Remove the
code that generates these clock lists.
Signed-off-by: Adam Ford
---
This was build tested for arm, and tested on i.MX8M Nano.
---
drivers/clk/imx/clk-imx25.c | 12
an
Signed-off-by: Adam Ford
---
Based on NXP's code base and adapted for 5.11-rc1.
https://source.codeaurora.org/external/imx/linux-imx/commit/drivers/clk/imx/clk.c?h=imx_5.4.47_2.2.0=754ae82cc55b7445545fc2f092a70e0f490e9c1b
The original signed-off was retained.
Added the fixes tag.
---
drive
On Tue, Dec 29, 2020 at 6:15 AM wrote:
>
> From: Peng Fan
>
> According to RM, there is a spba bus inside aips3 and aips1, add it.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 362 +++---
> 1 file changed, 189 insertions(+), 173 deletions(-)
>
compatibility with existing
boards.
Signed-off-by: Adam Ford
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index d37ec42a1caa..60e150320ce8 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -835,6
The datasheet for the RZ/G2 Series show the bit for choosing between a crystal
oscillator and an external oscillator is present. Add the bindings for
r8a774a1 (RZ/G2M), r8a774b1 (RZ/G2N), and r8a774e1 (RZ/G2H)
Signed-off-by: Adam Ford
diff --git
a/Documentation/devicetree/bindings/clock
The bindings have been updated to support two clocks, but the
original clock now requires the name fck to distinguish it
from the other.
Signed-off-by: Adam Ford
---
drivers/net/ethernet/renesas/ravb_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet
The bindings have been updated to support two clocks, but the
original clock now requires the name fck. Add a clock-names
list in the device tree with fck in it.
Signed-off-by: Adam Ford
---
arch/arm/boot/dts/r8a7742.dtsi | 1 +
arch/arm/boot/dts/r8a7743.dtsi | 1 +
arch/arm/boot/dts/r8a7744
The bindings have been updated to support two clocks, but the
original clock now requires the name fck. Add a clock-names
list in the device tree with fck in it.
Signed-off-by: Adam Ford
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 1 +
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 1 +
arch
to add the additional optional clock, and explicitly
name both of them.
Signed-off-by: Adam Ford
---
.../devicetree/bindings/net/renesas,etheravb.yaml | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
b
On Mon, Dec 14, 2020 at 4:05 AM Geert Uytterhoeven wrote:
>
> Hi Adam,
>
> On Sun, Dec 13, 2020 at 5:18 PM Adam Ford wrote:
> > The SoC expects the txv_refclk is provided, but if it is provided
> > by a programmable clock, there needs to be a way to get and enable
&
On Mon, Dec 28, 2020 at 6:33 AM Geert Uytterhoeven wrote:
>
> Hi Adam,
>
> On Thu, Dec 24, 2020 at 2:53 PM Adam Ford wrote:
> > On Tue, Dec 22, 2020 at 2:03 AM Geert Uytterhoeven
> > wrote:
> > > On Tue, Dec 22, 2020 at 2:39 AM Adam Ford wrote:
> > &g
The eMMC can run at hs400 and the WiFi chip can run at sdr104.
Set the respective flags to push the sdhi faster.
Signed-off-by: Adam Ford
---
V2: New to series
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
index
In preparation for adding new dev kits, move anything specific to the
RZ/G2M from the SOM-level and baseboard-levels and move them to the
kit-level. This allows the SOM and baseboard to be reused with
other SoC's.
Signed-off-by: Adam Ford
---
V2: Fix missing entries in dts file.
diff --git
for
a parallel RGB and an LVDS display. It uses the same baseboard
and SOM files as the RZ/G2M and RZ/G2N kits.
Signed-off-by: Adam Ford
---
V2: Add missing du node entries
diff --git a/arch/arm64/boot/dts/renesas/Makefile
b/arch/arm64/boot/dts/renesas/Makefile
index cf7e2f77e4ea..5c68de184501 100644
The keys on the baseboard are laid out in an diamond pattern, up, down,
left, right and center. Update the descriptions to make it easier to
read.
Signed-off-by: Adam Ford
---
V2: Make keycode match the key name.
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
b/arch
for
a parallel RGB and an LVDS display. It uses the same baseboard
and SOM as the RZ/G2M.
This SOM has only 2GB of DDR, and beacon-renesom-som.dtsi contains
the base memory node, so an additional memory node isn't necessary.
Signed-off-by: Adam Ford
---
V2: Add missing du node entries.
diff --git
the usb_extal reference.
Signed-off-by: Adam Ford
---
V2: Split this off into its own patch.
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
index a54ec36c69e4..3b3efaf749bb 100644
--- a/arch/arm64/boot/dts/renesas
With the newly added configurable clock options, the audio CODEC can
configure the mclk automatically. Add the reference to the versaclock.
Since the devices on I2C5 can communicate at 400KHz, let's also increase
that too
Signed-off-by: Adam Ford
---
V2: Remove the un-used clock-names
.
Signed-off-by: Adam Ford
---
V2: Go from fixed-factor-clock to just redefining the rcar-sound node
to reference the versaclock instead of the audio_clk_a.
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
index
When the board was added, clock drivers were being updated done at
the same time to allow the versaclock driver to properly configure
the modes. Unfortunately, the updates were not applied to the board
files at the time they should have been, so do it now.
Signed-off-by: Adam Ford
---
V2
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