[PATCH v4 3/5] ARM: implement support for SMCCC TRNG entropy source

reseeding. Cc: Linus Walleij Cc: Russell King Signed-off-by: Ard Biesheuvel [Andre: rework to be initialised by the SMCCC firmware driver] Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij --- arch/arm/Kconfig | 4 ++ arch/arm/include/asm/archrandom.h | 64

[PATCH v4 0/5] ARM: arm64: Add SMCCC TRNG entropy service

ation from the SMCCC firmware driver - use a single bool in smccc.c to hold the initialisation state for arm64 - handle endianess correctly in the KVM provider Andre Przywara (2): firmware: smccc: Introduce SMCCC TRNG framework arm64: Add support for SMCCC TRNG entropy source Ard Biesheuvel (3):

[PATCH v4 5/5] KVM: arm64: implement the TRNG hypervisor call

by the kernel's entropy pool only, to avoid guests draining more precious direct entropy sources. Signed-off-by: Ard Biesheuvel [Andre: minor fixes, drop arch_get_random() usage] Signed-off-by: Andre Przywara --- arch/arm64/include/asm/kvm_host.h | 2 + arch/arm64/kvm/Makefile | 2

[PATCH v4 4/5] arm64: Add support for SMCCC TRNG entropy source

ion, which returns -1 if this interface is not implemented. Signed-off-by: Andre Przywara --- arch/arm64/include/asm/archrandom.h | 72 - 1 file changed, 61 insertions(+), 11 deletions(-) diff --git a/arch/arm64/include/asm/archrandom.h b/arch/arm64/include/asm/archrando

[PATCH v4 1/5] firmware: smccc: Add SMCCC TRNG function call IDs

-off-by: Andre Przywara Reviewed-by: Linus Walleij --- include/linux/arm-smccc.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index f860645f6512..62c54234576c 100644 --- a/include/linux/arm-smccc.h +++ b

[PATCH v2 21/21] arm64: dts: allwinner: Add OrangePi Zero 2 .dts

The OrangePi Zero 2 is a development board with the new H616 SoC. It features the usual connectors used on those small boards, and comes with the AXP305, which seems to be compatible with the AXP805. For more details see: http://linux-sunxi.org/Xunlong_Orange_Pi_Zero2 Signed-off-by: Andre

[PATCH v2 12/21] soc: sunxi: sram: Add support for more than one EMAC clock

The Allwinner H616 adds a second EMAC clock register at offset 0x34, for controlling the second EMAC in this chip. Allow to extend the regmap in this case, to cover more than the current 4 bytes exported. Signed-off-by: Andre Przywara --- drivers/soc/sunxi/sunxi_sram.c | 31

[PATCH v2 20/21] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding

Signed-off-by: Andre Przywara --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index cab8e1b6417b..5f8b5c896e66 100644

[PATCH v2 13/21] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register

into the regmap, so that we can address more than the first register, if needed. Signed-off-by: Andre Przywara --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers

[PATCH v2 17/21] dt-bindings: watchdog: sun4i: Add H616 compatible string

Use enums to group all compatible devices together on the way. Signed-off-by: Andre Przywara --- .../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10

[PATCH v2 15/21] phy: sun4i-usb: Add support for the H616 USB PHY

and assign a new compatible name to it. Signed-off-by: Andre Przywara --- drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 4ba0699e0bb4..671c5cc59433 100644

[PATCH v2 06/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU

The clocks itself are identical to the H6 R-CCU, it's just that the H616 has not all of them implemented (or connected). Signed-off-by: Andre Przywara --- drivers/clk/sunxi-ng/Kconfig | 2 +- drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 47 +- drivers/clk/sunxi-ng

[PATCH v2 10/21] mfd: axp20x: Allow AXP chips without interrupt lines

describes the AXP chip as an interrupt controller before trying to register the irqchip, to avoid probe failures on setups without an interrupt. Signed-off-by: Andre Przywara --- drivers/mfd/axp20x.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/mfd

[PATCH v2 09/21] mmc: sunxi: add support for A100 mmc controller

From: Yangtao Li This patch adds support for A100 MMC controller, which use word address for internal dma. Signed-off-by: Yangtao Li Signed-off-by: Andre Przywara --- drivers/mmc/host/sunxi-mmc.c | 28 +--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git

[PATCH v2 18/21] dt-bindings: allwinner: Add H616 compatible strings

Add simple "allwinner,sun50i-h616-xxx" compatible names to existing bindings, and pair them with an existing fallback compatible string, as the devices are compatible. This covers I2C, infrared, RTC and SPI. Use enums to group all compatible devices together. Signed-off-by: Andr

[PATCH v2 05/21] dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616

Signed-off-by: Andre Przywara --- .../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml

[PATCH v2 14/21] phy: sun4i-usb: Rework "pmu_unk1" handling

Newer SoCs (A100, H616) need to clear a different bit in our "unknown" PMU PHY register. Generalise the existing code by allowing configs to specify a bitmask of bits to clear. Signed-off-by: Andre Przywara --- drivers/phy/allwinner/phy-sun4i-usb.c | 28 +++--

[PATCH v2 16/21] dt-bindings: watchdog: sun4i: Add A100 compatible

From: Yangtao Li Add a binding for A100's watchdog controller. Signed-off-by: Yangtao Li Acked-by: Rob Herring Signed-off-by: Andre Przywara --- .../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree

[PATCH v2 19/21] arm64: dts: allwinner: Add Allwinner H616 .dtsi file

interrupt controller anymore, also it lacks the corresponding NMI pin, so no interrupts for the PMIC. Signed-off-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 715 ++ 1 file changed, 715 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616

[PATCH v2 08/21] dt-bindings: mmc: sunxi: Add Allwinner A100 and H616 compatibles

From: Yangtao Li Add binding for A100's and H616's mmc and emmc controller. Signed-off-by: Yangtao Li Signed-off-by: Andre Przywara --- .../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc

[PATCH v2 11/21] dt-bindings: sram: sunxi-sram: Add H616 compatible string

The H616 adds a second EMAC clock register. We don't know about the exact SRAM properties yet, so this gets omitted for now. Signed-off-by: Andre Przywara --- .../bindings/sram/allwinner,sun4i-a10-system-control.yaml| 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation

[PATCH v2 07/21] clk: sunxi-ng: Add support for the Allwinner H616 CCU

While the clocks are fairly similar to the H6, many differ in tiny details, so a separate clock driver seems indicated. Derived from the H6 clock driver, and adjusted according to the manual. Signed-off-by: Andre Przywara --- drivers/clk/sunxi-ng/Kconfig|5 + drivers/clk

[PATCH v2 00/21] arm64: sunxi: Initial Allwinner H616 SoC support

extend USB PHY support - add DT binding documentation patches Andre Przywara (18): clk: sunxi-ng: h6: Fix clock divider range on some clocks dt-bindings: pinctrl: Add Allwinner H616 compatible strings pinctrl: sunxi: Add support for the Allwinner H616 pin controller pinctrl: sunxi: A

[PATCH v2 02/21] dt-bindings: pinctrl: Add Allwinner H616 compatible strings

A new SoC, a new compatible string. Also we were too miserly with just allowing seven interrupt banks. Signed-off-by: Andre Przywara --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/Documentation

[PATCH v2 04/21] pinctrl: sunxi: Add support for the Allwinner H616-R pin controller

There are only two pins left now, used to connect to the PMIC via I2C. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jernej Skrabec --- drivers/pinctrl/sunxi/Kconfig | 5 ++ drivers/pinctrl/sunxi/Makefile| 1 + drivers/pinctrl/sunxi

[PATCH v2 03/21] pinctrl: sunxi: Add support for the Allwinner H616 pin controller

Port A is used for an internal connection to some analogue circuitry which looks like an AC200 IP (as in the H6), though this is not mentioned in the manual. Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/Kconfig | 5 + drivers/pinctrl/sunxi/Makefile | 1

[PATCH v2 01/21] clk: sunxi-ng: h6: Fix clock divider range on some clocks

at bits [4:2] are indeed masked off, so the manual is right. Change to number of bits in the affected clock's description. Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/clk/sunxi-ng

[PATCH 7/8] arm64: dts: allwinner: Add Allwinner H616 .dtsi file

interrupt controller anymore, so no external interrupts through an NMI pin. The AXP driver needs to learn living with that. Signed-off-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 704 ++ 1 file changed, 704 insertions(+) create mode 100644 arch/arm64/boot

[PATCH 8/8] arm64: dts: allwinner: Add OrangePi Zero 2 .dts

The OrangePi Zero 2 is a development board with the new H616 SoC. It features the usual connectors used on those small boards, and comes with the AXP305, which seems to be compatible with the AXP805. For more details see: http://linux-sunxi.org/Xunlong_Orange_Pi_Zero2 Signed-off-by: Andre

[PATCH 5/8] clk: sunxi-ng: Add support for the Allwinner H616 CCU

While the clocks are fairly similar to the H6, many differ in tiny details, so a separate clock driver seems indicated. Derived from the H6 clock driver, and adjusted according to the manual. Signed-off-by: Andre Przywara --- drivers/clk/sunxi-ng/Kconfig|7 +- drivers/clk

[PATCH 6/8] mmc: sunxi: add support for A100 mmc controller

From: Yangtao Li This patch adds support for A100 MMC controller, which use word address for internal dma. Signed-off-by: Yangtao Li Signed-off-by: Andre Przywara --- drivers/mmc/host/sunxi-mmc.c | 28 +--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git

[PATCH 0/8] arm64: sunxi: Initial Allwinner H616 SoC support

ot/commits/h616-v1 [5] https://github.com/apritzel/arm-trusted-firmware/commits/h616-WIP Andre Przywara (7): clk: sunxi-ng: h6: Fix clock divider range on some clocks pinctrl: sunxi: Add support for the Allwinner H616 pin controller pinctrl: sunxi: Add support for the Allwinner H616-R pin contro

[PATCH 2/8] pinctrl: sunxi: Add support for the Allwinner H616 pin controller

Port A is used for an internal connection to some analogue circuitry which looks like an AC200 IP (as in the H6), though this is not mentioned in the manual. Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/Kconfig | 5 + drivers/pinctrl/sunxi/Makefile | 1

[PATCH 4/8] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU

The clocks itself are identical to the H6 R-CCU, it's just that the H616 has not all of them implemented (or connected). Signed-off-by: Andre Przywara --- drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 47 +- drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 3 +- 2 files changed, 48

[PATCH 3/8] pinctrl: sunxi: Add support for the Allwinner H616-R pin controller

There are only two pins left now, used to connect to the PMIC via I2C. Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/Kconfig | 5 ++ drivers/pinctrl/sunxi/Makefile| 1 + drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c | 58 +++ 3 files

[PATCH 1/8] clk: sunxi-ng: h6: Fix clock divider range on some clocks

at bits [4:2] are indeed masked off, so the manual is right. Change to number of bits in the affected clock's description. Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Andre Przywara --- drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8 ---

[PATCH v3 5/5] KVM: arm64: implement the TRNG hypervisor call

by the kernel's entropy pool only, to avoid guests draining more precious direct entropy sources. Signed-off-by: Ard Biesheuvel [Andre: minor fixes, drop arch_get_random() usage] Signed-off-by: Andre Przywara --- arch/arm64/include/asm/kvm_host.h | 2 + arch/arm64/kvm/Makefile | 2

[PATCH v3 4/5] arm64: Add support for SMCCC TRNG entropy source

ion, which returns -1 if this interface is not implemented. Signed-off-by: Andre Przywara --- arch/arm64/include/asm/archrandom.h | 69 - 1 file changed, 58 insertions(+), 11 deletions(-) diff --git a/arch/arm64/include/asm/archrandom.h b/arch/arm64/include/asm/archrando

[PATCH v3 1/5] firmware: smccc: Add SMCCC TRNG function call IDs

-off-by: Andre Przywara --- include/linux/arm-smccc.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index f860645f6512..62c54234576c 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h

[PATCH v3 3/5] ARM: implement support for SMCCC TRNG entropy source

reseeding. Cc: Linus Walleij Cc: Russell King Signed-off-by: Ard Biesheuvel [Andre: rework to be initialised by the SMCCC firmware driver] Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 4 ++ arch/arm/include/asm/archrandom.h | 64 +++ 2 files

[PATCH v3 2/5] firmware: smccc: Introduce SMCCC TRNG framework

of this interface. For now this return false, but this will be overwritten by each architecture's support patch. Signed-off-by: Andre Przywara --- arch/arm/include/asm/archrandom.h | 10 ++ arch/arm64/include/asm/archrandom.h | 12 drivers/firmware/smccc/smccc.c | 5

[PATCH v3 0/5] ARM: arm64: Add SMCCC TRNG entropy service

"v1" ... v2: - trigger ARCH_RANDOM initialisation from the SMCCC firmware driver - use a single bool in smccc.c to hold the initialisation state for arm64 - handle endianess correctly in the KVM provider Andre Przywara (2): firmware: smccc: Introduce SMCCC TRNG framework arm64: A

[PATCH] random: Use arch_get_random_long_early() for init_std_data()

ly()") Cc: Mark Rutland Signed-off-by: Andre Przywara --- drivers/char/random.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/char/random.c b/drivers/char/random.c index 2a41b21623ae..43bb331a67bd 100644 --- a/drivers/char/random.c +++ b/drivers/char/random.

[PATCH v2 4/5] arm64: Add support for SMCCC TRNG entropy source

ion, which returns -1 if this interface is not implemented. Signed-off-by: Andre Przywara --- arch/arm64/include/asm/archrandom.h | 53 - 1 file changed, 45 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/archrandom.h b/arch/arm64/include/asm/archrando

[PATCH v2 5/5] KVM: arm64: implement the TRNG hypervisor call

Signed-off-by: Andre Przywara --- arch/arm64/include/asm/kvm_host.h | 2 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/hypercalls.c | 6 ++ arch/arm64/kvm/trng.c | 91 +++ 4 files changed, 100 insertions(+), 1 deletion(-) create mode 100644

[PATCH v2 2/5] firmware: smccc: Introduce SMCCC TRNG framework

of this interface. For now this return false, but this will be overwritten by each architecture's support patch. Signed-off-by: Andre Przywara --- arch/arm/include/asm/archrandom.h | 10 ++ arch/arm64/include/asm/archrandom.h | 12 drivers/firmware/smccc/smccc.c | 5

[PATCH v2 3/5] ARM: implement support for SMCCC TRNG entropy source

reseeding. Cc: Linus Walleij Cc: Russell King Signed-off-by: Ard Biesheuvel [Andre: rework to be initialised by the SMCCC firmware driver] Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 4 ++ arch/arm/include/asm/archrandom.h | 64 +++ 2 files

[PATCH v2 0/5] ARM: arm64: Add SMCCC TRNG entropy service

gitlab.arm.com/linux-arm/linux-ap/-/commits/smccc-trng/v2/ Cheers, Andre [1] https://developer.arm.com/documentation/den0098/latest/ Andre Przywara (2): firmware: smccc: Introduce SMCCC TRNG framework arm64: Add support for SMCCC TRNG entropy source Ard Biesheuvel (3): firmware: smccc: Add

[PATCH v2 1/5] firmware: smccc: Add SMCCC TRNG function call IDs

-off-by: Andre Przywara --- include/linux/arm-smccc.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index f860645f6512..62c54234576c 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h

Re: [PATCH v5 10/21] perf arm_spe: Fixup top byte for data virtual address

comment to explain the fixing up. > > Signed-off-by: Leo Yan Thanks for the change! Reviewed-by: Andre Przywara Cheers, Andre > --- > .../util/arm-spe-decoder/arm-spe-decoder.c| 20 --- > 1 file changed, 17 insertions(+), 3 deletions(-) > > diff --git a/

[PATCH 1/2] firmware: smccc: Add SMCCC TRNG function call IDs

/documentation/den0098/latest/ Signed-off-by: Ard Biesheuvel Signed-off-by: Andre Przywara --- include/linux/arm-smccc.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 15c706fb0a37..95aae50eaab4

[PATCH 0/2] arm64: Add support for SMCCC TRNG interface

SMCCC, but no TRNG: regression test) - Ard's KVM patch (plus hack to inject fake numbers for verification purposes) Cheers, Andre [1] https://developer.arm.com/documentation/den0098/latest/ Andre Przywara (1): arm64: Add support for SMCCC TRNG firmware interface Ard Biesheuvel (1): firmware:

[PATCH 2/2] arm64: Add support for SMCCC TRNG firmware interface

ion, which returns -1 if this interface is not implemented. [1] https://developer.arm.com/documentation/den0098/latest/ Signed-off-by: Andre Przywara --- arch/arm64/include/asm/archrandom.h | 83 + 1 file changed, 73 insertions(+), 10 deletions(-) diff --git a/arch/ar

[PATCH] arm64: random: Remove no longer needed prototypes

they have no users outside of this header file. Signed-off-by: Andre Przywara --- arch/arm64/include/asm/archrandom.h | 5 - 1 file changed, 5 deletions(-) diff --git a/arch/arm64/include/asm/archrandom.h b/arch/arm64/include/asm/archrandom.h index 44209f6146aa..ffb1a40d5475 100644 --- a/

[PATCH 3/5] perf: arm_spe: Add nested virt event decoding

can decode it properly. Signed-off-by: Andre Przywara --- tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c | 4 1 file changed, 4 insertions(+) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index

[PATCH 5/5] perf: arm_spe: Decode SVE events

in the SPE decoder to allow the perf tool to correctly report about SVE instructions. Signed-off-by: Andre Przywara --- .../arm-spe-decoder/arm-spe-pkt-decoder.c | 48 ++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt

[PATCH 4/5] perf: arm_spe: Decode memory tagging properties

When SPE records a physical address, it can additionally tag the event with information from the Memory Tagging architecture extension. Decode the two additional fields in the SPE event payload. Signed-off-by: Andre Przywara --- .../util/arm-spe-decoder/arm-spe-pkt-decoder.c | 17

[PATCH 1/5] arm64: spe: Allow new bits in SPE filter register

The ARMv8.3-SPE extension adds some new bits for the event filter. Remove bits 11, 17 and 18 from the RES0 mask, so they can be used correctly. Signed-off-by: Andre Przywara --- arch/arm64/include/asm/sysreg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64

[PATCH 2/5] perf: arm_spe: Add new event packet bits

The ARMv8.3-SPE extension adds some new bits to the event packet fields. Handle bits 11 (alignment), 17 and 18 (SVE predication) when decoding the SPE buffer content. Signed-off-by: Andre Przywara --- .../util/arm-spe-decoder/arm-spe-pkt-decoder.c | 17 + 1 file changed, 17

[PATCH 0/5] perf: arm64: Support ARMv8.3-SPE extensions

The "ARMv8.3-SPE extensions" add some bits to SPE to cover newer architecture features, most prominently SVE. Add the new bits where needed, mostly to perf's SPE packet decoder. Cheers, Andre Andre Przywara (5): arm64: spe: Allow new bits in SPE filter register perf: arm_spe: Add

[PATCH v2] dt-bindings: watchdog: sp-805: Convert to Json-schema

Convert the ARM SP-805 watchdog IP DT binding over to Json-schema. A straight-forward conversion, but the requirement for providing two clocks got strengthened from "should" to "must". Signed-off-by: Andre Przywara --- Hi, this is just the bindings conversion patch, upda

[PATCH v3 3/6] arm64: dts: lg: Fix SP804 users

compatible string. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/lg/lg1312.dtsi | 6 +++--- arch/arm64/boot/dts/lg/lg1313.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 64f3b135068d

[PATCH v3 2/6] ARM: dts: nspire: Fix SP804 users

Even though the SP804 binding allows to specify only one clock, the primecell driver requires a named clock to activate the bus clock. Specify the one clock three times and provide some clock-names, to make the DT match the SP804 and primecell binding. Signed-off-by: Andre Przywara --- arch

[PATCH v3 0/6] ARM/arm64: dts: Fix SP804/SP805 users

://lkml.iu.edu/hypermail/linux/kernel/2008.3/07167.html Andre Przywara (6): ARM: dts: hisilicon: Fix SP804 users ARM: dts: nspire: Fix SP804 users arm64: dts: lg: Fix SP804 users arm64: dts: hisilicon: Fix SP805 clocks arm64: dts: lg: Fix SP805 clocks ARM: dts: hisilicon: Fix SP805 clocks

[PATCH v3 1/6] ARM: dts: hisilicon: Fix SP804 users

the clock list, and add two dummy clock-names to make the primecell driver happy. I don't know what the real APB clock for the IP is, but with the current DT the first timer clock was used for that, so this change keeps the current status. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/h

[PATCH v3 5/6] arm64: dts: lg: Fix SP805 clocks

og counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara Acked-by: Chanho Min --- arch/arm64/boot/dts/lg/lg1312.dtsi | 4 ++-- arch/arm64/boot/dts/lg/lg131

[PATCH v3 6/6] ARM: dts: hisilicon: Fix SP805 clocks

og counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/hisi-x5hd2.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --

[PATCH v3 4/6] arm64: dts: hisilicon: Fix SP805 clocks

og counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 10 ++ arch/arm64/boot/dts/hisilicon/hi6220

[PATCH v2 0/6] dt-bindings: Convert SP804 to Json-schema (and fix users)

-by: on Arm patch Andre Przywara (6): dt-bindings: timers: sp-804: Convert to json-schema ARM: dts: arm: Fix SP804 users ARM: dts: NSP: Fix SP804 compatible node ARM: dts: hisilicon: Fix SP804 users ARM: dts: nspire: Fix SP804 users arm64: dts: lg: Fix SP804 users .../devicetree/bindings

[PATCH v2 2/6] ARM: dts: arm: Fix SP804 users

property, as this is required by the Linux primecell driver. Try to make the clock-names more consistent on the way. Signed-off-by: Andre Przywara Acked-by: Linus Walleij --- arch/arm/boot/dts/arm-realview-pb11mp.dts | 16 arch/arm/boot/dts/mps2.dtsi | 6 -- arch

[PATCH v2 6/6] arm64: dts: lg: Fix SP804 users

compatible string. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/lg/lg1312.dtsi | 6 +++--- arch/arm64/boot/dts/lg/lg1313.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 64f3b135068d

[PATCH v2 5/6] ARM: dts: nspire: Fix SP804 users

Even though the SP804 binding allows to specify only one clock, the primecell driver requires a named clock to activate the bus clock. Specify the one clock three times and provide some clock-names, to make the DT match the SP804 and primecell binding. Signed-off-by: Andre Przywara --- arch

[PATCH v2 3/6] ARM: dts: NSP: Fix SP804 compatible node

The DT binding for SP804 requires to have an "arm,primecell" compatible string. Add this string so that the Linux primecell bus driver picks the device up and activates the clock. Fixes: a0efb0d28b77 ("ARM: dts: NSP: Add SP804 Support to DT") Tested-by: Florian Fainelli

[PATCH v2 4/6] ARM: dts: hisilicon: Fix SP804 users

the clock list, and add two dummy clock-names to make the primecell driver happy. I don't know what the real APB clock for the IP is, but with the current DT the first timer clock was used for that, so this change keeps the current status. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/h

[PATCH v2 1/6] dt-bindings: timers: sp-804: Convert to json-schema

name used by the existing DTs, I refrained from adding them in detail (just allowing the property). The requirement for the APB clock is enforced by the primecell binding already. Signed-off-by: Andre Przywara --- .../devicetree/bindings/timer/arm,sp804.txt | 29 -- .../devicetree/bindings

[PATCH 10/10] ARM: dts: hisilicon: Fix SP805 clocks

og counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/hisi-x5hd2.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --

[PATCH 08/10] ARM: dts: Cygnus: Fix SP805 clocks

og counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/bcm-cygnus.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --

[PATCH 07/10] ARM: dts: arm: Fix SP805 clocks

the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/arm-realview-eb.dtsi | 2 +- arch/arm/boot/dts/arm-realview-pb11mp.dts | 4 ++-- arch/arm/boot/dts/arm-realview-pbx.dts

[PATCH 09/10] ARM: dts: NSP: Fix SP805 clock-names

The SP805 binding sets the name for the actual watchdog clock to "wdog_clk" (with an underscore). Change the name in the DTs for the Broadcom NSP platform to match that. The Linux and U-Boot driver use the *first* clock for this purpose anyway, so it does not break anything. Signed-off

[PATCH 06/10] arm64: dts: lg: Fix SP805 clocks

og counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/lg/lg1312.dtsi | 4 ++-- arch/arm64/boot/dts/lg/lg1313.dtsi | 4 ++-- 2 files

[PATCH 05/10] arm64: dts: hisilicon: Fix SP805 clocks

og counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 10 ++ arch/arm64/boot/dts/hisilicon/hi6220

[PATCH 04/10] arm64: dts: freescale: Fix SP805 clock-names

The SP805 binding sets the order of the clock-names to be: "wdog_clk", "apb_pclk" (in exactly that order). Change the order in the DTs for Freescale platforms to match that. The two clocks given in all nodes are actually the same, so that does not change any behaviour.

[PATCH 00/10] dt-bindings: Convert SP805 to Json-schema (and fix users)

probing the device at all, so I didn't dare to touch those DTs at all. Missing clocks are equally fatal. Cheers, Andre Andre Przywara (10): dt-bindings: watchdog: sp-805: Convert to Json-schema arm64: dts: arm: Fix SP805 clock-names arm64: dts: broadcom: Fix SP805 clock-names arm64: dts

[PATCH 03/10] arm64: dts: broadcom: Fix SP805 clock-names

The SP805 binding sets the name for the actual watchdog clock to "wdog_clk" (with an underscore). Change the name in the DTs for Broadcom platforms to match that. The Linux and U-Boot driver use the *first* clock for this purpose anyway, so it does not break anything. Signed-off

[PATCH 01/10] dt-bindings: watchdog: sp-805: Convert to Json-schema

Convert the ARM SP-805 watchdog IP DT binding over to Json-schema. A straight-forward conversion, but the requirement for providing two clocks got strengthened from "should" to "must". Signed-off-by: Andre Przywara --- .../bindings/watchdog/arm,sp805.txt | 32 --

[PATCH 02/10] arm64: dts: arm: Fix SP805 clock-names

The SP805 binding sets the name for the actual watchdog clock to "wdog_clk" (with an underscore). Change the name in the DTs for ARM Ltd. platforms to match that. The Linux and U-Boot driver use the *first* clock for this purpose anyway, so it does not break anything. Signed-off

[PATCH 5/6] ARM: dts: nspire: Fix SP804 users

Even though the SP804 binding allows to specify only one clock, the primecell driver requires a named clock to activate the bus clock. Specify the one clock three times and provide some clock-names, to make the DT match the SP804 and primecell binding. Signed-off-by: Andre Przywara --- arch

[PATCH 3/6] ARM: dts: broadcom: Fix SP804 node

The DT binding for SP804 requires to have an "arm,primecell" compatible string. Add this string so that the Linux primecell bus driver picks the device up and activates the clock. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- 1 file changed, 1 insertion(+),

[PATCH 2/6] ARM: dts: arm: Fix SP804 users

property, as this is required by the Linux primecell driver. Try to make the clock-names more consistent on the way. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/arm-realview-pb11mp.dts | 16 arch/arm/boot/dts/mps2.dtsi | 6 -- arch/arm/boot/dts/vexpress-v2p

[PATCH 1/6] dt-bindings: timers: sp-804: Convert to json-schema

name used by the existing DTs, I refrained from adding them. The requirement for the APB clock is enforced by the primecell binding already. Signed-off-by: Andre Przywara --- .../devicetree/bindings/timer/arm,sp804.txt | 29 --- .../devicetree/bindings/timer/arm,sp804.yaml | 82

[PATCH 4/6] ARM: dts: hisilicon: Fix SP804 users

the clock list, and add two dummy clock-names to make the primecell driver happy. I don't know what the real APB clock for the IP is, but with the current DT the first timer clock was used for that, so this change keeps the current status. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/h

[PATCH 0/6] dt-bindings: Convert SP804 to Json-schema (and fix users)

. The only other SP804 DT user I could find is FreeBSD, but they seem to use a different binding (no clocks, but a clock-frequency property). For some platforms I wonder how this worked before (missing arm,primecell compatible), maybe they magically spring to life now? Cheers, Andre Andre Przywara (6

[PATCH 6/6] arm64: dts: lg: Fix SP804 users

compatible string. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/lg/lg1312.dtsi | 6 +++--- arch/arm64/boot/dts/lg/lg1313.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 64f3b135068d

Re: next/master bisection: baseline.dmesg.crit on qemu_arm-vexpress-a15

works fine: no GIC messages, and the second core comes up. I did the test with v5.7, v5.8-rc2, v5.8-rc3 and linux-next, all with the same result (ignoring the bug in 5.8-rc2 that this patch here fixes). So can someone shed some light on what is going on here? Is there some bootlog that does not ha

[PATCH v3 3/8] dt-bindings: net: Convert Calxeda Ethernet binding to json-schema

Convert the Calxeda XGMAC Ethernet device binding to DT schema format using json-schema. Signed-off-by: Andre Przywara --- .../devicetree/bindings/net/calxeda-xgmac.txt | 18 --- .../bindings/net/calxeda-xgmac.yaml | 49 +++ 2 files changed, 49 insertions(+), 18

[PATCH v3 1/8] dt-bindings: clock: Convert Calxeda clock bindings to json-schema

oddity is that the addresses are relative to the parent node, without that being pronounced using a ranges property. But this is too late to fix now. Signed-off-by: Andre Przywara Acked-by: Stephen Boyd --- .../devicetree/bindings/clock/calxeda.txt | 17 .../devicetree/bindings/clock

[PATCH v3 7/8] dt-bindings: ipmi: Convert IPMI-SMIC bindings to json-schema

, but there are no in-tree users. Let's allow extra properties to cover any other users. Signed-off-by: Andre Przywara --- .../devicetree/bindings/ipmi/ipmi-smic.txt| 25 .../devicetree/bindings/ipmi/ipmi-smic.yaml | 63 +++ 2 files changed, 63 insertions(+), 25 deletions

[PATCH v3 5/8] dt-bindings: arm: Convert Calxeda L2 cache controller to json-schema

Convert the L2-ECC controller binding to DT schema format using json-schema. This is indented to be just used for error reporting. Signed-off-by: Andre Przywara --- .../devicetree/bindings/arm/calxeda/l2ecc.txt | 15 --- .../bindings/arm/calxeda/l2ecc.yaml | 42

[PATCH v3 6/8] dt-bindings: memory-controllers: Convert Calxeda DDR to json-schema

Convert the Calxeda DDR memory controller binding to DT schema format using json-schema. Although this technically covers the whole DRAM controller, the intention to use it only for error reporting and mapping fault addresses to DRAM chips. Signed-off-by: Andre Przywara --- .../memory

[PATCH v3 8/8] dt-bindings: arm: Add Calxeda system registers json-schema binding

-by: Andre Przywara --- .../bindings/arm/calxeda/hb-sregs.yaml| 49 +++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml diff --git a/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml b/Documentation

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