Hi Samuel,
thank you very much for writing and posting this!
On 28/02/18 08:28, Maxime Ripard wrote:
> Hi,
>
> On Tue, Feb 27, 2018 at 08:27:12PM -0600, Samuel Holland wrote:
>> This mailbox hardware is present in several Allwinner sun8i and sun50i
>> SoCs. Add a device tree binding for it.
>>
Hi,
On 28/02/18 02:27, Samuel Holland wrote:
> If a reception IRQ is pending when a mailbox channel is shut down (for
> example, if the controller uses threaded interrupts), it is possible for
> mbox_chan_received_data to be called while chan->cl is NULL.
>
> This was found while developing a
Hi Samuel,
thank you very much for writing and posting this!
On 28/02/18 08:28, Maxime Ripard wrote:
> Hi,
>
> On Tue, Feb 27, 2018 at 08:27:12PM -0600, Samuel Holland wrote:
>> This mailbox hardware is present in several Allwinner sun8i and sun50i
>> SoCs. Add a device tree binding for it.
>>
Hi,
On 26/02/18 15:54, Samuel Holland wrote:
> On 02/26/18 03:26, Maxime Ripard wrote:
>> On Fri, Feb 23, 2018 at 11:22:06PM +0800, Icenowy Zheng wrote:
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
Is it needed? The bootloader
Hi,
On 26/02/18 15:54, Samuel Holland wrote:
> On 02/26/18 03:26, Maxime Ripard wrote:
>> On Fri, Feb 23, 2018 at 11:22:06PM +0800, Icenowy Zheng wrote:
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
Is it needed? The bootloader
Hi,
On 11/01/18 10:41, Maxime Ripard wrote:
> On Thu, Jan 11, 2018 at 10:23:52AM +0000, Andre Przywara wrote:
>> Hi,
>>
>> On 11/01/18 10:14, Chen-Yu Tsai wrote:
>>> On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara <andre.przyw...@arm.com>
>>> wrote:
Hi,
On 11/01/18 10:41, Maxime Ripard wrote:
> On Thu, Jan 11, 2018 at 10:23:52AM +0000, Andre Przywara wrote:
>> Hi,
>>
>> On 11/01/18 10:14, Chen-Yu Tsai wrote:
>>> On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara
>>> wrote:
>>>> H
Hi,
another take to avoid this patch at all, I just remembered this from an
IRC discussion before:
On 06/01/18 04:23, Icenowy Zheng wrote:
> The Allwinner H6 pin controllers (both the main one and the CPUs one)
> have no bus gate clocks.
I don't think this is true. The pin controller *needs* an
Hi,
another take to avoid this patch at all, I just remembered this from an
IRC discussion before:
On 06/01/18 04:23, Icenowy Zheng wrote:
> The Allwinner H6 pin controllers (both the main one and the CPUs one)
> have no bus gate clocks.
I don't think this is true. The pin controller *needs* an
Hi,
On 11/01/18 10:15, Icenowy Zheng wrote:
>
>
> 于 2018年1月11日 GMT+08:00 下午6:08:19, Andre Przywara <andre.przyw...@arm.com> 写到:
>> Hi,
>>
>> On 06/01/18 04:23, Icenowy Zheng wrote:
>>> The Allwinner H6 pin controllers (both the main one and the CPUs one
Hi,
On 11/01/18 10:15, Icenowy Zheng wrote:
>
>
> 于 2018年1月11日 GMT+08:00 下午6:08:19, Andre Przywara 写到:
>> Hi,
>>
>> On 06/01/18 04:23, Icenowy Zheng wrote:
>>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
>>> have no bus g
Hi,
On 11/01/18 10:14, Chen-Yu Tsai wrote:
> On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara <andre.przyw...@arm.com>
> wrote:
>> Hi,
>>
>> On 06/01/18 04:23, Icenowy Zheng wrote:
>>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
&
Hi,
On 11/01/18 10:14, Chen-Yu Tsai wrote:
> On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara
> wrote:
>> Hi,
>>
>> On 06/01/18 04:23, Icenowy Zheng wrote:
>>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
>>> have no bus gate
Hi,
On 06/01/18 04:23, Icenowy Zheng wrote:
> The Allwinner H6 pin controllers (both the main one and the CPUs one)
> have no bus gate clocks.
>
> Add support for this kind of pin controllers.
>
> Signed-off-by: Icenowy Zheng
> ---
> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30
Hi,
On 06/01/18 04:23, Icenowy Zheng wrote:
> The Allwinner H6 pin controllers (both the main one and the CPUs one)
> have no bus gate clocks.
>
> Add support for this kind of pin controllers.
>
> Signed-off-by: Icenowy Zheng
> ---
> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30
Hi,
On 18/10/17 14:50, Philipp Zabel wrote:
> On Wed, 2017-10-18 at 14:00 +0100, Andre Przywara wrote:
>> Hi,
>
> Thank you for the review.
>
>> On 17/10/17 14:03, Philipp Zabel wrote:
>>> Add reset line status readback, inverted status support, and socfpga
>
Hi,
On 18/10/17 14:50, Philipp Zabel wrote:
> On Wed, 2017-10-18 at 14:00 +0100, Andre Przywara wrote:
>> Hi,
>
> Thank you for the review.
>
>> On 17/10/17 14:03, Philipp Zabel wrote:
>>> Add reset line status readback, inverted status support, and socfpga
>
Hi,
On 17/10/17 14:03, Philipp Zabel wrote:
> Add reset line status readback, inverted status support, and socfpga
> device tree quirks to the simple reset driver, and use it to replace
> the socfpga driver.
>
> Signed-off-by: Philipp Zabel
> ---
> Changes since v3:
> -
Hi,
On 17/10/17 14:03, Philipp Zabel wrote:
> Add reset line status readback, inverted status support, and socfpga
> device tree quirks to the simple reset driver, and use it to replace
> the socfpga driver.
>
> Signed-off-by: Philipp Zabel
> ---
> Changes since v3:
> - Rebased onto reset/next
Hi,
On 27/09/17 14:28, Eric Auger wrote:
> At the moment vgic_its_process_commands() does not
> check the CBASER is valid before processing any command.
> Let's fix that.
Good catch, but actually it goes a bit further:
"When GITS_CTLR.Enabled is written from 0 to 1 behavior is UNPREDICTABLE
if
Hi,
On 27/09/17 14:28, Eric Auger wrote:
> At the moment vgic_its_process_commands() does not
> check the CBASER is valid before processing any command.
> Let's fix that.
Good catch, but actually it goes a bit further:
"When GITS_CTLR.Enabled is written from 0 to 1 behavior is UNPREDICTABLE
if
Hi,
On 27/09/17 14:28, Eric Auger wrote:
> In case the device table save fails, we currently do not
> attempt to save the collection table. However it may
> happen that the device table fails because the structures
> in memory are inconsistent with device GITS_BASER however
> this does not mean
Hi,
On 27/09/17 14:28, Eric Auger wrote:
> In case the device table save fails, we currently do not
> attempt to save the collection table. However it may
> happen that the device table fails because the structures
> in memory are inconsistent with device GITS_BASER however
> this does not mean
Hi,
On 27/09/17 14:28, Eric Auger wrote:
> If the GITS_CBASER Size field is 0, which can correspond to a
> reset value, the userspace fails to set the GITS_CREADR/CWRITER
> offsets to 0. This failure is not justified.
>
> Let's allow this setting which can also correspond to a reset value.
But
Hi,
On 27/09/17 14:28, Eric Auger wrote:
> At the moment the device table save() returns -EINVAL if
> vgic_its_check_id() fails to return the gpa of the entry
> associated to the device/collection id. Let vgic_its_check_id()
> return an int instead of a bool and return a more precised
> error
hat:
> Signed-off-by: Eric Auger <eric.au...@redhat.com>
Reviewed-by: Andre Przywara <andre.przyw...@arm.com>
Cheers,
Andre.
> ---
> virt/kvm/arm/vgic/vgic-its.c | 20 +++-
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/virt/kvm/arm
Hi,
On 27/09/17 14:28, Eric Auger wrote:
> If the GITS_CBASER Size field is 0, which can correspond to a
> reset value, the userspace fails to set the GITS_CREADR/CWRITER
> offsets to 0. This failure is not justified.
>
> Let's allow this setting which can also correspond to a reset value.
But
Hi,
On 27/09/17 14:28, Eric Auger wrote:
> At the moment the device table save() returns -EINVAL if
> vgic_its_check_id() fails to return the gpa of the entry
> associated to the device/collection id. Let vgic_its_check_id()
> return an int instead of a bool and return a more precised
> error
hat:
> Signed-off-by: Eric Auger
Reviewed-by: Andre Przywara
Cheers,
Andre.
> ---
> virt/kvm/arm/vgic/vgic-its.c | 20 +++-
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
> index
Hi,
On 27/09/17 14:28, Eric Auger wrote:
> From: wanghaibin
>
> This patch fix the migrate restore tables failure.
>
> The same scene, at the destination, the restore tables
> interface traversal guest memory, and check the dte/ite
> is valid or not. If all
Hi,
On 27/09/17 14:28, Eric Auger wrote:
> From: wanghaibin
>
> This patch fix the migrate restore tables failure.
>
> The same scene, at the destination, the restore tables
> interface traversal guest memory, and check the dte/ite
> is valid or not. If all dtes/ites are invalid, we will do
>
Hi Maxime,
On 08/09/17 15:39, Maxime Ripard wrote:
> Hi,
>
> On Mon, Sep 04, 2017 at 09:14:52AM +0100, André Przywara wrote:
>>> And obviously, while maintaining the stability of the binding of those
>>> hundreds properties.
>>>
>>> Or, you can base all this on the compatible, and be done with
Hi Maxime,
On 08/09/17 15:39, Maxime Ripard wrote:
> Hi,
>
> On Mon, Sep 04, 2017 at 09:14:52AM +0100, André Przywara wrote:
>>> And obviously, while maintaining the stability of the binding of those
>>> hundreds properties.
>>>
>>> Or, you can base all this on the compatible, and be done with
Hi,
On 31/08/17 00:36, Stefan Brüns wrote:
> The A64 SoC has the same dma engine as the H3 (sun8i), with a
> reduced amount of physical channels. Add the proper config data
> and compatible string to support it.
...
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index
Hi,
On 31/08/17 00:36, Stefan Brüns wrote:
> The A64 SoC has the same dma engine as the H3 (sun8i), with a
> reduced amount of physical channels. Add the proper config data
> and compatible string to support it.
...
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index
Hi,
(sorry for the delay, cleaning up my inbox after holidays)
On 01/08/17 11:50, Alexander Graf wrote:
> Hi Andre,
>
> On 24.07.17 01:23, Andre Przywara wrote:
>> This is a reworked version of my previous post. It addresses Jassi's
>> comments on the driver and also
Hi,
(sorry for the delay, cleaning up my inbox after holidays)
On 01/08/17 11:50, Alexander Graf wrote:
> Hi Andre,
>
> On 24.07.17 01:23, Andre Przywara wrote:
>> This is a reworked version of my previous post. It addresses Jassi's
>> comments on the driver and also
Hi,
On 16/08/17 21:55, Alexandru Gagniuc wrote:
>
>
> On 08/16/2017 01:52 PM, Andreas Färber wrote:
>> Am 16.08.2017 um 22:50 schrieb Alexandru Gagniuc:
>>> On 08/16/2017 02:46 AM, Philipp Zabel wrote:
The reset-simple driver can be used without changes.
Signed-off-by: Philipp
Hi,
On 16/08/17 21:55, Alexandru Gagniuc wrote:
>
>
> On 08/16/2017 01:52 PM, Andreas Färber wrote:
>> Am 16.08.2017 um 22:50 schrieb Alexandru Gagniuc:
>>> On 08/16/2017 02:46 AM, Philipp Zabel wrote:
The reset-simple driver can be used without changes.
Signed-off-by: Philipp
Hi,
On 16/08/17 17:41, Andreas Färber wrote:
> Am 16.08.2017 um 17:11 schrieb Philipp Zabel:
>> On Wed, 2017-08-16 at 14:12 +0200, Andreas Färber wrote:
>>> Am 16.08.2017 um 13:30 schrieb Andre Przywara:
>>>> On 16/08/17 10:46, Philipp Zabel wrote:
>>>>&g
Hi,
On 16/08/17 17:41, Andreas Färber wrote:
> Am 16.08.2017 um 17:11 schrieb Philipp Zabel:
>> On Wed, 2017-08-16 at 14:12 +0200, Andreas Färber wrote:
>>> Am 16.08.2017 um 13:30 schrieb Andre Przywara:
>>>> On 16/08/17 10:46, Philipp Zabel wrote:
>>>>&g
Hi,
On 16/08/17 16:11, Philipp Zabel wrote:
> On Wed, 2017-08-16 at 14:12 +0200, Andreas Färber wrote:
>> Hi Andre,
>>
>> Am 16.08.2017 um 13:30 schrieb Andre Przywara:
>>> On 16/08/17 10:46, Philipp Zabel wrote:
>>>> +/**
>>>> + * struct res
Hi,
On 16/08/17 16:11, Philipp Zabel wrote:
> On Wed, 2017-08-16 at 14:12 +0200, Andreas Färber wrote:
>> Hi Andre,
>>
>> Am 16.08.2017 um 13:30 schrieb Andre Przywara:
>>> On 16/08/17 10:46, Philipp Zabel wrote:
>>>> +/**
>>>> + * struct res
Hi,
On 16/08/17 13:52, Eugeniy Paltsev wrote:
> Hi Philipp,
>
> On Wed, 2017-08-16 at 11:46 +0200, Philipp Zabel wrote:
>> The reset-simple driver can be used without changes.
>>
>> Signed-off-by: Philipp Zabel
>> [snip]
>>
>> --- a/drivers/reset/reset-simple.c
>> +++
Hi,
On 16/08/17 13:52, Eugeniy Paltsev wrote:
> Hi Philipp,
>
> On Wed, 2017-08-16 at 11:46 +0200, Philipp Zabel wrote:
>> The reset-simple driver can be used without changes.
>>
>> Signed-off-by: Philipp Zabel
>> [snip]
>>
>> --- a/drivers/reset/reset-simple.c
>> +++
Hi Philipp,
sorry for the delay, I was on holidays.
Thanks for putting together the series, this looks very good to me.
One comment below...
On 16/08/17 10:46, Philipp Zabel wrote:
> Split reusable parts out of the sunxi driver, to add a driver for simple
> reset controllers with reset lines
Hi Philipp,
sorry for the delay, I was on holidays.
Thanks for putting together the series, this looks very good to me.
One comment below...
On 16/08/17 10:46, Philipp Zabel wrote:
> Split reusable parts out of the sunxi driver, to add a driver for simple
> reset controllers with reset lines
The ARM SMC mailbox binding describes a firmware interface to trigger
actions in software layers running in the EL2 or EL3 exception levels.
The term "ARM" here relates to the SMC instruction as part of the ARM
instruction set, not as a standard endorsed by ARM Ltd.
Signed-off-by: Andr
The ARM SMC mailbox binding describes a firmware interface to trigger
actions in software layers running in the EL2 or EL3 exception levels.
The term "ARM" here relates to the SMC instruction as part of the ARM
instruction set, not as a standard endorsed by ARM Ltd.
Signed-off-by: Andr
is not implemented.
This allows the usage of a mailbox to trigger firmware actions on SoCs
which either don't have a separate management processor or on which such
a core is not available. A user of this mailbox could be the SCP
interface.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
d
is not implemented.
This allows the usage of a mailbox to trigger firmware actions on SoCs
which either don't have a separate management processor or on which such
a core is not available. A user of this mailbox could be the SCP
interface.
Signed-off-by: Andre Przywara
---
drivers/mailbox/Kconfig
For 64-bit Allwinner SoCs there exist firmware implementations which
provide SCPI controlled handlers for DVFS, sensors and power domains.
To allow usage of this features, enable the required SMC mailbox when
Allwinner SoCs are supported by the kernel.
Signed-off-by: Andre Przywara <andre.pr
For 64-bit Allwinner SoCs there exist firmware implementations which
provide SCPI controlled handlers for DVFS, sensors and power domains.
To allow usage of this features, enable the required SMC mailbox when
Allwinner SoCs are supported by the kernel.
Signed-off-by: Andre Przywara
---
drivers
[1] https://github.com/apritzel/arm-trusted-firmware/commits/allwinner-scpi-wip
Andre Przywara (3):
DT: mailbox: add binding doc for the ARM SMC mailbox
mailbox: introduce ARM SMC based mailbox
mailbox: Kconfig: enable ARM SMC mailbox on 64-bit Allwinner SoCs
.../devicetree/bindings/mailbox/a
[1] https://github.com/apritzel/arm-trusted-firmware/commits/allwinner-scpi-wip
Andre Przywara (3):
DT: mailbox: add binding doc for the ARM SMC mailbox
mailbox: introduce ARM SMC based mailbox
mailbox: Kconfig: enable ARM SMC mailbox on 64-bit Allwinner SoCs
.../devicetree/bindings/mailbox/a
Hi,
On 07/07/17 15:35, Mark Rutland wrote:
> Hi Andre,
>
> As a nit, please post bindings before drivers, as per
> Documentation/devicetree/bindings/submitting-patches.txt.
Sure.
> On Fri, Jun 30, 2017 at 10:56:02AM +0100, Andre Przywara wrote:
>> Add binding documentatio
Hi,
On 07/07/17 15:35, Mark Rutland wrote:
> Hi Andre,
>
> As a nit, please post bindings before drivers, as per
> Documentation/devicetree/bindings/submitting-patches.txt.
Sure.
> On Fri, Jun 30, 2017 at 10:56:02AM +0100, Andre Przywara wrote:
>> Add binding documentatio
Hi,
On 29/06/17 12:49, Maxime Ripard wrote:
> On Thu, Jun 29, 2017 at 11:57:05AM +0100, Andre Przywara wrote:
>> Hi,
>>
>> On 25/06/17 21:45, Priit Laes wrote:
>>> Convert sun7i-a20.dtsi to new CCU driver.
>>
>> I know that some people hat^Wget annoyed b
Hi,
On 29/06/17 12:49, Maxime Ripard wrote:
> On Thu, Jun 29, 2017 at 11:57:05AM +0100, Andre Przywara wrote:
>> Hi,
>>
>> On 25/06/17 21:45, Priit Laes wrote:
>>> Convert sun7i-a20.dtsi to new CCU driver.
>>
>> I know that some people hat^Wget annoyed b
Hi,
thanks for having a look!
On 30/06/17 13:25, Maxime Ripard wrote:
> Hi,
>
> On Fri, Jun 30, 2017 at 10:56:00AM +0100, Andre Przywara wrote:
>> The remaining patches demonstrate usage of this feature to drive SCPI
>> services
>> implemented as part of the ARM Trus
Hi,
thanks for having a look!
On 30/06/17 13:25, Maxime Ripard wrote:
> Hi,
>
> On Fri, Jun 30, 2017 at 10:56:00AM +0100, Andre Przywara wrote:
>> The remaining patches demonstrate usage of this feature to drive SCPI
>> services
>> implemented as part of the ARM Trus
to signal a mailbox condition to firmware or a
hypervisor.
Please have a look and comment whether this sounds like a useful addition
to the kernel.
Cheers,
Andre.
[1] https://github.com/apritzel/arm-trusted-firmware/commits/allwinner-scpi-wip
Andre Przywara (8):
mailbox: introduce ARM SMC bas
to signal a mailbox condition to firmware or a
hypervisor.
Please have a look and comment whether this sounds like a useful addition
to the kernel.
Cheers,
Andre.
[1] https://github.com/apritzel/arm-trusted-firmware/commits/allwinner-scpi-wip
Andre Przywara (8):
mailbox: introduce ARM SMC bas
Add binding documentation for the generic ARM SMC mailbox.
This is not describing hardware, but a firmware interface.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
.../devicetree/bindings/mailbox/arm-smc.txt| 61 ++
1 file changed, 61 inse
Add binding documentation for the generic ARM SMC mailbox.
This is not describing hardware, but a firmware interface.
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/mailbox/arm-smc.txt| 61 ++
1 file changed, 61 insertions(+)
create mode 100644
is not implemented.
This allows the usage of a mailbox to trigger firmware actions on SoCs
which either don't have a separate management processor or on which such
a core is not available. A user of this mailbox could be the SCP
interface.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
d
is not implemented.
This allows the usage of a mailbox to trigger firmware actions on SoCs
which either don't have a separate management processor or on which such
a core is not available. A user of this mailbox could be the SCP
interface.
Signed-off-by: Andre Przywara
---
drivers/mailbox/Kconfig
in the kernel.
The number here is made explicitly compatible with the in-kernel CCF
numbering, so any consumer can be switched over by just exchaning the
phandle.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +
1 file chan
in the kernel.
The number here is made explicitly compatible with the in-kernel CCF
numbering, so any consumer can be switched over by just exchaning the
phandle.
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git
calls.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index ef6f10e..5
calls.
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index ef6f10e..58c3675 100644
--- a/arch/arm64
a clock to be running, we set
a fixed clock rate for this particular clock to prevent the Linux driver
from turning it off.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm6
a clock to be running, we set
a fixed clock rate for this particular clock to prevent the Linux driver
from turning it off.
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i
For 64-bit Allwinner SoCs there exist firmware implementations which
provide SCPI controlled handlers for DVFS, sensors and power domains.
To allow usage of this features, enable the required SMC mailbox when
Allwinner SoCs are supported by the kernel.
Signed-off-by: Andre Przywara <andre.pr
For 64-bit Allwinner SoCs there exist firmware implementations which
provide SCPI controlled handlers for DVFS, sensors and power domains.
To allow usage of this features, enable the required SMC mailbox when
Allwinner SoCs are supported by the kernel.
Signed-off-by: Andre Przywara
---
drivers
This adds support for the SCPI protocol using an SMC mailbox and some
shared memory in SRAM.
The SCPI provider is implemented in the ARM Trusted Firmware layer
(running in EL3 on the application processor cores), triggered by an smc
call.
Signed-off-by: Andre Przywara <andre.przyw...@arm.
This adds support for the SCPI protocol using an SMC mailbox and some
shared memory in SRAM.
The SCPI provider is implemented in the ARM Trusted Firmware layer
(running in EL3 on the application processor cores), triggered by an smc
call.
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts
The SCPI protocol allows controlling device power domains, which
abstracts the various ways of providing voltage to devices like Ethernet
PHYs or on-board WiFi chips.
Provide the power domain provider DT node, which can be referenced by
a power domain consumer device.
Signed-off-by: Andre
The SCPI protocol allows controlling device power domains, which
abstracts the various ways of providing voltage to devices like Ethernet
PHYs or on-board WiFi chips.
Provide the power domain provider DT node, which can be referenced by
a power domain consumer device.
Signed-off-by: Andre
Hi,
On 25/06/17 21:45, Priit Laes wrote:
> Convert sun7i-a20.dtsi to new CCU driver.
I know that some people hat^Wget annoyed by me asking this, but anyway:
Why do we actually need this?
This ultimately makes the DT incompatible with older kernels (as
actually shipped by distros today).
So if
Hi,
On 25/06/17 21:45, Priit Laes wrote:
> Convert sun7i-a20.dtsi to new CCU driver.
I know that some people hat^Wget annoyed by me asking this, but anyway:
Why do we actually need this?
This ultimately makes the DT incompatible with older kernels (as
actually shipped by distros today).
So if
Hi,
On 27/06/17 11:23, Icenowy Zheng wrote:
>
>
> 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara <andre.przyw...@arm.com> 写到:
>> Hi,
>>
>> On 27/06/17 10:41, Maxime Ripard wrote:
>>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
&
Hi,
On 27/06/17 11:23, Icenowy Zheng wrote:
>
>
> 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara 写到:
>> Hi,
>>
>> On 27/06/17 10:41, Maxime Ripard wrote:
>>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
>>>> Hi,
>>>&
Hi,
On 27/06/17 10:41, Maxime Ripard wrote:
> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
>> Hi,
>>
>> (CC:ing some people from that Rockchip dmwac series)
>>
>> On 27/06/17 09:21, Corentin Labbe wrote:
>>> On Tue, Jun 27, 20
Hi,
On 27/06/17 10:41, Maxime Ripard wrote:
> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
>> Hi,
>>
>> (CC:ing some people from that Rockchip dmwac series)
>>
>> On 27/06/17 09:21, Corentin Labbe wrote:
>>> On Tue, Jun 27, 20
Hi,
(CC:ing some people from that Rockchip dmwac series)
On 27/06/17 09:21, Corentin Labbe wrote:
> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe
>> wrote:
>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100,
Hi,
(CC:ing some people from that Rockchip dmwac series)
On 27/06/17 09:21, Corentin Labbe wrote:
> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe
>> wrote:
>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote:
.141087]ret_from_fork+0x10/0x40
>
> It is rather easy to avoid by dropping xb_write_mutex before calling
> xenbus_dev_queue_reply().
>
> Fixes: fd8aa9095a95c02dcc35540a263267c29b8fda9d ("xen: optimize xenbus
> driver for multiple concurrent xenstore accesses").
&
.141087]ret_from_fork+0x10/0x40
>
> It is rather easy to avoid by dropping xb_write_mutex before calling
> xenbus_dev_queue_reply().
>
> Fixes: fd8aa9095a95c02dcc35540a263267c29b8fda9d ("xen: optimize xenbus
> driver for multiple concurrent xenstore accesses").
&
Hi,
On 09/06/17 16:26, Jagan Teki wrote:
> On Friday 09 June 2017 08:21 PM, Maxime Ripard wrote:
>> Hi Jagan,
>>
>> On Fri, Jun 09, 2017 at 12:40:52PM +, Jagan Teki wrote:
>>> + {
>>> +pinctrl-names = "default";
>>> +pinctrl-0 = <_pins>;
>>> +status = "okay";
>>> +};
>>> +
>>>
Hi,
On 09/06/17 16:26, Jagan Teki wrote:
> On Friday 09 June 2017 08:21 PM, Maxime Ripard wrote:
>> Hi Jagan,
>>
>> On Fri, Jun 09, 2017 at 12:40:52PM +, Jagan Teki wrote:
>>> + {
>>> +pinctrl-names = "default";
>>> +pinctrl-0 = <_pins>;
>>> +status = "okay";
>>> +};
>>> +
>>>
Hi,
On 09/06/17 13:40, Jagan Teki wrote:
> From: Jagan Teki
>
> Remove duplicate ethernet@1c3 from allwinner/sun50i-a64.dtsi
I think this is an artefact of the sun8i-dwmac merging, where both David
and Maxime merged the DT patches in their trees (compare
Hi,
On 09/06/17 13:40, Jagan Teki wrote:
> From: Jagan Teki
>
> Remove duplicate ethernet@1c3 from allwinner/sun50i-a64.dtsi
I think this is an artefact of the sun8i-dwmac merging, where both David
and Maxime merged the DT patches in their trees (compare e53f67e9 and
103aefa0). I think
545]mutex_lock_nested+0x3c/0x50
>> [ 248.128016]xenbus_dev_queue_reply+0x3c/0x230
>> [ 248.133005]xenbus_thread+0x788/0x798
>> [ 248.137306]kthread+0x110/0x140
>> [ 248.141087]ret_from_fork+0x10/0x40
>>
>> It is rather easy to a
545]mutex_lock_nested+0x3c/0x50
>> [ 248.128016]xenbus_dev_queue_reply+0x3c/0x230
>> [ 248.133005]xenbus_thread+0x788/0x798
>> [ 248.137306]kthread+0x110/0x140
>> [ 248.141087]ret_from_fork+0x10/0x40
>>
>> It is rather easy to avoi
Hi,
On 26/05/17 04:54, Chen-Yu Tsai wrote:
> On Fri, May 26, 2017 at 6:30 AM, André Przywara
> wrote:
>> On 25/05/17 20:26, Jagan Teki wrote:
>>> From: Jagan Teki
>>>
>>> Orangepi Win/WinPlus is an open-source single-board computer
>>> using
Hi,
On 26/05/17 04:54, Chen-Yu Tsai wrote:
> On Fri, May 26, 2017 at 6:30 AM, André Przywara
> wrote:
>> On 25/05/17 20:26, Jagan Teki wrote:
>>> From: Jagan Teki
>>>
>>> Orangepi Win/WinPlus is an open-source single-board computer
>>> using the Allwinner A64 SOC.
>>>
>>> A64 Orangepi
Hi,
On 19/05/17 09:29, Icenowy Zheng wrote:
>
>
> 于 2017年5月19日 GMT+08:00 下午4:27:21, Andre Przywara <andre.przyw...@arm.com> 写到:
>> Hi,
>>
>> On 18/05/17 08:16, Icenowy Zheng wrote:
>>> Add support of AXP803 regulators in the Pine64 device t
Hi,
On 19/05/17 09:29, Icenowy Zheng wrote:
>
>
> 于 2017年5月19日 GMT+08:00 下午4:27:21, Andre Przywara 写到:
>> Hi,
>>
>> On 18/05/17 08:16, Icenowy Zheng wrote:
>>> Add support of AXP803 regulators in the Pine64 device tree, in order
>> to
>>
Hi,
On 18/05/17 08:16, Icenowy Zheng wrote:
> Add support of AXP803 regulators in the Pine64 device tree, in order to
> enable many future functionalities, e.g. Wi-Fi.
>
> Signed-off-by: Icenowy Zheng
> ---
> Changes in v6:
> - Rebased on next-20170517.
>
>
301 - 400 of 945 matches
Mail list logo