On Sat, Sep 5, 2020 at 6:47 AM Palmer Dabbelt wrote:
>
> On Fri, 04 Sep 2020 09:57:09 PDT (-0700), Christoph Hellwig wrote:
> > On Fri, Sep 04, 2020 at 10:13:18PM +0530, Anup Patel wrote:
> >> I respectfully disagree. IMHO, the previous code made the RISC-V
> >> tim
On Fri, Sep 4, 2020 at 9:55 PM Christoph Hellwig wrote:
>
> On Fri, Sep 04, 2020 at 09:51:21PM +0530, Anup Patel wrote:
> > The TIME CSR is usually not present on most RISC-V systems so the
> > M-mode firmware will emulate the TIME CSR for the S-mode (MMU) kernel
> > w
so we provide alternate implementation of
the get_cycles() for the M-mode (NoMMU) kernel which expects drivers
to provide custom MMIO based read_cycles64() method.
Fixes: 2bc3fc877aa9 ("RISC-V: Remove CLINT related code from timer
and arch")
Signed-off-by: Anup Patel
---
arch/riscv/i
On Fri, Sep 4, 2020 at 9:33 PM Christoph Hellwig wrote:
>
> On Fri, Sep 04, 2020 at 07:26:41PM +0530, Anup Patel wrote:
> > On Fri, Sep 4, 2020 at 6:30 PM Christoph Hellwig wrote:
> > >
> > > On Fri, Sep 04, 2020 at 08:58:25PM +0800, Qiu Wenbo wrote:
> > >
On Fri, Sep 4, 2020 at 6:30 PM Christoph Hellwig wrote:
>
> On Fri, Sep 04, 2020 at 08:58:25PM +0800, Qiu Wenbo wrote:
> > I can confirm this patch also breaks K210 support. It seems that
> > csr_read(CSR_TIME) will trigger an illegal instruction exception on K210.
>
> CSR_TIME is trapped by just
On Fri, Sep 4, 2020 at 3:16 PM Christoph Hellwig wrote:
>
> On Fri, Sep 04, 2020 at 03:12:18PM +0530, Anup Patel wrote:
> > I tried Linux-5.9-rc3 using nommu_virt_defconfig at my end. I am not
> > able to reproduce
> > this issue. Is there additional Kconfig opti
On Fri, Sep 4, 2020 at 2:01 PM Christoph Hellwig wrote:
>
> On Fri, Aug 21, 2020 at 12:35:20PM -0700, Linus Torvalds wrote:
> > On Fri, Aug 21, 2020 at 11:26 AM Palmer Dabbelt wrote:
> > >
> > > * The CLINT driver has been split in two: one to handle the M-mode CLINT
> > > (memory mapped and
On Mon, Aug 31, 2020 at 8:09 AM Jiangyifei wrote:
>
>
> > -Original Message-
> > From: Anup Patel [mailto:a...@brainfault.org]
> > Sent: Friday, August 28, 2020 12:54 PM
> > To: Jiangyifei
> > Cc: Paul Walmsley ; Palmer Dabbelt
> > ; Albert Ou ;
for updating MAINTAINERS file
Anup Patel (13):
RISC-V: Add hypervisor extension related CSR defines
RISC-V: Add initial skeletal KVM support
RISC-V: KVM: Implement VCPU create, init and destroy functions
RISC-V: KVM: Implement VCPU interrupts and requests handling
RISC-V: KVM: Implement KV
of these are read/write registers.
In future, more VCPU register types will be added (such as FP) for the
KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/include/uapi/asm/kvm.h | 53 ++-
arch/riscv/kvm/vcpu.c
Stage2 VMID for each Guest VCPU whenever
VMID changes using VCPU request KVM_REQ_UPDATE_HGATP
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 24 ++
arch/riscv/kvm/Makefile | 3
.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/kvm/vcpu_exit.c | 76 ++
1 file changed, 76 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
index 9a0d2a57ced5..1324b95d3044
From: Atish Patra
Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating
point registers such as F0-F31 and FCSR. This support is added for
both 'F' and 'D' extensions.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Add myself as maintainer for KVM RISC-V and Atish as designated reviewer.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git
to
the guest VCPU whenever the guest VCPU hrtimer event expires.
This patch adds guest VCPU timer implementation along with ONE_REG
interface to access VCPU timer state from user space.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Acked
which are forwarded to user space because these calls cannot be
implemented in kernel space. In future, when we implement SBI v0.2 for
Guest, we will forward SBI v0.2 experimental and vendor extension calls
to user space.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
reason KVM_EXIT_RISCV_SBI for SBI calls forwarded to
userspace tool.
CC: Jonathan Corbet
CC: linux-...@vger.kernel.org
Signed-off-by: Anup Patel
---
Documentation/virt/kvm/api.rst | 193 +++--
1 file changed, 184 insertions(+), 9 deletions(-)
diff --git
performance.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 5 +
arch/riscv/kernel/asm-offsets.c | 72 +
arch/riscv/kvm/vcpu.c | 91
This patch implements MMU notifiers for KVM RISC-V so that Guest
physical address space is in-sync with Host physical address space.
This will allow swapping, page migration, etc to work transparently
with KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
support]
Signed-off-by: Yifei Jiang
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/include/asm/kvm_host.h | 12 +
arch/riscv/include/asm/pgtable-bits.h | 1 +
arch/riscv/kvm/Kconfig| 1 +
arch/riscv/kvm/main.c
() and kvm_arch_vcpu_put() functions
respectively.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 10 +-
arch/riscv/kernel/asm-offsets.c | 78
arch/riscv/kvm/Makefile | 2
and kvm_riscv_vcpu_has_interrupt() function.
The KVM_REQ_VCPU_RESET request will be used by SBI emulation (added
later) to power-up a VCPU in power-off state. The user-space can use
the GET_MPSTATE/SET_MPSTATE ioctls to get/set power state of a VCPU.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed
-by: Yifei Jiang
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 22 ++
arch/riscv/kernel/asm-offsets.c | 6 +
arch/riscv/kvm/Kconfig| 1 +
arch/riscv/kvm/Makefile | 1
kvm_arch_vcpu_ioctl_run() which is semi-complete and
extended by subsequent patches.
3. Stubs for required arch specific stage2 MMU functions.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/Kconfig | 2 +
arch
This patch implements VCPU create, init and destroy functions
required by generic KVM module. We don't have much dynamic
resources in struct kvm_vcpu_arch so these functions are quite
simple for KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed
This patch extends asm/csr.h by adding RISC-V hypervisor extension
related defines.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/csr.h | 89
1 file changed, 89
On Mon, Aug 31, 2020 at 5:56 PM Anup Patel wrote:
>
> This series adds initial KVM RISC-V support. Currently, we are able to boot
> Linux on RV64/RV32 Guest with multiple VCPUs.
>
> Key aspects of KVM RISC-V added by this series are:
> 1. No RISC-V specific KVM IOCTL
> 2.
for updating MAINTAINERS file
Anup Patel (14):
RISC-V: Add hypervisor extension related CSR defines
RISC-V: Add initial skeletal KVM support
RISC-V: KVM: Implement VCPU create, init and destroy functions
RISC-V: KVM: Implement VCPU interrupts and requests handling
RISC-V: KVM: Implement KV
On Fri, Jul 24, 2020 at 2:25 PM Yifei Jiang wrote:
>
> Hi,
>
> These two patches enable support for vhost-net on RISC-V architecture. They
> are developed
> based on the Linux source in this repo: https://github.com/avpatel/linux,
> the branch is riscv_kvm_v13.
>
> The accompanying QEMU is from
On Thu, Aug 27, 2020 at 1:54 PM Yifei Jiang wrote:
>
> Add two interfaces of log dirty for kvm_main.c, and detele the interface
> kvm_vm_ioctl_get_dirty_log which is redundantly defined.
>
> CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT is added in defconfig.
>
> Signed-off-by: Yifei Jiang
>
On Thu, Aug 27, 2020 at 1:53 PM Yifei Jiang wrote:
>
> The correct sip/sie 0x222 could mask wrong 0x000 by VSIP_VALID_MASK,
> This patch fix it.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
> ---
> arch/riscv/kvm/vcpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
, CLINT provides IPI registers along with
timer registers. To use CLINT IPI registers, the CLINT timer driver
provides IPI related callbacks to arch/riscv.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
Acked-by: Daniel Lezcano
Reviewed-by: Atish Patra
Reviewed-by: Palmer Dabbelt
MMIO compare register
for clockevent device.
We now have a separate CLINT timer driver which also provide CLINT
based IPI operations so let's remove CLINT MMIO related code from
arch/riscv directory and RISC-V timer driver.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
Acked
We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel
Reviewed-by: Palmer Dabbelt
Tested-by: Emil Renner Berhing
Reviewed-by: Atish Patra
Reviewed-by: Rob Herring
Reviewed-by: Palmer Dabbelt
---
.../bindings/timer/sifive,clint.yaml | 60
We add mechanism to set custom IPI operations so that CLINT driver
from drivers directory can provide custom IPI operations.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
Reviewed-by: Atish Patra
Reviewed-by: Palmer Dabbelt
---
arch/riscv/include/asm/clint.h | 25
- Added riscv,clint0 compatible string in DT bindings document
Anup Patel (4):
RISC-V: Add mechanism to provide custom IPI operations
clocksource/drivers: Add CLINT timer driver
RISC-V: Remove CLINT related code from timer and arch
dt-bindings: timer: Add CLINT bindings
.../bindings/tim
p_init(void)
> for (j = 0; j < ARRAY_SIZE(pte_bits); j++)
> pg_level[i].mask |= pte_bits[j].mask;
>
> - debugfs_create_file("kernel_page_tables", 0400, NULL, NULL,
> + debugfs_create_file("kernel_page_tables", 0400, NULL,
> _ptd_info,
> _fops);
> +#ifdef CONFIG_EFI
> + if (efi_enabled(EFI_RUNTIME_SERVICES))
> + debugfs_create_file("efi_page_tables", 0400, NULL,
> _ptd_info,
> + _fops);
> +#endif
>
> return 0;
> }
> --
> 2.24.0
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
>
> EXCEPTION_TABLE(0x10)
>
> +#ifdef CONFIG_EFI
> + . = ALIGN(PECOFF_SECTION_ALIGNMENT);
> + __pecoff_text_end = .;
> +#endif
> . = ALIGN(SECTION_ALIGN);
> _data = .;
>
> @@ -83,16 +91,26 @@ SECTIONS
> .sdata : {
> __global_pointer$ = . + 0x800;
> *(.sdata*)
> - /* End of data section */
> - _edata = .;
> }
>
> +#ifdef CONFIG_EFI
> + .pecoff_edata_padding : { BYTE(0); . = ALIGN(PECOFF_FILE_ALIGNMENT); }
> + __pecoff_data_raw_size = ABSOLUTE(. - __pecoff_text_end);
> +#endif
> +
> + /* End of data section */
> + _edata = .;
> +
> BSS_SECTION(PAGE_SIZE, PAGE_SIZE, 0)
>
> .rel.dyn : {
> *(.rel.dyn*)
> }
>
> +#ifdef CONFIG_EFI
> + . = ALIGN(PECOFF_SECTION_ALIGNMENT);
> + __pecoff_data_virt_size = ABSOLUTE(. - __pecoff_text_end);
> +#endif
> _end = .;
>
> STABS_DEBUG
> --
> 2.24.0
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> + pt_ops.alloc_pmd = alloc_pmd_fixmap;
> + pt_ops.get_pmd_virt = get_pmd_virt_fixmap;
> +#endif
> /* Setup swapper PGD for fixmap */
> create_pgd_mapping(swapper_pg_dir, FIXADDR_START,
> __pa_symbol(fixmap_pgd_next),
> @@ -533,6 +593,14 @@ static void __init setup_vm_final(void)
> /* Move to swapper page table */
> csr_write(CSR_SATP, PFN_DOWN(__pa_symbol(swapper_pg_dir)) |
> SATP_MODE);
> local_flush_tlb_all();
> +
> + /* generic page allocation functions must be used to setup page table
> */
> + pt_ops.alloc_pte = alloc_pte_late;
> + pt_ops.get_pte_virt = get_pte_virt_late;
> +#ifndef __PAGETABLE_PMD_FOLDED
> + pt_ops.alloc_pmd = alloc_pmd_late;
> + pt_ops.get_pmd_virt = get_pmd_virt_late;
> +#endif
> }
> #else
> asmlinkage void __init setup_vm(uintptr_t dtb_pa)
> --
> 2.24.0
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
fix_to_virt(FIX_BTMAP_BEGIN): %08lx\n",
> + fix_to_virt(FIX_BTMAP_BEGIN));
> + pr_warn("fix_to_virt(FIX_BTMAP_END): %08lx\n",
> + fix_to_virt(FIX_BTMAP_END));
> +
> + pr_warn("FIX_BTMAP_END: %d\n", FIX_BTMAP_END);
> + pr_warn("FIX_BTMAP_BEGIN: %d\n", FIX_BTMAP_BEGIN);
> + }
> +#endif
> }
>
> static void __init setup_vm_final(void)
> --
> 2.24.0
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
On Thu, Aug 13, 2020 at 9:10 AM Qiu Wenbo wrote:
>
> Exception vector is missing on nommu platform and that is an issue.
> This patch is tested in Sipeed Maix Bit Dev Board.
>
> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> Suggested-by: Anup Patel
On Wed, Aug 12, 2020 at 12:16 AM Atish Patra wrote:
>
> On Tue, Aug 11, 2020 at 1:41 AM Anup Patel wrote:
> >
> > On Tue, Aug 11, 2020 at 12:07 PM Qiu Wenbo wrote:
> > >
> > > Exception vector is missing on nommu platform and it is a big issue.
> > >
On Tue, Aug 11, 2020 at 12:07 PM Qiu Wenbo wrote:
>
> Exception vector is missing on nommu platform and it is a big issue.
> This patch is tested in Sipeed MAIX Bit Dev Board.
>
> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> Signed-off-by: Qiu Wenbo
> ---
>
On Wed, Aug 5, 2020 at 7:17 AM Palmer Dabbelt wrote:
>
> On Fri, 24 Jul 2020 00:18:18 PDT (-0700), Anup Patel wrote:
> > The current RISC-V timer driver is convoluted and implements two
> > distinct timers:
> > 1. S-mode timer: This is for Linux RISC-V S-mode with MMU.
if (pgprot_val(prot))
> set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
> - } else {
> + else
> pte_clear(_mm, addr, ptep);
> - local_flush_tlb_page(addr);
> - }
> + local_flush_tlb_page(addr);
> }
>
&
Change subject to:
RISC-V: KVM: kernel mmio read/write support
Also add 1-2 sentences of commit description.
On Fri, Jul 24, 2020 at 2:25 PM Yifei Jiang wrote:
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> ---
> arch/riscv/kvm/vcpu_exit.c | 38
On Fri, Jul 24, 2020 at 2:25 PM Yifei Jiang wrote:
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> ---
> arch/riscv/kvm/vcpu_exit.c | 38 --
> 1 file changed, 32 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu_exit.c
Please change subject to:
"RISC-V: KVM: enable ioeventfd capability"
Also add 1-2 sentences of commit description.
On Fri, Jul 24, 2020 at 2:25 PM Yifei Jiang wrote:
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> ---
> arch/riscv/kvm/Kconfig | 2 ++
> arch/riscv/kvm/Makefile
On Sat, Jul 25, 2020 at 10:46 AM Atish Patra wrote:
>
> On Fri, Jul 24, 2020 at 12:19 AM Anup Patel wrote:
> >
> > Right now the RISC-V timer driver is convoluted to support:
> > 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for
> >c
MMIO compare register
for clockevent device.
We now have a separate CLINT timer driver which also provide CLINT
based IPI operations so let's remove CLINT MMIO related code from
arch/riscv directory and RISC-V timer driver.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
Acked
We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel
Reviewed-by: Palmer Dabbelt
Tested-by: Emil Renner Berhing
---
.../bindings/timer/sifive,clint.yaml | 60 +++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree
, CLINT provides IPI registers along with
timer registers. To use CLINT IPI registers, the CLINT timer driver
provides IPI related callbacks to arch/riscv.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
Acked-by: Daniel Lezcano
---
drivers/clocksource/Kconfig | 9 ++
drivers
We add mechanism to set custom IPI operations so that CLINT driver
from drivers directory can provide custom IPI operations.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
Reviewed-by: Atish Patra
---
arch/riscv/include/asm/clint.h | 25
arch/riscv/include/asm
sed series on Linux-5.8-rc2
- Added pr_warn() for case where ipi_ops not available in PATCH1
- Updated ipi_inject() prototype to use "struct cpumask *" in PATCH1
- Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4
- Added riscv,clint0 compatible string in DT bindings doc
On Thu, Jul 23, 2020 at 10:38 PM Rob Herring wrote:
>
> On Thu, Jul 23, 2020 at 07:54:09PM +0530, Anup Patel wrote:
> > We add DT bindings documentation for CLINT device.
> >
> > Signed-off-by: Anup Patel
> > Reviewed-by: Palmer Dabbelt
>
We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel
Reviewed-by: Palmer Dabbelt
Tested-by: Emil Renner Berhing
---
.../bindings/timer/sifive,clint.yaml | 58 +++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree
, CLINT provides IPI registers along with
timer registers. To use CLINT IPI registers, the CLINT timer driver
provides IPI related callbacks to arch/riscv.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
---
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile | 1
LINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4
- Added riscv,clint0 compatible string in DT bindings document
Anup Patel (4):
RISC-V: Add mechanism to provide custom IPI operations
clocksource/drivers: Add CLINT timer driver
RISC-V: Remove CLINT related code from timer and arch
d
MMIO compare register
for clockevent device.
We now have a separate CLINT timer driver which also provide CLINT
based IPI operations so let's remove CLINT MMIO related code from
arch/riscv directory and RISC-V timer driver.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
---
arch/riscv
We add mechanism to set custom IPI operations so that CLINT driver
from drivers directory can provide custom IPI operations.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
Reviewed-by: Atish Patra
---
arch/riscv/include/asm/clint.h | 25
arch/riscv/include/asm
On Tue, Jul 21, 2020 at 5:48 PM Sean Anderson wrote:
>
> On 7/20/20 9:15 PM, Atish Patra wrote:
> > On Fri, Jul 17, 2020 at 12:52 AM Anup Patel wrote:
> >>
> >> We add DT bindings documentation for CLINT device.
> >>
> >> Signed-off-by: Anup Pate
On Tue, Jul 21, 2020 at 5:45 PM Daniel Lezcano
wrote:
>
> On 21/07/2020 13:49, Anup Patel wrote:
> > On Tue, Jul 21, 2020 at 4:32 PM Daniel Lezcano
> > wrote:
> >>
> >> On 17/07/2020 09:50, Anup Patel wrote:
> >>> We add a separate CLINT timer d
On Tue, Jul 21, 2020 at 4:32 PM Daniel Lezcano
wrote:
>
> On 17/07/2020 09:50, Anup Patel wrote:
> > We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
> > RISC-V NoMMU kernel).
> >
> > The CLINT MMIO device provides three things:
> > 1. 64bit
On Tue, Jul 21, 2020 at 6:41 AM Atish Patra wrote:
>
> On Fri, Jul 17, 2020 at 12:52 AM Anup Patel wrote:
> >
> > We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
> > RISC-V NoMMU kernel).
> >
> > The CLINT MMIO device provides three thing
On Tue, Jul 21, 2020 at 6:45 AM Atish Patra wrote:
>
> On Fri, Jul 17, 2020 at 12:52 AM Anup Patel wrote:
> >
> > We add DT bindings documentation for CLINT device.
> >
> > Signed-off-by: Anup Patel
> > Reviewed-by: Palmer Dabbelt
> > Tested-by: Emil
On Tue, Jul 21, 2020 at 2:32 PM Ard Biesheuvel wrote:
>
> On Tue, 21 Jul 2020 at 11:57, Arnd Bergmann wrote:
> >
> > On Tue, Jul 21, 2020 at 6:18 AM Atish Patra wrote:
> > > On Sat, Jul 18, 2020 at 2:24 AM Arnd Bergmann wrote:
> > > > On Sat, Jul 18, 2020 at 3:05 AM Atish Patra
> > > >
We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel
Reviewed-by: Palmer Dabbelt
Tested-by: Emil Renner Berhing
---
.../bindings/timer/sifive,clint.yaml | 58 +++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree
- Updated ipi_inject() prototype to use "struct cpumask *" in PATCH1
- Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4
- Added riscv,clint0 compatible string in DT bindings document
Anup Patel (4):
RISC-V: Add mechanism to provide custom IPI operations
clocksour
, CLINT provides IPI registers along with
timer registers. To use CLINT IPI registers, the CLINT timer driver
provides IPI related callbacks to arch/riscv.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
---
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile | 1
MMIO compare register
for clockevent device.
We now have a separate CLINT timer driver which also provide CLINT
based IPI operations so let's remove CLINT MMIO related code from
arch/riscv directory and RISC-V timer driver.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
---
arch/riscv
We add mechanism to set custom IPI operations so that CLINT driver
from drivers directory can provide custom IPI operations.
Signed-off-by: Anup Patel
Tested-by: Emil Renner Berhing
---
arch/riscv/include/asm/clint.h | 25
arch/riscv/include/asm/smp.h | 19
On Fri, Jul 17, 2020 at 10:58 AM Daniel Lezcano
wrote:
>
> On 17/07/2020 07:21, Anup Patel wrote:
> > On Fri, Jul 17, 2020 at 2:57 AM Daniel Lezcano
> > wrote:
> >>
> >>
> >> Hi Anup,
> >>
> >>
> >> On 15/07/2020 09:15, Anup
On Fri, Jul 17, 2020 at 2:57 AM Daniel Lezcano
wrote:
>
>
> Hi Anup,
>
>
> On 15/07/2020 09:15, Anup Patel wrote:
> > The TIME CSR and SBI calls are not available in RISC-V M-mode so we
> > separate add CLINT driver for Linux RISC-V M-mode (i.e. RISC-V NoMMU
&g
Hi Daniel,
On Thu, Jul 16, 2020 at 7:31 PM Daniel Lezcano
wrote:
>
>
> Hi Anup,
>
>
> On 16/07/2020 14:32, Anup Patel wrote:
> > On Wed, Jul 15, 2020 at 11:20 PM Rob Herring wrote:
>
> [ ... ]
>
> > Thanks for these steps. I will fix and send v4.
>
&g
k_ops pageattr_ops = {
> +static const struct mm_walk_ops pageattr_ops = {
> .pgd_entry = pageattr_pgd_entry,
> .p4d_entry = pageattr_p4d_entry,
> .pud_entry = pageattr_pud_entry,
> --
> 2.27.0
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
t.c
> +++ b/arch/riscv/mm/init.c
> @@ -517,7 +517,7 @@ void mark_rodata_ro(void)
> }
> #endif
>
> -void __init resource_init(void)
> +static void __init resource_init(void)
> {
> struct memblock_region *region;
>
> --
> 2.27.0
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
LATFORM=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_UAS=y
> +CONFIG_MMC=y
> +CONFIG_MMC_SPI=y
> CONFIG_RTC_CLASS=y
> CONFIG_VIRTIO_PCI=y
> CONFIG_VIRTIO_BALLOON=y
> --
> 2.7.4
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
On Wed, Jul 15, 2020 at 11:20 PM Rob Herring wrote:
>
> On Wed, 15 Jul 2020 12:45:05 +0530, Anup Patel wrote:
> > We add DT bindings documentation for CLINT device.
> >
> > Signed-off-by: Anup Patel
> > Reviewed-by: Palmer Dabbelt
> > ---
> > .../bind
MMIO compare register
for clockevent device.
We now have a separate CLINT timer driver which also provide CLINT
based IPI operations so let's remove CLINT MMIO related code from
arch/riscv directory and RISC-V timer driver.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig| 2
The TIME CSR and SBI calls are not available in RISC-V M-mode so we
separate add CLINT driver for Linux RISC-V M-mode (i.e. RISC-V NoMMU
kernel).
Signed-off-by: Anup Patel
---
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer
We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel
Reviewed-by: Palmer Dabbelt
---
.../bindings/timer/sifive,clint.yaml | 58 +++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.yaml
We add mechanism to set custom IPI operations so that CLINT driver
from drivers directory can provide custom IPI operations.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/smp.h | 19
arch/riscv/kernel/sbi.c | 14
arch/riscv/kernel/smp.c | 43
() prototype to use "struct cpumask *" in PATCH1
- Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4
- Added riscv,clint0 compatible string in DT bindings document
Anup Patel (4):
RISC-V: Add mechanism to provide custom IPI operations
clocksource/drivers: Add CLINT ti
On Tue, Jul 14, 2020 at 4:32 AM Palmer Dabbelt wrote:
>
> On Sat, 27 Jun 2020 09:19:52 PDT (-0700), Anup Patel wrote:
> > The current RISC-V timer driver is convoluted and implements two
> > distinct timers:
> > 1. S-mode timer: This is for Linux RISC-V S-mode with MMU.
On Tue, Jul 14, 2020 at 8:07 AM Rob Herring wrote:
>
> On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote:
> > We add DT bindings documentation for CLINT device.
> >
> > Signed-off-by: Anup Patel
> > Reviewed-by: Palmer Dabbelt
> > ---
>
reason KVM_EXIT_RISCV_SBI for SBI calls forwarded to
userspace tool.
CC: Jonathan Corbet
CC: linux-...@vger.kernel.org
Signed-off-by: Anup Patel
---
Documentation/virt/kvm/api.rst | 193 +++--
1 file changed, 184 insertions(+), 9 deletions(-)
diff --git
Add myself as maintainer for KVM RISC-V and Atish as designated reviewer.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git
to
the guest VCPU whenever the guest VCPU hrtimer event expires.
This patch adds guest VCPU timer implementation along with ONE_REG
interface to access VCPU timer state from user space.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Acked
This patch implements MMU notifiers for KVM RISC-V so that Guest
physical address space is in-sync with Host physical address space.
This will allow swapping, page migration, etc to work transparently
with KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
From: Atish Patra
Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating
point registers such as F0-F31 and FCSR. This support is added for
both 'F' and 'D' extensions.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
This patch implements all required functions for programming
the stage2 page table for each Guest/VM.
At high-level, the flow of stage2 related functions is similar
from KVM ARM/ARM64 implementation but the stage2 page table
format is quite different for KVM RISC-V.
Signed-off-by: Anup Patel
which are forwarded to user space because these calls cannot be
implemented in kernel space. In future, when we implement SBI v0.2 for
Guest, we will forward SBI v0.2 experimental and vendor extension calls
to user space.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
performance.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 5 +
arch/riscv/kernel/asm-offsets.c | 72 +
arch/riscv/kvm/vcpu.c | 91
Stage2 VMID for each Guest VCPU whenever
VMID changes using VCPU request KVM_REQ_UPDATE_HGATP
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 24 ++
arch/riscv/kvm/Makefile | 3
.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/kvm/vcpu_exit.c | 76 ++
1 file changed, 76 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
index 7fd603acd97a..6ef833e29e71
and kvm_riscv_vcpu_has_interrupt() function.
The KVM_REQ_VCPU_RESET request will be used by SBI emulation (added
later) to power-up a VCPU in power-off state. The user-space can use
the GET_MPSTATE/SET_MPSTATE ioctls to get/set power state of a VCPU.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed
This patch extends asm/csr.h by adding RISC-V hypervisor extension
related defines.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/csr.h | 87
1 file changed, 87
() and kvm_arch_vcpu_put() functions
respectively.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 9 +-
arch/riscv/kernel/asm-offsets.c | 76
arch/riscv/kvm/Makefile | 2
will happen
in user-space and KVM kernel module will only take care of register
updates before resuming the trapped VCPU.
The handling for stage2 page faults for unmapped Guest RAM will be
implemeted by a separate patch later.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo
kvm_arch_vcpu_ioctl_run() which is semi-complete and
extended by subsequent patches.
3. Stubs for required arch specific stage2 MMU functions.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/Kconfig| 2 +
arch
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