for updating MAINTAINERS file
Anup Patel (13):
RISC-V: Add hypervisor extension related CSR defines
RISC-V: Add initial skeletal KVM support
RISC-V: KVM: Implement VCPU create, init and destroy functions
RISC-V: KVM: Implement VCPU interrupts and requests handling
RISC-V: KVM: Implement KV
of these are read/write registers.
In future, more VCPU register types will be added (such as FP) for the
KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/include/uapi/asm/kvm.h | 52 ++-
arch/riscv/kvm/vcpu.c
This patch implements VCPU create, init and destroy functions
required by generic KVM module. We don't have much dynamic
resources in struct kvm_vcpu_arch so these functions are quite
simple for KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed
gt;
> --
> Andreas Schwab, SUSE Labs, sch...@suse.de
> GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
> "And now for something completely different."
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
On Wed, Jul 1, 2020 at 7:44 AM Zong Li wrote:
>
> On Wed, Jul 1, 2020 at 2:57 AM Atish Patra wrote:
> >
> > On Tue, 2020-06-30 at 17:08 +0530, Anup Patel wrote:
> > > On Tue, Jun 30, 2020 at 3:48 PM Anup Patel
> > > wrote:
> > > > On Tue, Jun 30,
omain_remove(intc_domain);
> return rc;
> }
>
> --
> 2.1.0
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
On Wed, Jul 1, 2020 at 6:48 AM Alan Kao wrote:
>
> On Mon, Jun 29, 2020 at 11:19:09AM +0800, Zong Li wrote:
> > This patch set adds raw event support on RISC-V. In addition, we
> > introduce the DT mechanism to make our perf more generic and common.
> >
> > Currently, we set the hardware events
On Tue, Jun 30, 2020 at 3:48 PM Anup Patel wrote:
>
> On Tue, Jun 30, 2020 at 1:34 PM Zong Li wrote:
> >
> > On Tue, Jun 30, 2020 at 3:40 PM Anup Patel wrote:
> > >
> > > On Tue, Jun 30, 2020 at 12:07 PM Zong Li wrote:
> > > >
> >
On Tue, Jun 30, 2020 at 1:34 PM Zong Li wrote:
>
> On Tue, Jun 30, 2020 at 3:40 PM Anup Patel wrote:
> >
> > On Tue, Jun 30, 2020 at 12:07 PM Zong Li wrote:
> > >
> > > On Mon, Jun 29, 2020 at 9:23 PM Anup Patel wrote:
> > > >
> &
On Tue, Jun 30, 2020 at 12:07 PM Zong Li wrote:
>
> On Mon, Jun 29, 2020 at 9:23 PM Anup Patel wrote:
> >
> > On Mon, Jun 29, 2020 at 6:23 PM Zong Li wrote:
> > >
> > > On Mon, Jun 29, 2020 at 4:28 PM Anup Patel wrote:
> > > >
> &g
On Mon, Jun 29, 2020 at 8:49 AM Zong Li wrote:
>
> This patch set adds raw event support on RISC-V. In addition, we
> introduce the DT mechanism to make our perf more generic and common.
>
> Currently, we set the hardware events by writing the mhpmeventN CSRs, it
> would raise an illegal
On Mon, Jun 29, 2020 at 8:49 AM Zong Li wrote:
>
> Add device tree bindings for performance monitor unit. And it passes the
> dt_binding_check verification.
>
> Signed-off-by: Zong Li
> ---
> .../devicetree/bindings/riscv/pmu.yaml| 59 +++
> 1 file changed, 59
On Mon, Jun 29, 2020 at 11:22 AM Zong Li wrote:
>
> On Mon, Jun 29, 2020 at 12:53 PM Anup Patel wrote:
> >
> > On Mon, Jun 29, 2020 at 8:49 AM Zong Li wrote:
> > >
> > > This patch set adds raw event support on RISC-V. In addition, we
> > > int
On Mon, Jun 29, 2020 at 8:49 AM Zong Li wrote:
>
> Add support for raw events and hardware cache events. Currently, we set
> the events by writing the mhpmeventN CSRs, it would raise an illegal
> instruction exception and trap into m-mode to emulate event selector
> CSRs access. It doesn't make
On Mon, Jun 29, 2020 at 10:05 AM Zong Li wrote:
>
> On Mon, Jun 29, 2020 at 12:17 PM Anup Patel wrote:
> >
> > On Mon, Jun 29, 2020 at 8:49 AM Zong Li wrote:
> > >
> > > Add support for raw events and hardware cache events. Currently, we set
> > &
On Mon, Jun 29, 2020 at 12:06 PM Zong Li wrote:
>
> On Mon, Jun 29, 2020 at 12:38 PM Anup Patel wrote:
> >
> > On Mon, Jun 29, 2020 at 9:58 AM Zong Li wrote:
> > >
> > > On Mon, Jun 29, 2020 at 12:09 PM Anup Patel wrote:
> > > >
> &
On Mon, Jun 29, 2020 at 9:58 AM Zong Li wrote:
>
> On Mon, Jun 29, 2020 at 12:09 PM Anup Patel wrote:
> >
> > On Mon, Jun 29, 2020 at 8:49 AM Zong Li wrote:
> > >
> > > Add device tree bindings for performance monitor unit. And it passes the
On Mon, Jun 29, 2020 at 6:23 PM Zong Li wrote:
>
> On Mon, Jun 29, 2020 at 4:28 PM Anup Patel wrote:
> >
> > On Mon, Jun 29, 2020 at 11:22 AM Zong Li wrote:
> > >
> > > On Mon, Jun 29, 2020 at 12:53 PM Anup Patel wrote:
> > > >
> &
On Mon, Jun 29, 2020 at 8:49 AM Zong Li wrote:
>
> Each architecture is responsible for mapping generic hardware and cache
> events to their own specific encoding of hardware events. For each
> architecture, it also have to distinguish the defination of hardware
> events of different platforms of
compare
register for clockevent device.
This patch removes MMIO related stuff from RISC-V timer driver
so that we can have a separate CLINT timer driver.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig| 2 +-
arch/riscv/include/asm/timex.h| 28
We add mechanism to set custom IPI operations so that CLINT driver
from drivers directory can provide custom IPI operations.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/smp.h | 11 +
arch/riscv/kernel/sbi.c | 14
arch/riscv/kernel/smp.c | 43
We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel
Reviewed-by: Palmer Dabbelt
---
.../bindings/timer/sifive,clint.txt | 34 +++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
The TIME CSR and SBI calls are not available in RISC-V M-mode so we
add CLINT driver for Linux RISC-V M-mode (i.e. RISC-V NoMMU kernel).
Signed-off-by: Anup Patel
---
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-clint.c | 229
to use "struct cpumask *" in PATCH1
- Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4
- Added riscv,clint0 compatible string in DT bindings document
Anup Patel (5):
RISC-V: Add mechanism to provide custom IPI operations
RISC-V: Remove CLINT related code
c
We will be having separate CLINT timer driver which will also
provide CLINT based IPI operations so let's remove CLINT related
code from arch/riscv directory.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/clint.h | 39 --
arch/riscv/kernel/Makefile | 2
On Fri, May 29, 2020 at 4:48 AM Rob Herring wrote:
>
> On Tue, May 26, 2020 at 05:32:30PM -0700, Palmer Dabbelt wrote:
> > On Thu, 21 May 2020 23:29:36 PDT (-0700), sean...@gmail.com wrote:
> > > On 5/22/20 1:54 AM, Anup Patel wrote:
> > > > On Fri, May 22, 202
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
Reviewed-by: Marc Zyngier
The RISC-V per-HART local interrupt controller driver is mandatory
for all RISC-V system (with/without MMU) hence we force select it
for CONFIG_RISCV (just like RISCV_TIMER).
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff
The plic_find_hart_id() can be useful to other interrupt controller
drivers (such as RISC-V local interrupt driver) so we rename this
function to riscv_of_parent_hartid() and place it in arch directory
along with riscv_of_processor_hartid().
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
es related to puggable IPI triggering
- Separate patch for self-contained IPI handling routine
- Removed patch for GENERIC_IRQ kconfig options
- Added patch to remove do_IRQ() function
- Rebased upon Atish's SMP patches
Anup Patel (6):
RISC-V: self-contained IPI handling routine
RISC-V: Renam
m IRQCHIP drivers.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
---
arch/riscv/include/asm/irq.h | 1 -
arch/riscv/include/asm/smp.h | 3 +++
arch/riscv/kernel/irq.c | 16 ++--
arch/riscv/kernel/smp.c | 11 ++
-off-by: Palmer Dabbelt
Signed-off-by: Anup Patel
Acked-by: Palmer Dabbelt
Reviewed-by: Marc Zyngier
Reviewed-by: Atish Patra
---
arch/riscv/Kconfig| 1 +
arch/riscv/include/asm/irq.h | 2 -
arch/riscv/kernel/irq.c | 33 +--
arch/riscv/kernel/traps.c
The only thing do_IRQ() does is call handle_arch_irq function
pointer. We can very well call handle_arch_irq function pointer
directly from assembly and remove do_IRQ() function hence this
patch.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/kernel/entry.S | 4 +++-
arch
On Fri, Jun 5, 2020 at 2:10 AM Palmer Dabbelt wrote:
>
> On Thu, 21 May 2020 06:45:40 PDT (-0700), Anup Patel wrote:
> > We add mechanism to set custom IPI operations so that CLINT driver
> > from drivers directory can provide custom IPI operations.
> >
>
On Fri, Jun 5, 2020 at 2:10 AM Palmer Dabbelt wrote:
>
> On Thu, 21 May 2020 06:45:43 PDT (-0700), Anup Patel wrote:
> > The TIME CSR and SBI calls are not available in RISC-V M-mode so we
> > add CLINT driver for Linux RISC-V M-mode (i.e. RISC-V NoMMU kernel).
> >
>
On Fri, Jun 5, 2020 at 2:10 AM Palmer Dabbelt wrote:
>
> On Thu, 21 May 2020 06:45:42 PDT (-0700), Anup Patel wrote:
> > Right now the RISC-V timer is convoluted to support:
> > 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR
> >for clocksource and SBI ti
On Fri, Jun 5, 2020 at 2:10 AM Palmer Dabbelt wrote:
>
> On Thu, 21 May 2020 06:45:41 PDT (-0700), Anup Patel wrote:
> > We will be having separate CLINT timer driver which will also
> > provide CLINT based IPI operations so let's remove CLINT related
> > code f
elect HAVE_ARCH_KASAN if MMU && 64BIT
> + select ARCH_SUPPORTS_ATOMIC_RMW
>
> config ARCH_MMAP_RND_BITS_MIN
> default 18 if 64BIT
> --
> 2.25.1
>
>
Looks good to me.
Reviewed-by: Anup Patel
This is a good candidate for Linux-5.8. Palmer ??
Regards,
Anup
On Tue, Jun 2, 2020 at 1:49 AM Atish Patra wrote:
>
> On Mon, Jun 1, 2020 at 2:16 AM Anup Patel wrote:
> >
> > The RISC-V per-HART local interrupt controller manages software
> > interrupts, timer interrupts, external interrupts (which are routed
> > via the platf
The plic_find_hart_id() can be useful to other interrupt controller
drivers (such as RISC-V local interrupt driver) so we rename this
function to riscv_of_parent_hartid() and place it in arch directory
along with riscv_of_processor_hartid().
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
ng routine
- Removed patch for GENERIC_IRQ kconfig options
- Added patch to remove do_IRQ() function
- Rebased upon Atish's SMP patches
Anup Patel (6):
RISC-V: self-contained IPI handling routine
RISC-V: Rename and move plic_find_hart_id() to arch directory
irqchip: RISC-V per-HART local interrupt
m IRQCHIP drivers.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
---
arch/riscv/include/asm/irq.h | 1 -
arch/riscv/include/asm/smp.h | 3 +++
arch/riscv/kernel/irq.c | 16 ++--
arch/riscv/kernel/smp.c | 11 ++
-off-by: Palmer Dabbelt
Signed-off-by: Anup Patel
Acked-by: Palmer Dabbelt
---
arch/riscv/Kconfig| 1 +
arch/riscv/include/asm/irq.h | 2 -
arch/riscv/kernel/irq.c | 33 +--
arch/riscv/kernel/traps.c | 2 -
drivers/irqchip/Kconfig | 13
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/include
The only thing do_IRQ() does is call handle_arch_irq function
pointer. We can very well call handle_arch_irq function pointer
directly from assembly and remove do_IRQ() function hence this
patch.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/kernel/entry.S | 4 +++-
arch
The RISC-V per-HART local interrupt controller driver is mandatory
for all RISC-V system (with/without MMU) hence we force select it
for CONFIG_RISCV (just like RISCV_TIMER).
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff
On Mon, Jun 1, 2020 at 1:11 PM Marc Zyngier wrote:
>
> On 2020-06-01 05:09, Anup Patel wrote:
> > On Sun, May 31, 2020 at 4:23 PM Marc Zyngier wrote:
> >>
> >> On 2020-05-31 11:06, Anup Patel wrote:
>
> [...]
>
> > Also, the PLIC spec is now owne
: add STRICT_KERNEL_RWX support")
Cc: sta...@vger.kernel.org
Signed-off-by: Anup Patel
---
Changes since v1:
- Updated free_initmem() is same as generic free_initmem() defined in
init/main.c so we completely remove free_initmem() from arch/riscv
---
arch/riscv/mm/init.c | 11 ---
1 fi
On Sun, May 31, 2020 at 3:28 PM Anup Patel wrote:
>
> The head text section (i.e. _start, secondary_start_sbi, etc) and the
> init section fall under same page table level-1 mapping.
>
> Currently, the runtime CPU hotplug is broken because we are marking
> init section as no
On Sun, May 31, 2020 at 4:23 PM Marc Zyngier wrote:
>
> On 2020-05-31 11:06, Anup Patel wrote:
> > On Sun, May 31, 2020 at 3:03 PM Marc Zyngier wrote:
> >>
> >> On 2020-05-31 06:36, Anup Patel wrote:
> >> > On Sat, M
On Sun, May 31, 2020 at 3:03 PM Marc Zyngier wrote:
>
> On 2020-05-31 06:36, Anup Patel wrote:
> > On Sat, May 30, 2020 at 5:31 PM Marc Zyngier wrote:
>
> [...]
>
> >> > plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
> >>
> >
: add STRICT_KERNEL_RWX support")
Cc: sta...@vger.kernel.org
Signed-off-by: Anup Patel
---
arch/riscv/mm/init.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 736de6c8739f..e0f8ccab8a41 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv
On Sat, May 30, 2020 at 5:11 PM Marc Zyngier wrote:
>
> On 2020-05-30 11:07, Anup Patel wrote:
> > Instead of directly calling RISC-V timer interrupt handler from
> > RISC-V local interrupt conntroller driver, this patch implements
> > RISC-V timer interrupt as a per-CPU
On Sat, May 30, 2020 at 5:31 PM Marc Zyngier wrote:
>
> On 2020-05-30 11:07, Anup Patel wrote:
> > The RISC-V per-HART local interrupt controller manages software
> > interrupts, timer interrupts, external interrupts (which are routed
> > via the platform level interrupt c
The plic_find_hart_id() can be useful to other interrupt controller
drivers (such as RISC-V local interrupt driver) so we rename this
function to riscv_of_parent_hartid() and place it in arch directory
along with riscv_of_processor_hartid().
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
Dabbelt
Signed-off-by: Palmer Dabbelt
Signed-off-by: Anup Patel
Acked-by: Palmer Dabbelt
---
arch/riscv/Kconfig| 1 +
arch/riscv/include/asm/irq.h | 2 -
arch/riscv/kernel/irq.c | 33 +--
arch/riscv/kernel/traps.c | 2 -
drivers/irqchip/Kconfig
The RISC-V per-HART local interrupt controller driver is mandatory
for all RISC-V system (with/without MMU) hence we force select it
for CONFIG_RISCV (just like RISCV_TIMER).
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff
) function
- Rebased upon Atish's SMP patches
Anup Patel (6):
RISC-V: self-contained IPI handling routine
RISC-V: Rename and move plic_find_hart_id() to arch directory
irqchip: RISC-V per-HART local interrupt controller driver
clocksource/drivers/timer-riscv: Use per-CPU timer interrup
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/include
The only thing do_IRQ() does is call handle_arch_irq function
pointer. We can very well call handle_arch_irq function pointer
directly from assembly and remove do_IRQ() function hence this
patch.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/kernel/entry.S | 4 +++-
arch
m IRQCHIP drivers.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
---
arch/riscv/include/asm/irq.h | 1 -
arch/riscv/include/asm/smp.h | 3 +++
arch/riscv/kernel/irq.c | 16 ++--
arch/riscv/kernel/smp.c | 11 ++
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 2458ed31e9b9ab40d78a452ab2650a0857556e85
Gitweb:
https://git.kernel.org/tip/2458ed31e9b9ab40d78a452ab2650a0857556e85
Author:Anup Patel
AuthorDate:Mon, 18 May 2020 14:44:39 +05:30
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 2234ae846ccb9ebdf4c391824cb79e73674dceda
Gitweb:
https://git.kernel.org/tip/2234ae846ccb9ebdf4c391824cb79e73674dceda
Author:Anup Patel
AuthorDate:Mon, 18 May 2020 14:44:40 +05:30
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 0e375f51017bcc86c23979118b10445c424ef5ad
Gitweb:
https://git.kernel.org/tip/0e375f51017bcc86c23979118b10445c424ef5ad
Author:Anup Patel
AuthorDate:Mon, 18 May 2020 14:44:41 +05:30
Committer
et a list of all the relocations, remove from it the relocations
> +# that are known to be legitimate and return this list to arch specific
> +# script that will look for suspicious relocations.
> +
> +objdump="$1"
> +nm="$2"
> +vmlinux="$3"
> +
> +# Remove from the possible bad relocations those that match an undefined
> +# weak symbol which will result in an absolute relocation to 0.
> +# Weak unresolved symbols are of that form in nm output:
> +# " w _binary__btf_vmlinux_bin_end"
> +undef_weak_symbols=$($nm "$vmlinux" | awk '$1 ~ /w/ { print $2 }')
> +
> +$objdump -R "$vmlinux" |
> + grep -E '\ + ([ "$undef_weak_symbols" ] && grep -F -w -v "$undef_weak_symbols" ||
> cat)
> --
> 2.20.1
>
Otherwise, looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
relocation offset
> + * makes the kernel cross over a PGDIR_SIZE boundary, raise a bug
> +* since a part of the kernel would not get mapped.
> +* This cannot happen on rv32 as we use the entire page directory
> level.
> +*/
> + BUG_ON(PGDIR_SIZE - (kernel_virt_addr & (PGDIR_SIZE - 1)) < load_sz);
> +#endif
> + relocate_kernel(load_pa);
> +#endif
> /*
> * Enforce boot alignment requirements of RV32 and
> * RV64 by only allowing PMD or PGD mappings.
> --
> 2.20.1
>
>
Looks good to me as well.
Reviewed-by: Anup Patel
Regards,
Anup
On Fri, May 29, 2020 at 4:40 PM Marc Zyngier wrote:
>
> On 2020-05-29 11:45, Anup Patel wrote:
> > On Fri, May 29, 2020 at 3:39 PM Marc Zyngier wrote:
> >>
> >> On 2020-05-21 14:32, Anup Patel wrote:
>
> [...]
>
> >> > +/* Get the OF de
On Fri, May 29, 2020 at 3:39 PM Marc Zyngier wrote:
>
> On 2020-05-21 14:32, Anup Patel wrote:
> > The RISC-V per-HART local interrupt controller manages software
> > interrupts, timer interrupts, external interrupts (which are routed
> > via the platform level interrupt c
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Palmer Dabbelt
> Sent: 29 May 2020 09:43
> To: a...@brainfault.org
> Cc: Marc Zyngier ; Anup Patel ; Paul
> Walmsley ; a...@eecs.berkeley.edu;
> dani
On Fri, May 29, 2020 at 8:10 AM Palmer Dabbelt wrote:
>
> On Thu, 21 May 2020 06:32:58 PDT (-0700), Anup Patel wrote:
> > The RISC-V per-HART local interrupt controller manages software
> > interrupts, timer interrupts, external interrupts (which are routed
> > via the
On Thu, May 28, 2020 at 12:17 AM Palmer Dabbelt wrote:
>
> On Thu, 21 May 2020 06:32:55 PDT (-0700), Anup Patel wrote:
> > This patchset provides a new RISC-V Local Interrupt Controller Driver
> > for managing per-CPU local interrupts. The overall approach is inspired
> &
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Alex Ghiti
> Sent: 26 May 2020 22:00
> To: Anup Patel
> Cc: Paul Walmsley ; Palmer Dabbelt
> ; Zong Li ; Christoph Hellwig
> ; linux-riscv ; linux-
>
On Sun, May 24, 2020 at 2:45 PM Alexandre Ghiti wrote:
>
> By adding a new 4th level of page table, give the possibility to 64bit
> kernel to address 2^48 bytes of virtual address: in practice, that roughly
> offers ~160TB of virtual address space to userspace and allows up to 64TB
> of physical
>
> Signed-off-by: Alexandre Ghiti
> Reviewed-by: Anup Patel
> Reviewed-by: Palmer Dabbelt
> ---
> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 4
> arch/riscv/kernel/cpu.c| 24 --
> 2 files changed, 13 insertions(+), 15 deleti
asmlinkage void __init setup_vm(uintptr_t dtb_pa)
> load_sz = (uintptr_t)(&_end) - load_pa;
>
> #if defined(CONFIG_64BIT) && !defined(CONFIG_MAXPHYSMEM_2GB)
> - set_satp_mode(load_pa);
> + set_satp_mode(load_pa, dtb_pa);
> #endif
>
> kernel_virt_addr = KERNEL_VIRT_ADDR;
> --
> 2.20.1
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
#endif
> +
> + kernel_virt_addr = KERNEL_VIRT_ADDR;
> +
> va_pa_offset = PAGE_OFFSET - load_pa;
> va_kernel_pa_offset = kernel_virt_addr - load_pa;
> -
> pfn_base = PFN_DOWN(load_pa);
>
> #ifdef CONFIG_RELOCATABLE
> @@ -473,15 +596,22 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
>
> /* Setup early PGD for fixmap */
> create_pgd_mapping(early_pg_dir, FIXADDR_START,
> - (uintptr_t)fixmap_pgd_next, PGDIR_SIZE,
> PAGE_TABLE);
> + fixmap_pgd_next, PGDIR_SIZE, PAGE_TABLE);
>
> #ifndef __PAGETABLE_PMD_FOLDED
> - /* Setup fixmap PMD */
> + /* Setup fixmap PUD and PMD */
> + if (pgtable_l4_enabled)
> + create_pud_mapping(fixmap_pud, FIXADDR_START,
> + (uintptr_t)fixmap_pmd, PUD_SIZE, PAGE_TABLE);
> create_pmd_mapping(fixmap_pmd, FIXADDR_START,
>(uintptr_t)fixmap_pte, PMD_SIZE, PAGE_TABLE);
> +
> /* Setup trampoline PGD and PMD */
> create_pgd_mapping(trampoline_pg_dir, kernel_virt_addr,
> - (uintptr_t)trampoline_pmd, PGDIR_SIZE, PAGE_TABLE);
> + trampoline_pgd_next, PGDIR_SIZE, PAGE_TABLE);
> + if (pgtable_l4_enabled)
> + create_pud_mapping(trampoline_pud, kernel_virt_addr,
> + (uintptr_t)trampoline_pmd, PUD_SIZE, PAGE_TABLE);
> create_pmd_mapping(trampoline_pmd, kernel_virt_addr,
>load_pa, PMD_SIZE, PAGE_KERNEL_EXEC);
> #else
> @@ -558,12 +688,13 @@ static void __init setup_vm_final(void)
>
> vm_area_add_early(_kernel);
>
> - /* Clear fixmap PTE and PMD mappings */
> + /* Clear fixmap page table mappings */
> clear_fixmap(FIX_PTE);
> clear_fixmap(FIX_PMD);
> + clear_fixmap(FIX_PUD);
>
> /* Move to swapper page table */
> - csr_write(CSR_SATP, PFN_DOWN(__pa_symbol(swapper_pg_dir)) |
> SATP_MODE);
> + csr_write(CSR_SATP, PFN_DOWN(__pa_symbol(swapper_pg_dir)) |
> satp_mode);
> local_flush_tlb_all();
> }
>
> --
> 2.20.1
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
VMEMMAP
> + address_markers[VMEMMAP_START_NR].start_address = VMEMMAP_START;
> + address_markers[VMEMMAP_END_NR].start_address = VMEMMAP_END;
> +#endif
> + address_markers[VMALLOC_START_NR].start_address = VMALLOC_START;
> + address_markers[VMALLOC_END_NR].start_address = VMALLOC_END;
> + address_markers[PAGE_OFFSET_NR].start_address = PAGE_OFFSET;
> +
> for (i = 0; i < ARRAY_SIZE(pg_level); i++)
> for (j = 0; j < ARRAY_SIZE(pte_bits); j++)
> pg_level[i].mask |= pte_bits[j].mask;
> --
> 2.20.1
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> -Original Message-
> From: Daniel Lezcano
> Sent: 22 May 2020 18:38
> To: Anup Patel ; Palmer Dabbelt
> ; Paul Walmsley ; Albert
> Ou ; Thomas Gleixner ; Jason
> Cooper ; Marc Zyngier
> Cc: Atish Patra ; Alistair Francis
> ; Anup Patel ; linux-
> ri
On Fri, May 22, 2020 at 3:36 AM Palmer Dabbelt wrote:
>
> On Mon, 18 May 2020 02:14:40 PDT (-0700), Anup Patel wrote:
> > For multiple PLIC instances, the plic_init() is called once for each
> > PLIC instance. Due to this we have two issues:
> > 1. cpuhp_setup_state()
On Fri, May 22, 2020 at 3:36 AM Palmer Dabbelt wrote:
>
> On Mon, 18 May 2020 02:14:39 PDT (-0700), Anup Patel wrote:
> > For multiple PLIC instances, each PLIC can only target a subset of
> > CPUs which is represented by "lmask" in the "struct plic_priv&quo
On Fri, May 22, 2020 at 11:59 AM Sean Anderson wrote:
>
> On 5/22/20 1:54 AM, Anup Patel wrote:
> > On Fri, May 22, 2020 at 1:35 AM Sean Anderson wrote:
> >>
> >> On 5/21/20 9:45 AM, Anup Patel wrote:
> >>> +Required properties:
> >>> +- comp
On Fri, May 22, 2020 at 1:35 AM Sean Anderson wrote:
>
> On 5/21/20 9:45 AM, Anup Patel wrote:
> > We add DT bindings documentation for CLINT device.
> >
> > Signed-off-by: Anup Patel
> > ---
> > .../bindings/timer/sifive,clint.txt | 33 +++
We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel
---
.../bindings/timer/sifive,clint.txt | 33 +++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
diff --git a/Documentation
We add mechanism to set custom IPI operations so that CLINT driver
from drivers directory can provide custom IPI operations.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/smp.h | 11
arch/riscv/kernel/smp.c | 52
arch/riscv/kernel
We will be having separate CLINT timer driver which will also
provide CLINT based IPI operations so let's remove CLINT related
code from arch/riscv directory.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/clint.h | 39 --
arch/riscv/kernel/Makefile | 2
i.e. NoMMU)
Anup Patel (5):
RISC-V: Add mechanism to provide custom IPI operations
RISC-V: Remove CLINT related code
clocksource/drivers/timer-riscv: Remove MMIO related stuff
clocksource/drivers: Add CLINT timer driver
dt-bindings: timer: Add CLINT bindings
.../bindings/timer/sifive
compare
register for clockevent device.
This patch removes MMIO related stuff from RISC-V timer driver
so that we can have a separate CLINT timer driver.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig| 2 +-
arch/riscv/include/asm/timex.h| 28
The TIME CSR and SBI calls are not available in RISC-V M-mode so we
add CLINT driver for Linux RISC-V M-mode (i.e. RISC-V NoMMU kernel).
Signed-off-by: Anup Patel
---
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-clint.c | 226
The only thing do_IRQ() does is call handle_arch_irq function
pointer. We can very well call handle_arch_irq function pointer
directly from assembly and remove do_IRQ() function hence this
patch.
Signed-off-by: Anup Patel
---
arch/riscv/kernel/entry.S | 4 +++-
arch/riscv/kernel/irq.c | 6
The RISC-V per-HART local interrupt controller driver is mandatory
for all RISC-V system (with/without MMU) hence we force select it
for CONFIG_RISCV (just like RISCV_TIMER).
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/irq.h | 2
The plic_find_hart_id() can be useful to other interrupt controller
drivers (such as RISC-V local interrupt driver) so we rename this
function to riscv_of_parent_hartid() and place it in arch directory
along with riscv_of_processor_hartid().
Signed-off-by: Anup Patel
---
arch/riscv/include/asm
m IRQCHIP drivers.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/irq.h | 1 -
arch/riscv/include/asm/smp.h | 3 +++
arch/riscv/kernel/irq.c | 16 ++--
arch/riscv/kernel/smp.c | 11 +--
4 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/
h for self-contained IPI handling routine
- Removed patch for GENERIC_IRQ kconfig options
- Added patch to remove do_IRQ() function
- Rebased upon Atish's SMP patches
Anup Patel (6):
RISC-V: self-contained IPI handling routine
RISC-V: Rename and move plic_find_hart_id() to arch directory
irqch
Signed-off-by: Palmer Dabbelt
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/irq.h | 2 -
arch/riscv/kernel/irq.c| 33 +-
arch/riscv/kernel/traps.c | 2 -
drivers/irqchip/Kconfig
On Tue, May 19, 2020 at 7:21 PM Daniel Lezcano
wrote:
>
> On 19/05/2020 14:39, Kefeng Wang wrote:
> >
> > On 2020/5/19 4:23, Daniel Lezcano wrote:
> >> Hi Kefeng,
> >>
> >> On 18/05/2020 17:40, Kefeng Wang wrote:
> >>> On 2020/5/18 22:09, Daniel Lezcano wrote:
> On 13/05/2020 23:14, Palmer
We improve PLIC banner to help distinguish multiple PLIC instances
in boot time prints.
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c
b/drivers/irqchip/irq-sifive-plic.c
.
This patch fixes both above issues.
Fixes: f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs")
Cc: sta...@vger.kernel.org
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drive
tiple PLIC instances. To fix this, we now set "lmask" as the
default irq affinity in for each interrupt in plic_irqdomain_map().
Fixes: f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs")
Cc: sta...@vger.kernel.org
Signed-off-by: Anup Patel
---
drivers/irqchip/i
://github.com/avpatel/qemu.git
Changes since v1:
- Re-arranged PATCHs to have fixes first
- Added Fixes tag to PATCH1 and PATCH2
- Use %pOFP in boot print to distinguish PLIC instance
Anup Patel (3):
irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()
irqchip/sifive-plic: Setup cpuhp
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